KR20220010699A - Memory device comprising bitline sense amplifier and operating method thereof - Google Patents

Abstract

A memory device and a method of operating the same are provided. The memory device comprises: a bit line detection amplifier coupled to a bit line coupled to a memory cell and a complementary bit line and configured to detect and amplify a voltage difference by developing a voltage of the bit line and a voltage of the complementary bit line; and a detection amplifier driving circuit. The detection amplifier driving circuit includes: a pull-up circuit, in response to a first pull-up pulse, adjusting a level of a bit line low level voltage developed by the bit line detection amplifier to be higher than a level of a ground voltage; a pull-down circuit, in response to a pull-down pulse, adjusting a level of the bit line low level voltage adjusted by the pull-up circuit to be equal to the level of the ground voltage; and a pulse generator generating the first pull-up pulse and the pull-down pulse based on a command received from a host. The present invention can reduce a current leakage of a memory cell array.

Description

MEMORY DEVICE COMPRISING BITLINE SENSE AMPLIFIER AND OPERATING METHOD THEREOF

The present invention relates to a memory device and an operating method thereof, and more particularly, to a memory device including a bit line sense amplifier and an operating method thereof.

A memory cell array included in a memory device implemented as a dynamic random access memory (DRAM) may be connected to a bit line sense amplifier through a bit line and a complementary bit line. The bitline sense amplifier may sense a voltage difference between the bitline and the complementary bitline, and amplify the sensed voltage difference. Based on the sensing and amplifying operations of the bit line sense amplifier, data stored in the memory cell array may be read.

When the bit line sense amplifier senses the voltage difference between the bit line and the complementary bit line, noise may be generated in memory cells that are not to be sensed. Due to such noise, an error may occur in data stored in memory cells that are not to be detected. Accordingly, the reliability of the DRAM may be deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device including a bit line sense amplifier and a method of operating the same.

A memory device according to an embodiment of the present invention includes: a bit line sense amplifier connected to a bit line connected to a memory cell and a complementary bit line, and sensing and amplifying a voltage difference between a voltage of a bit line and a voltage of a complementary bit line; It may include a sense amplifier driving circuit. The sense amplifier driving circuit may adjust the level of the bit line low level voltage sensed by the bit line sense amplifier to be higher than the level of the ground voltage in response to a command received from the host.

A memory device according to another embodiment of the present invention may include: a bit line sense amplifier and a sense amplifier driving circuit connected to a bit line connected to a memory cell and a complementary bit line, and configured to sense and amplify data stored in the memory cell have. The sense amplifier driving circuit generates a first pull-up pulse and a pull-down pulse based on a command received from a host, and in response to the first pull-up pulse and the pull-down pulse, a bit line low voltage developed by the bit line sense amplifier. level can be adjusted. The level of the bit line low voltage may be higher than the ground voltage by a delta voltage when a read operation is performed on the memory cell, and may be equal to the ground voltage when a write operation is performed on the memory cell.

According to another embodiment of the present invention, a method of operating a memory device including a bit line sense amplifier includes: sensing data stored in a target memory cell among a plurality of memory cells, and first data to be stored in the target memory cell is not input to the memory device, restoring data stored in the target memory cell and increasing the voltage level of the first node of the bitline sense amplifier from a ground voltage, and the first data to be stored in the target memory cell is When input to the memory device, the method may include reducing the voltage level of the first node of the bit line sense amplifier to a ground voltage while writing the first data to the target memory cell. Each of the plurality of memory cells may include a transistor having a floating body structure.

According to an embodiment of the present invention, the low level of the voltage developed by the bit line sense amplifier may be adjusted to be greater than or equal to the ground voltage based on a command received from an external device. Accordingly, the amount of leakage current of the memory cell array due to the operation of the bit line sense amplifier may be reduced. In addition, loss of data stored in the memory cell array can be prevented.

1 exemplarily shows a block diagram of a memory device according to an embodiment of the present invention.
FIG. 2 illustrates a portion of a block diagram of the memory device of FIG. 1 in more detail.
FIG. 3 exemplarily shows a block diagram of the sense amplifier unit of FIG. 1 .
FIG. 4 exemplarily shows a circuit diagram of the bit line sense amplifier driving circuit of FIG. 3 .
5 exemplarily shows a timing diagram of a waveform of a signal applied to the bit line sense amplifier driving circuit of FIG. 3, signals used in the bit line sense amplifier driving circuit, a voltage of a bit line, and a voltage of a complementary bit line do.
6A illustrates the pull-up circuit of FIG. 4 in more detail, according to an embodiment of the present invention.
6B illustrates the pull-up circuit of FIG. 4 in more detail, according to another embodiment of the present invention.
7 exemplarily shows a block diagram of the pulse generator of FIG. 4 .
8 is an exemplary flowchart of a method of operating a memory device according to an embodiment of the present invention.
9 exemplarily shows a flowchart of a method of operating a system including a memory device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In order to facilitate the overall understanding in describing the present invention, similar reference numerals are used for similar components in the drawings, and duplicate descriptions of similar components are omitted.

1 exemplarily shows a block diagram of a memory device according to an embodiment of the present invention. 1 , the memory device 10 includes a control logic 11 , a memory cell array 12 , a row decoder 13 , a column decoder 14 , an input/output buffer 15 , a voltage generator 16 , and It may include a sense amplifier unit 100 . According to an embodiment, the memory device 10 may be implemented as a dynamic random access memory (DRAM).

The control logic 11 may receive a command/address CA and a clock CK from a device (which may be referred to as a host, CPU, memory controller, etc.) external to the memory device 10 . The command/address CA is a command (command) indicating an operation to be performed by the memory device 10 , and a memory cell that is a target of an operation to be performed by the memory device 10 (hereinafter, a target memory cell (hereinafter) It may include a row address (ADDR_R) indicating a row of a target memory cell) and a column address (ADDR_C) indicating a column of a target memory cell. The control logic 11 may transmit the row address ADDR_R to the row decoder 13 , and may transmit the column address ADDR_C to the column decoder 14 .

The control logic 11 may decode the received command/address CA. For example, the control logic 11 may include a decoder that decodes the received command/address CA. The control logic 11 may receive an active command, a read/write command, a PRECHARGE command, and the like from the host, and decode the received commands. . The control logic 11 generates a word line active signal WLACT, a write enable signal WREN, and a precharge signal PRCG based on the decoding result, and generates the generated signal by the sense amplifier unit 100 . can be sent to For example, the word line active signal WLACT may be generated in response to an active command, the write enable signal WREN may be generated in response to a write command, and the precharge signal PRCG may be a precharge command. can be created in response to

The memory cell array 12 may include a plurality of memory cells (eg, MC1/MC2/MC3 of FIG. 2 ). For example, each of the memory cells included in the memory cell array 12 may be disposed at a point where the plurality of word lines WL and the plurality of bit lines BL intersect. Each of the memory cells may be connected to a corresponding word line among the plurality of word lines WL. Each of the memory cells may be connected to a corresponding bit line of the plurality of bit lines BL and a corresponding complementary bit line of the plurality of complementary bit lines BLB. Each of the memory cells may be provided in a matrix form. In this case, the plurality of word lines WL may be connected to rows of memory cells, and the plurality of bit lines BL and the plurality of complementary bit lines BLB may be connected to columns of memory cells. The memory cell array 12 will be described in more detail below with reference to FIG. 2 .

The row decoder 13 may receive a row address ADDR_R from the control logic 11 . The row decoder 13 may be connected to the memory cell array 12 through a plurality of word lines WL. The row decoder 13 may select one of the plurality of word lines WL connected to the memory cell array 12 by decoding the received row address ADDR_R. The row decoder 13 may activate the selected word line by applying a voltage to the selected word line.

The column decoder 14 may receive the column address ADDR_C from the control logic 11 . The column decoder 14 may be connected to the sense amplifier unit 100 through a column selection line CSL. The column decoder 14 decodes the received column address ADDR_C to select a read unit bit line(s) and a complementary bit line(s) from among a plurality of bit lines BL connected to the memory cell array 12 . can The column decoder 14 may select (or activate) the bit line and the complementary bit line by applying a voltage to the bit line and the complementary bit line through the column select line CSL.

When the memory device 10 performs a write operation in response to the command/address CA, the input/output buffer 15 may receive data DQ from an external device. The input/output buffer 15 may temporarily store the received data DQ. The input/output buffer 15 may transmit the stored data DQ to the sense amplifier unit 100 .

When the memory device 10 performs a read operation in response to the command/address CA, the input/output buffer 15 receives data sensed by the sense amplifier unit 100 and stored in the memory cell array 12 . receive, and temporarily store the received data. Data temporarily stored in the input/output buffer 15 and stored in the memory cell array 12 may be output to the external device in response to a request from the external device.

The voltage generator 16 may generate various voltages that may be used within the memory device 10 . For example, the voltage generator 16 may receive an external voltage VEXT from an external device of the memory device 10 . The voltage generator 16 may generate an internal voltage VINTA and a pull-up reference voltage VREF_PU based on the external voltage VEXT. For example, the internal voltage VINTA may be applied to the memory cell array 12 .

The sense amplifier unit 100 may sense data stored in the memory cell array 12 , amplify a voltage corresponding to the sensed data, and output the amplified data to an external device in response to a request from the external device. . For example, the sense amplifier unit 100 is stored in the target memory cell based on the signals WLACT, WREN, PRCG received from the control logic 11 and the voltages VINTA and VREF_PU received from the voltage generator. data can be detected. A specific operation of the sense amplifier unit 100 will be described later.

FIG. 2 illustrates a portion of a block diagram of the memory device of FIG. 1 in more detail. 1 and 2 , the memory device 10 includes a memory cell array 12 in which a plurality of memory cells are arranged, a sense amplifier unit 100 connected to the memory cell array 12 , and a column selection line CSL. It may include a plurality of transistors CST connected to , and an input/output buffer 15 . FIG. 2 illustrates some components of the memory device 10 , and the components included in the memory device 10 are not limited to those shown in FIG. 2 .

Each memory cell included in the memory cell array 12 may include a transistor and a capacitor. For example, the first memory cell MC1 includes a transistor TR1 including a gate connected to the word line WL0, a first terminal connected to the bit line BL, and a second terminal connected to the capacitor CS1. may include The first memory cell MC1 has a first terminal connected to the second terminal of the transistor TR1 and a ground voltage (GND or VSS) or a plate voltage (Vp; for example, 1/2 VINTA, or a specific (or preset) ) may include a capacitor CS1 including a second terminal connected to the voltage). In a similar manner, the second memory cell MC2 may include a transistor TR2 and a capacitor CS2 connected to the word line WL1 and the bit line BL, and the third memory cell MC3 may include a word It may include a transistor TR3 and a capacitor CS3 connected to the line WL2 and the bit line BL.

Memory cells connected to the complementary bit line BLB may have the same structures as memory cells connected to the bit line BL. In order to avoid unnecessarily complicating the drawing, the memory cells of the bit line BL and the memory cells of the complementary bit line BLB are shown to be adjacent to each other. However, the bit lines BL may be disposed in the first array, and the complementary bit lines BLB may be disposed in the second array. The sense amplifier unit 100 may be disposed between the first array and the second array. The bit line BL may extend toward the first array to be connected to the memory cells, and the complementary bit line BLB may extend toward the second array to be connected to the memory cells.

Each of the plurality of memory cells may store data DQ input from the external device in response to a command/address CA received from the external device. For example, when the external device wants to store data '1' in the first memory cell MC1 , the external device has a row address ADDR_R, a column address ADDR_C, and A command/address CA including a write command and data DQ including data '1' may be transmitted to the memory device 10 . The memory device 10 may charge a voltage corresponding to data '1' in the capacitor CS1 included in the first memory cell MC1 in response to the received command/address CA and data DQ. have.

Memory cells connected to the complementary bit line BL may store data complementary to the memory cells connected to the bit line BL. When data '1' is stored in a specific memory cell of the bit line BL, data '0' may be stored in a corresponding memory cell of the complementary bit line BLB. Similarly, when data '0' is stored in a specific memory cell of the bit line BL, data '1' may be stored in a corresponding memory cell of the complementary bit line BLB.

In the illustrated embodiment, one pair of a bit line BL and a complementary bit line BLB is illustrated. However, a plurality of pairs of the bit line BL and the complementary bit line BLB may be provided and may be connected to a plurality of memory cells.

In the illustrated embodiment, the memory cell array 12 may further include a device isolation layer TRENCH. The device isolation layer TRENCH may isolate each of the plurality of memory cells included in the memory cell array 12 from each other. For example, the first memory cell MC1 may be electrically isolated from each other by the second memory cell MC2 and the device isolation layer TRENCH. The device isolation layer TRENCH may be implemented as an insulator.

In the illustrated embodiment, the transistors included in each of the plurality of memory cells may have a floating body structure. For example, no voltage may be applied to the body (or the substrate, bulk) of the transistor TR1 included in the first memory cell MC1 . For example, the body of the transistor TR1 may be electrically floating. However, the disclosed invention is not limited to the illustrated embodiment, and a voltage may be applied to the body of the transistor included in the memory cell unlike the illustrated embodiment.

The sense amplifier unit 100 may include a bit line sense amplifier driving circuit 110 , a bit line sense amplifier 120 , and a voltage equalization circuit 130 . The bit line sense amplifier 120 may sense and amplify a voltage corresponding to data stored in a capacitor included in a target memory cell among a plurality of memory cells under the control of the bit line sense amplifier driving circuit 110 . In other words, the bit line sense amplifier 120 may read data stored in the memory cell array 12 , amplify the read data, and temporarily store the data stored in the memory cell array 12 under the control of the bit line sense amplifier driving circuit 110 . Specific operations of the bit line sense amplifier 120 and the bit line sense amplifier driving circuit 110 will be described later.

The voltage equalization circuit 130 may equalize the voltage applied to the pair of the bit line BL and the complementary bit line BLB before the sensing operation of the bit line sense amplifier 120 . For example, in response to a precharge command received from an external device, the voltage equalization circuit 130 converts the precharge voltage (eg, 1/2 of the driving voltage supplied to the memory device 10) to the bit line ( BL) can be transmitted. Accordingly, the bit line BL may be pre-charged with the pre-charge voltage.

The column selection line CSL may be connected to a gate of each of the plurality of transistors CST. The column selection line CSL may turn on a transistor CST corresponding to a column (or bit line) connected to a target memory cell in response to a command/address CA received from an external device. Accordingly, the voltage sensed and amplified by the bit line sense amplifier 120 (ie, data stored in the target memory cell) may be transmitted to the input/output buffer 15 through the turned-on transistor CST.

In an embodiment, only the word line WL0 of FIG. 2 may be activated in response to the command/address CA, and the word lines WL1 and WL2 may not be activated. That is, a voltage sufficiently high enough to turn on the transistor TR1 may be supplied to the word line WL0, and a voltage smaller than that may be supplied to the word lines WL1 and WL2. Accordingly, the transistor TR1 connected to the word line WL0 may be turned on, and the transistors TR2 and TR3 may not be turned on.

After the word line WL0 is activated, the bit line BL and the complementary bit line BLB may be developed by the sense amplifier unit 100 . For example, the voltages of the bit line BL and the complementary bit line BLB may be a power supply voltage or a ground voltage. For example, assuming that the second memory cell MC2 stores data '0' and the third memory cell MC3 stores data '1', the capacitor CS2 stores data '0'. It may be charged to a corresponding voltage (or not charged at all), and the capacitor CS3 may be charged to a voltage corresponding to data '1'.

Since the transistors TR2 and TR3 are not turned on, channels are not formed in the transistors TR2 and TR3. At this time, a voltage corresponding to data '1', for example, a power supply voltage, is charged in the capacitor CS3 , and the voltage of the word line WL2 is lower than the threshold (threshold) voltage of the transistor TR3 . Due to this, a hole may be generated due to gate induced drain leakage (GIDL) on the surface or curved surface of the drain terminal of the transistor TR3 , and the hole may be injected into the body of the transistor TR3 .

In the illustrated embodiment, the transistors TR2 and TR3 may have a floating body structure. Accordingly, holes generated by the GIDL may be accumulated in the floating body of the transistor TR3 . The potential (or voltage) of the body of the transistor TR3 may increase due to the accumulated holes. When a ground voltage is applied to the source terminal of the transistor TR3 (eg, the terminal connected to the bit line BL in the illustrated embodiment) due to the raised body potential, the source terminal of the transistor TR3 and A forward-biased PN junction may occur between the bodies.

When a voltage corresponding to data '1' is applied to the drain terminal of the transistor TR3 due to the capacitor CS3 and a voltage lower than the threshold voltage of the transistor TR3 is applied to the gate of the transistor TR3, the transistor ( A reverse-biased PN junction occurs between the drain end of TR3 and the body. Due to the forward biased PN junction between the source terminal and the body of the transistor TR3 and the reverse biased PN junction between the drain terminal and the body of the transistor TR3, the parasitic BJT condition may be satisfied. For example, the terminal connected to the capacitor CS3 of the transistor TR3 is an emitter terminal, the body of the transistor TR3 is a base terminal, and the bit line BL of the transistor TR3 is used. The stage connected to may operate as a collector stage. Accordingly, the transistor TR3 may operate as an npn-type BJT, and charges may move from the emitter end of the transistor TR3 through the base end to the collector end. As a result, the charge stored in the capacitor CS3 connected to the source terminal of the transistor TR3 leaks, so that the data '1' stored in the third memory cell MC3 may be lost.

The memory device according to an embodiment of the present invention may maintain the low level of the voltage developed by the bit line sense amplifier to be higher than the ground voltage for a predetermined time during the operation of the bit line sense amplifier. Since the potential of the source terminal of the transistor included in the memory cell is maintained higher than the ground voltage, the above-described GIDL phenomenon can be improved. In addition, the amount of holes accumulated in the body of the transistor of the floating body structure can be reduced, and the reverse bias PN junction between the end to which the bit line is connected and the body can be maintained. As a result, the amount of leakage current of the memory cells of the memory cell array 12 can be reduced, and loss of data stored in the memory cells of the memory cell array 12 can be prevented. Accordingly, the reliability of the memory device 10 may be improved.

FIG. 3 exemplarily shows a block diagram of the sense amplifier unit of FIG. 1 . 1 to 3 , the sense amplifier unit 100 may include a bit line sense amplifier 120 and a bit line sense amplifier driving circuit 110 . For convenience of illustration, other components (eg, voltage equalization circuit 130) and peripheral components (eg, column decoder 14) of the sense amplifier unit 100 described above in FIG. 2 ) is not shown in FIG. 3 .

The bit line sense amplifier driving circuit 110 may include a regulator 111 , a pull-up circuit 112 , a pull-down circuit 113 , and a pulse generator 114 . The bit line sense amplifier driving circuit 110 may be connected to the node LAB of the bit line sense amplifier 120 . The bit line sense amplifier driving circuit 110 is based on the internal voltage VINTA, the pull-up reference voltage VREF_PU, the word line active signal WLACT, the write enable signal WREN, and the precharge signal PRCG, The voltage VLAB may be provided to the node LAB. Accordingly, the level of the voltage (ie, VLAB) of the node LAB may be equal to or higher than the ground voltage VSS. In other words, the bit line sense amplifier driving circuit 110 may pull up the voltage VLAB of the node LAB to be higher than the ground voltage VSS or pull down the voltage VLAB to be equal to the ground voltage VSS.

In the illustrated embodiment, the bit line sense amplifier driving circuit 110 includes the pull-down circuit 113 , but another embodiment of the present invention may not include the pull-down circuit 113 . In this embodiment, the bit line sense amplifier driving circuit 110 may not pull down the voltage VLAB of the node LAB. Alternatively, the voltage VLAB may be pulled down to the ground voltage VSS based on the operation of the transistor MLAB1 to be described later.

The bit line sense amplifier 120 may include transistors MP, MN, MSP1, MSP2, MSN1, MSN2, and MLAB1. The bit line sense amplifier 120 may include a first sensing unit PSA and a second sensing unit NSA. The first sensing unit PSA may include transistors MSP1 and MSP2. The second sensing unit NSA may include transistors MSN1 and MSN2 . The transistors MSP1 and MSP2 of the first sensing unit PSA may be implemented as PMOS. The transistors MSN1 and MSN2 of the second sensing unit NSA may be implemented as NMOS.

Transistor MN has a first stage (eg, drain) to which internal voltage VINTA is applied from voltage generator 16 , and a gate to which bit line sense amplifier enable signal BLSA_EN is applied from pulse generator 114 . , and a second end (eg, a source) connected to the node LA. In the illustrated embodiment, the transistor MN may be implemented as an NMOS.

The transistor MSP1 has a first terminal (eg, source) connected to the node LA, a gate connected to a complementary bit line BLB, and a second terminal (eg, drain) connected to the bit line BL. may include The transistor MSP2 has a first end (eg, source) connected to a node LA, a gate connected to a bit line BL, and a second end (eg, drain) connected to a complementary bit line BLB. may include The transistor MSN1 has a first end (eg, drain) connected to a bit line BL, a gate connected to a complementary bit line BLB, and a second terminal (eg, source) connected to a node LAB. may include Transistor MSN2 has a first end (eg, drain) connected to a complementary bit line BLB, a gate connected to bit line BL, and a second terminal (eg, source) connected to node LAB. may include

The first sensing unit PSA and the second sensing unit NSA may sense data stored in memory cells to which the bit line pair BL and BLB are connected. Specific operations of the first sensing unit PSA and the second sensing unit NSA will be described later.

Due to charge sharing between the bit line BL and the first memory cell MC1 , the voltage level of the bit line BL may vary from the precharge voltage charged by the voltage equalization circuit 130 . . The first sensing unit PSA and the second sensing unit NSA may detect a change in the voltage level of the bit line BL.

Transistor MP has a first stage (eg, source) to which internal voltage VINTA is applied from voltage generator 16 , a gate to which develop signal LAPG is applied from pulse generator 114 , and a node ( A second end (eg, a drain) connected to LA) may be included. In the illustrated embodiment, the transistor MP may be implemented as a PMOS.

The transistor MLAB1 has a first terminal (eg, a drain) connected to the node LAB of the bit line sense amplifier 120 , a gate to which the develop signal LANG is applied from the pulse generator 114 , and a ground voltage. It may include a second stage (eg, a source) to which (VSS) is applied.

The regulator 111 of the bit line sense amplifier driving circuit 110 is a voltage supplied to the pull-up circuit 112 based on the internal voltage VINTA and the pull-up reference voltage VREF_PU (eg, the pull-up gate voltage of FIG. 4 ). (PU_N)) level can be adjusted. The pull-up circuit 112 may increase the level of the voltage VLAB based on the voltage supplied from the regulator 111 and the signal applied from the pulse generator 114 . The pull-down circuit 113 may reduce the level of the voltage VLAB to the same level as the ground voltage VSS based on the signal applied from the pulse generator 114 . The pulse generator 114 receives various signals (eg, a bit line sense amplifier enable signal) used in the sense amplifier unit 100 based on the signals WLACT, WREN, and PRCG received from the control logic 11 . (BLSA_EN), develop signals (LAPG, LANG, etc.) may be generated. Specific operations of the regulator 111 , the pull-up circuit 112 , the pull-down circuit 113 , and the pulse generator 114 will be described later.

FIG. 4 exemplarily shows a circuit diagram of the bit line sense amplifier driving circuit of FIG. 3 . 1 to 4 , the bit line sense amplifier driving circuit 110 may include a regulator 111 , a pull-up circuit 112 , and a pull-down circuit 113 . For convenience of illustration, illustration of the pulse generator 114 is omitted.

The regulator 111 may include an amplifier AMPR and a transistor MREF. Transistor MREF is connected to a first terminal (eg, a source) to which an internal voltage VINTA is applied from the voltage generator 16 , a gate to which an output terminal of the amplifier AMPR is connected, and a pull-up circuit 112 . A second end (eg, a drain) may be included. In the illustrated embodiment, the transistor MREF may be implemented as a PMOS.

The amplifier AMPR has a first input terminal to which the pull-up reference voltage VREF_PU is applied from the voltage generator 16, a second input terminal connected to a second terminal connected to the pull-up circuit 112 of the transistor MREF, and a transistor ( MREF) may include an output terminal connected to the gate. The pull-up reference voltage VREF_PU may be a DC voltage.

Unlike the illustrated embodiment, according to another embodiment of the present invention, a voltage of a different level from the internal voltage VINTA may be applied from the voltage generator 16 to the first terminal of the transistor MREF. For example, the voltage generator 16 may apply the received external voltage VEXT to the first terminal of the transistor MREF.

In an embodiment, the level of the pull-up reference voltage VREF_PU may be determined based on characteristics of a die (or a chip) on which the memory cell array 12 is implemented. For example, the level of the pull-up reference voltage VREF_PU is a physical characteristic of each of the one or more dies on which the memory cell array 12 is implemented, which may be caused by process, voltage, temperature (PVT) variations. It can be determined that the differences in can cancel each other out. As another example, the level of the pull-up reference voltage VREF_PU may be determined to cancel a process error such as a non-uniform surface or height of a substrate caused during a die manufacturing process in one die.

The pull-up circuit 112 may include inverters INV1 and INV2 , pull-up transistors MPU1 , MPU2 , and MLAB2a , and a delta voltage generator 112_1 . The inverter INV2 may receive the pull-up pulse PU_PULSE from the pulse generator 114 . The inverter INV2 may output a voltage to the inverter INV1 in response to the pull-up pulse PU_PULSE. The inverter INV1 may output the pull-up gate voltage PU_N to the gate of the pull-up transistor MPU2 based on the voltage received from the inverter INV2 and the voltage received from the second terminal of the transistor MREF.

The pull-up transistor MPU1 has a first terminal (eg, drain) to which an internal voltage VINTA is applied from the voltage generator 16 , a gate to which a pull-up pulse PLABUP is applied, and a first of the pull-up transistor MPU2 . It may include a second end (eg, source) connected to the end (eg, drain). In the illustrated embodiment, the pull-up transistor MPU1 may be implemented as an NMOS.

If the pull-up pulse PLABUP is not applied to the gate of the pull-up transistor MPU1 , no current flows from the first end to the second end of the pull-up transistor MPU1 . Accordingly, it is possible to prevent current from leaking from the pull-up transistor MPU1 to the pull-up transistor MPU2 during a period in which the pull-up pulse PLABUP is not applied from the pulse generator 114 . As a result, when the pull-up pulse PLABUP is not applied, leakage of the current based on the internal voltage VINTA to the bit line sense amplifier 120 through the pull-up transistors MPU1 and MPU2 can be prevented.

The pull-up transistor MPU2 includes a first terminal connected to the second terminal of the pull-up transistor MPU1, a gate to which the pull-up gate voltage PU_N is applied, and a first terminal (eg, drain) of the pull-up transistor MLAB2a, and It may include a second end (eg, a source) connected to the node LAB. When the magnitude of the pull-up gate voltage PU_N is greater than the magnitude of the threshold voltage of the pull-up transistor MPU2 , the pull-up transistor MPU2 may be turned on. In the illustrated embodiment, the pull-up transistor MPU2 may be implemented as an NMOS.

The pull-up transistor MLAB2a includes a second end of the pull-up transistor MPU2 and a first end (eg, a drain) connected to the node LAB, a gate to which the pull-up pulse PLABUP is applied, and a delta voltage generator 112_1 ) may include a second end (eg, a source) connected to.

The delta voltage generator 112_1 provides a voltage VLAB higher than the ground voltage VSS by a delta voltage (eg, dVLABa in FIG. 6A or dVLABb in FIG. 6B ) to the node LAB through the pull-up transistor MLAB2a. can do. As a result, the pull-up circuit 112 supplies the voltage generated by the delta voltage generator 112_1 to the node LAB in response to the pull-up pulses PU_PULSE and PLABUP, thereby increasing the voltage VLAB of the node LAB. It can be pulled from the ground voltage to a voltage greater than the ground voltage. A detailed operation of the delta voltage generator 112_1 will be described below with reference to FIGS. 6A and 6B .

The pull-down circuit 113 may include a pull-down transistor MPD. The pull-down transistor MPD has a first terminal (eg, drain) connected to the node LAB, a gate to which the pull-down pulse PLABDN is applied from the pulse generator 114, and a second terminal (eg, a ground) connected to the ground voltage. for example, source).

5 exemplarily shows a timing diagram of a waveform of a signal applied to the bit line sense amplifier driving circuit of FIG. 3, signals used in the bit line sense amplifier driving circuit, a voltage of a bit line, and a voltage of a complementary bit line do. FIG. 5 is described with reference to FIGS. 1 to 4 .

In the first phase (Phase1) or the charge sharing operation mode, in response to the command/address CA requesting to activate the word line (eg, WLO), the control logic 11 transmits the word line active signal WLACT ) can be created. In the illustrated embodiment, the high level of the word line active signal WLACT may be maintained for a time tCgShr. In response to the word line active signal WLACT, a voltage VBL pre-charged in the bit line BL and a capacitor (eg, MC1) of a memory cell (eg, MC1) connected to the word line WL0 and the bit line BL. For example, charge sharing may occur between the voltages charged to CS1).

For example, as shown in FIG. 2 , the memory device 10 may receive an access request for the word line WL0 to which the first memory cell MC1 of FIG. 2 is connected from an external device. In this case, the memory device 10 may receive the row address ADDR_R of the first memory cell MC1 and the command/address CA including the active command. In response to the received command/address CA, a voltage higher than the driving voltage of the memory device 10 by the turn-on voltage of a transistor included in each of the memory cells may be supplied to the word line WL0. Accordingly, transistors (eg, TR1 ) connected to the word line WL0 may be turned on.

Assuming that data '1' is stored in the first memory cell MC1, as the transistor TR1 is turned on, the voltage (corresponding to the data '1') charged in the capacitor CS1 is increased in the transistor It may be transmitted to the bit line BL through TR1. On the other hand, if it is assumed that data '0' is stored in the first memory cell MC1 (ie, the capacitor CS1 is not charged), as the transistor TR1 is turned on, the bit line BL ) may be transferred to the capacitor CS1. In other words, as the word line WL0 is activated, a charge is shared between the charge of the bit line BL charged by the voltage equalization circuit 130 and the charge of the capacitor CS1 of the first memory cell MC1 ( charge sharing) may occur.

In the second phase (Phase2) or in the sensing operation mode, after a time tCgShr from the point in time when the word line active signal WLACT changes to the high level, the bit line sense amplifier enable signal BLSA_EN and the develop signal LANG) may have a high level, and the develop signal LAPG may have a low level.

In response to the low level of the develop signal LAPG, the transistor MP of the bit line sense amplifier 120 may be turned on. For example, as shown in FIG. 3 , when the develop signal LAPG is applied to the gate of the transistor MP, the internal voltage VINTA is applied to the first of the bit line sense amplifier 120 through the transistor MP. 1 may be supplied to the sensing unit PSA. Accordingly, the voltage level of the bit line BL may increase. In this case, the increased voltage level of the bit line BL may be a voltage level corresponding to data '1'. In other words, the bit line sense amplifier 120 may develop the voltage of the bit line BL to a voltage corresponding to data '1' in response to the develop signal LAPG.

In response to the high level of the bit line sense amplifier enable signal BLSA_EN, the transistor MN may be turned on. For example, as shown in FIG. 3 , when the bit line sense amplifier enable signal BLSA_EN is applied to the transistor MN, the internal voltage VINTA is applied to the bit line sense amplifier 120 through the transistor MN. can be transmitted to Accordingly, the bit line sense amplifier 120 may be driven.

In response to the develop signal LANG, the transistor MLAB1 may be turned on. Accordingly, the voltage VBL of the bit line BL may rise, and the voltage VBLB of the complementary bit line BLB may fall. (corresponds to data '1')

In a third phase (Phase3), the pull-up pulses PLABUP and PU_PULSE may change from a low level to a high level, and the develop signal LANG may change from a high level to a low level. In response to the pull-up pulse PU_PULSE, the pull-up gate voltage PU_N may be applied to the pull-up transistor MPU2 . For example, a read operation and a write operation may be performed in the third phase (Phase3).

For example, as shown in FIG. 4 , when the pull-up pulse PLABUP is applied to the pull-up transistor MLAB2a, the pull-up transistor MLAB2a may be turned on. Accordingly, the voltage VLAB generated by the delta voltage generator 112_1 may be provided to the node LAB through the pull-up transistor MLAB2a.

In an embodiment, the pull-up pulses PLABUP and PU_PULSE are changed to a high level after at least a time tRCD from a point in time when the pulse generator 114 receives the word line active signal WLACT from the control logic 11 . can The time tRCD may be the time between issuing an active command and issuing a read/write command. The time tRCD may be a time required for the sense amplifier unit 100 to sense and amplify data stored in the first memory cell MC1 . The word line active signal WLACT (eg, for the selected word line WL0) may change to a high level in response to an active command. Accordingly, the time tRCD may be sufficiently guaranteed. The pulse PU_PULSE may have a high level for a time t A. The time tA may be an adjustment delay time delayed by the adjustable delay circuit DA.

In response to the low level of the develop signal LANG, the transistor MLAB1 may be turned off. In response to the pull-up pulses PU_PULSE and PLABUP and the pull-up gate voltage PU_N, the pull-up transistors MPU1 , MPU2 , and MLAB2a may be turned on. Accordingly, the voltage VBLB of the complementary bit line BLB may be raised from the ground voltage GND by the delta voltage dVLAB generated by the delta voltage generator 112_1.

When the pull-up pulse PU_PULSE has a low level again after the time tA has elapsed, the magnitude of the pull-up gate voltage PU_N may be reduced. Accordingly, the pull-up transistor MPU2 may be turned off. When the pull-up transistor MPU2 is turned off, the delta voltage dVLAB may not be supplied to the bit line sense amplifier 120 . Accordingly, the voltage VBLB of the complementary bit line BLB may decrease back to the ground voltage VSS level after a predetermined time elapses.

In response to the command/address CA for writing data to the memory cell (eg, MC1 ) to which the word line (eg, WL0) and the bit line (BL) activated by the word line active signal WLACT are connected Accordingly, the control logic 11 may generate the write enable signal WREN. In response to the write enable signal WREN, the write column select signal WRITE_CSL may be applied to the column select line CSL. In response to the write column selection signal WRITE_CSL, the sense amplifier unit 100 may write new data to the target memory cell. For example, the sense amplifier unit 100 may include a capacitor (eg, MC1) of a memory cell (eg, MC1) connected to a bit line (eg, BL) corresponding to the write column selection signal (WRITE_CSL) among the plurality of bit lines. For example, a voltage corresponding to new data may be charged to CS1).

Alternatively, the sense amplifier unit 100 may restore data stored in each of the memory cells connected to the word line (eg, WL0) activated by the word line active signal WLACT back to each of the memory cells. have. For example, the sense amplifier unit 100 may charge a voltage corresponding to the data sensed by the bit line sense amplifier 120 back to capacitors included in the memory cells, respectively.

In response to the high level of the write column selection signal WRITE_CSL, the level of the voltages VBL/VBLB of the bit line BL or the complementary bit line BLB is grounded for a predetermined time in order to write new data. It may need to be pulled down to the level of voltage VSS. In the illustrated embodiment, the level of the voltage VBLB of the complementary bit line BLB is pulled down to the level of the ground voltage VSS.

After a time tWRITE elapses from a time point when the write column selection signal WRITE_CSL changes to a high level, the pull-up pulse PU_PULSE may have a high level for a time tB. The time tWRITE may be a time required for the sense amplifier unit 100 to write new data to the target memory cell. The time tB may be an adjustment delay time delayed by the adjustable delay circuit DA.

In response to the pull-up pulse PU_PULSE, the pull-up gate voltage PU_N may be applied to the pull-up transistor MPU2 . The pull-up transistor MPU2 may be turned on again in response to the pull-up gate voltage PU_N. Accordingly, the delta voltage dVLAB can be supplied by the delta voltage generator 112_1 to the bitline sense amplifier 120, and consequently the voltage VBLB of the complementary bitline BLB is the delta voltage dVLAB. can be raised again.

In some embodiments, in the third phase (Phase3), the memory device 10 may perform a read operation in response to the command/address CA. For example, the external device may transmit a command/address CA, and the command/address CA may include a read command and a column address ADDR_C indicating the first memory cell. For example, the memory device 10 may perform a read operation in response to the command/address CA. In a read operation, the sense amplifier unit 100 may transmit amplified data of a difference between the voltage of the bit line BL and the complementary bit line BLB to the input/output buffer 15 .

The control logic 11 may transmit the precharge signal PRCG to the sense amplifier unit 100 in response to the command/address CA requesting the precharge operation.

In the fourth phase (Phase4) or in the precharge operation mode, the pull-up pulse PLABUP may change to a low level, and the develop signal LANG and the pull-down pulse PLABDN may have a high level. In response to the high level of the develop signal LANG, the transistor MLAB1 may be turned on. In response to the high level of the pull-down pulse PLABDN, the pull-down transistor MPD may be turned on. For example, when the pull-down pulse PLABDN is applied to the pull-down transistor MPD, the pull-down transistor MPD may be turned on. Accordingly, the voltage VLAB of the node LAB may be brought down to the ground voltage. In other words, the pull-down circuit 113 may pull down the voltage VLAB in response to the pull-down pulse PLABDN received from the pulse generator 114 . As the transistors MLAB1 and MPD are turned on, the voltage VBLB of the complementary bit line BLB may be pulled down to the level of the ground voltage VSS.

In the illustrated embodiment, the develop signal LANG and the pull-down pulse PLABDN may have a high level for a time tWR. Accordingly, a time tWR required for the memory device 10 to perform a write restore operation may be sufficiently guaranteed.

After a time tWR has elapsed from the point in time when the develop signal LANG and the pull-down pulse PLABDN change to the high level, the bit line sense amplifier enable signal BLSA_EN, the develop signal LANG, and the pull-down pulse PLABDN ) may change to a low level, and the develop signal LAPG may change to a high level. Accordingly, the internal voltage VINTA may not be supplied to the bit line sense amplifier 120 . In other words, the bitline sense amplifier 120 may be deactivated. In response to the precharge signal PRCG, the voltages VBL and VBLB of the bit line BL and the complementary bit line BLB may be charged with the precharge voltage by the voltage equalization circuit 130 .

6A illustrates the pull-up circuit of FIG. 4 in more detail, according to an embodiment of the present invention. 6B illustrates the pull-up circuit of FIG. 4 in more detail according to another embodiment of the present invention. 1 to 4 , 6A, and 6B , the pull-up circuit 112 may include delta voltage generators 112_1a/112_1b.

In the embodiment shown in FIG. 6A , the delta voltage generator 112_1a may include transistors MLAB2n and MLAB2p and amplifiers AMPn and AMPp. In the illustrated embodiment, the transistor MLAB2n may be implemented as an NMOS, and the transistor MLAB2p may be implemented as a PMOS. In the illustrated embodiment, the amplifiers AMPn and AMPp may be implemented as a Class AB amplifier or a Class B amplifier.

The transistor MLAB2n has a first terminal (eg, drain) connected to the second terminal of the pull-up transistor MLAB2a, a gate connected to the output terminal of the amplifier AMPn, and a second terminal (eg, connected to the ground voltage VSS). For example, the source) may be included. The transistor MLAB2p has a first terminal (eg, source) to which the voltage VDD1 is applied, a gate connected to the output terminal of the amplifier AMPp, and a second terminal (eg, connected to the second terminal) of the pull-up transistor MLAB2a. For example, drain) may be included.

The amplifier AMPn may include a first input terminal to which the reference voltage VREF_VLAB is applied, a second input terminal connected to the second terminal of the pull-up transistor MLAB2a, and an output terminal connected to the gate of the transistor MLAB2n. The amplifier AMPp may include a first input terminal to which the reference voltage VREF_VLAB is applied, a second input terminal connected to the second terminal of the pull-up transistor MLAB2a, and an output terminal connected to the gate of the transistor MLAB2p.

In the embodiment shown in FIG. 6A , the reference voltage VREF_VLAB is generated by the voltage generator 16 and may be supplied to the amplifiers AMPn and AMPp. The amplifiers AMPn and AMPp may amplify the reference voltage VREF_VLAB and output the amplified voltage. When the level of the voltage amplified by the amplifiers AMPn and AMPp is large enough to turn on the transistors MLAB2n and MLAB2p, the transistors MLAB2n and MLAB2p may be turned on. Accordingly, the magnitude of the delta voltage dVLABa applied to the second terminal of the pull-up transistor MLAB2a may vary. In other words, the magnitude of the delta voltage dVLABa may be adjusted based on the operation of the amplifiers AMPn and AMPp. The adjusted delta voltage dVLABa may be supplied to the node LAB of the bit line sense amplifier 120 through the pull-up transistor MLAB2a in response to the pull-up pulses PU_PULSE and PLABUP. In the embodiment shown in FIG. 6B , the delta voltage generator 112_1b may include a transistor MLAB2b. The transistor MLAB2b may be implemented as an NMOS. The transistor MLAB2b has a first terminal (eg, drain) connected to the second terminal of the pull-up transistor MLAB2a, a gate connected to the second terminal of the pull-up transistor MLAB2a, and a second terminal connected to the ground voltage VSS. It may include a stage (eg, a source). In this case, the transistor MLAB2b may be diode-connected.

6B , the pull-up transistors MPU1 and MLAB2a are turned on in response to the pull-up pulse PLABUP, and the pull-up transistor MPU1 and MLAB2a are turned on in response to the pull-up pulse PU_PULSE and the pull-up gate voltage PU_N When the MPU2 is turned on, a current based on the internal voltage VINTA may be transferred to the transistor MLAB2b through the pull-up transistors MPU1 , MPU2 , and MLAB2a . In this case, the delta voltage dVLABb applied to the gate and the first terminal of the transistor MLAB2b may be equal to the threshold voltage of the transistor MLAB2b. As a result, in response to the pull-up pulses PU_PULSE and PLABPU, a delta voltage dVLABb that is higher than the ground voltage VSS by the threshold voltage of the transistor MLAB2b is transmitted through the transistor MLAB2a to the bit line sense amplifier 120 . It may be supplied to the node LAB.

In the illustrated embodiment, the pull-up gate voltage PU_N may be equal to the level of the pull-up reference voltage VREF_PU. The pull-up reference voltage VREF_PU may be less than the internal voltage VINTA. Levels of the pull-up reference voltage VREF_PU and the internal voltage VINTA may be adjusted by the voltage generator 16 . For example, the voltage generator 16 adjusts the levels of the pull-up reference voltage VREF_PU and the internal voltage VINTA transmitted to the regulator 111 , thereby providing a pull-up gate supplied from the regulator 111 to the pull-up circuit 112 . The level of the voltage PU_N may be adjusted.

As the level of the pull-up gate voltage PU_N is adjusted, the level of the voltage VLAB pulled up by the pull-up circuit 112 may be adjusted. For example, as shown in FIG. 4 , the voltage generator 16 adjusts the level of the voltage output from the amplifier AMPR to the gate of the transistor MREF by adjusting the level of the pull-up reference voltage VREF_PU. have. Accordingly, it may be determined whether the transistor MREF is turned on. When the transistor MREF is turned on, a voltage determined based on the internal voltage VINTA and the pull-up reference voltage VREF_PU may be supplied to the pull-up circuit 112 through the transistor MREF. The voltage supplied from the regulator 111 to the pull-up circuit 112 may be applied to the gate of the pull-up transistor MPU2 through the inverters INV2 and INV1 . The configuration of the delta voltage generator 112_1 is not limited to the embodiments shown in FIGS. 6A and 6B . Accordingly, in consideration of the performance of the memory device 10 , the voltage VLAB may be pulled up to an appropriate level in a manner different from the illustrated embodiment.

7 exemplarily shows a block diagram of the pulse generator of FIG. 4 . 1 to 5 and 7 , the pulse generator 114 includes delay circuits D1 to D3, latches SR1 to SR3, flip-flop DFF1, and XOR gates XOR1 and XOR2. , and an adjustable delay circuit DA.

In the illustrated embodiment, the latches SR1 to SR3 may be implemented as SR latches. In the illustrated embodiment, the flip-flop DFF1 may be implemented as a D flip-flop. In an embodiment, the delay circuits D1 to D3 may include one or more buffers connected in series. In this case, the number of buffers included in each of the delay circuits D1 to D3 may be determined based on a length of time that each of the delay circuits D1 to D3 wants to delay. The embodiment shown in FIG. 7 is illustrative, and the configuration of the pulse generator 114 according to the embodiment of the present invention will not be limited thereto.

The delay circuit D1 may receive the word line active signal WLACT from the control logic 11 . After a time tCgShr has elapsed from the time point when the delay circuit D1 receives the word line active signal WLACT, the delay circuit D1 applies the received word line active signal WLACT to the latch SR1 and the delay circuit ( D3) as a signal BLSA_ST. In one embodiment, the time tCgShr is a memory cell (eg, the bit line BL) connected to the activated word line and the bit line BL as the word line (eg, WLO of FIG. 2 ) is activated. For example, it may be a time required to share charge between the capacitors (eg, CS1 of FIG. 2 ) included in MC1 of FIG. 2 ).

The delay circuit D2 may receive the precharge signal PRCG from the control logic 11 . After a time tWR has elapsed from the time when the delay circuit D2 receives the precharge signal PRCG, the delay circuit D2 transfers the received precharge signal PRCG to the latch SR1 as a signal BLSA_END. can be printed out. In an embodiment, the time tWR may be a write recovery time.

The delay circuit D3 may receive the signal BLSA_ST from the delay circuit D1 . After at least time tRCD has elapsed from the point in time when the delay circuit D1 receives the word line active signal WLACT, the delay circuit D3 applies the received signal BLSA_ST to the latch SR2, and the XOR gate XOR2. ) as a signal BLSA_STD. In an embodiment, the time tRCD may be a RAS-to-CAS delay.

The latch SR1 may receive the signal BLSA_ST from the delay circuit D1 . The latch SR1 may receive the signal BLSA_END from the delay circuit D2 . The latch SR1 may output the bit line sense amplifier enable signal BLSA_EN and the develop signal LAPG based on the received signals BLSA_ST and BLSA_END.

In the illustrated embodiment, the latch SR1 may use the signal BLSA_ST as a set signal, and may use the signal BLSA_END as a reset signal. The latch SR1 may latch the received signals BLSA_ST and BLSA_END to output the bit line sense amplifier enable signal BLSA_EN to the XOR gate XOR1 . The latch SR1 may output the develop signal LAPG by inverting the bit line sense amplifier enable signal BLSA_EN. The develop signal LAPG may be transmitted to the bit line sense amplifier 120 .

The latch SR2 may receive the signal BLSA_STD from the delay circuit D3 . The latch SR2 may receive the precharge signal PRCG from the control logic 11 . The latch SR2 may output the pull-up pulse PLABUP based on the received signals BLSA_STD and PRCG.

In the illustrated embodiment, the latch SR2 may use the signal BLSA_STD as a setting signal and the precharge signal PRCG as a reset signal. The pull-up pulse PLABUP may be output by latching the latch SR2 to the received signals BLSA_STD and PRCG. The pull-up pulse PLABUP may be transmitted to the XOR gate XOR1 and the pull-up circuit 112 .

The XOR gate XOR1 may receive the bit line sense amplifier enable signal BLSA_EN from the latch SR1 . The XOR gate XOR1 may receive the pull-up pulse PLABUP from the latch SR2 . The XOR gate XOR1 may output the develop signal LANG to the bit line sense amplifier 120 based on the received bit line sense amplifier enable signal BLSA_EN and the pull-up pulse PLABUP.

The flip-flop DFF1 may receive the bit line sense amplifier enable signal BLSA_EN from the latch SR1 . The flip-flop DFF1 may receive the write enable signal WREN from the control logic 11 . The flip-flop DFF1 may receive the signal SNORD from the adjustable delay circuit DA. In an embodiment, the flip-flop DFF1 may be a negative edge-triggered flip-flop. The flip-flop DFF1 may be output to the XOR gate XOR2 based on the signal WRENEDGE and the received signals BLSA_STD, WREN, and SNORD.

In the illustrated embodiment, the flip-flop DFF1 may use the signal BLSA_EN as a data input. The flip-flop DFF1 may use the write enable signal WREN as a clock input. The flip-flop DFF1 may use the signal SNORD as a reset signal. In response to the falling edge of the write enable signal WREN, the flip-flop DFF1 may output the signal WRENEDGE to the XOR gate XOR2 based on the signals BLSA_STD and SNORD.

The XOR gate XOR2 may receive the signal BLSA_STD from the delay circuit D3 . The XOR gate XOR2 may receive the signal WRENEDGE from the flip-flop DFF1. The XOR gate XOR2 may output the signal SNOR to the latch SR3 and the adjustable delay circuit DA based on the signals BLSA_STD and WRENEDGE.

The adjustable delay circuit DA may receive the signal SNOR. After an adjustable delay time from the time when the adjustable delay circuit DA receives the signal SNOR, the adjustable delay circuit DA may output the signal SNOR to the latch SR3 as a signal SNORD. . In this case, the level of the voltage VLAB may depend on the length of the adjustment delay time.

In an embodiment, the adjustment delay time delayed by the adjustable delay circuit DA may be determined based on characteristics of a die in which the memory cell array 12 is implemented. For example, the adjustment delay time may be determined in a manner similar to the manner in which the level of the above-described pull-up reference voltage VREF_PU is determined.

In the illustrated embodiment, the adjustable delay circuit DA may include a plurality of delay circuits D and a multiplexer MUX connected in series. The manner in which the adjustable delay circuit DA can be implemented is not limited to the embodiment illustrated in FIG. 7 .

Each of the delay circuits D of the adjustable delay circuit DA may output the received signal to the multiplexer MUX and the delay circuit D connected to each output terminal after a predetermined time elapses. For example, among the delay circuits D, the delay circuit D for receiving the signal SNOR transmits the received signal SNOR after a predetermined period of time, the delay circuit D connected to the multiplexer MUX and the output terminal can be output as For another example, the delay circuit D without the delay circuit D connected to the output terminal among the delay circuits D may output the received signal to the multiplexer MUX after a predetermined time elapses.

The multiplexer MUX may receive the selection signal SEL from the control logic 11 . Any one of the signals received from the delay circuits D may be selected based on the selection signal SEL. The multiplexer MUX may output the selected signal to the latch SR3 as a signal SNORD. In an embodiment, the control logic 11 may adjust the length of the adjustment delay time delayed by the adjustable delay circuit DA by using the selection signal SEL.

The latch SR3 may receive the signal SNOR from the XOR gate XOR2 . The latch SR3 may receive the signal SNORD from the adjustable delay circuit DA. The latch SR3 may output the pull-up pulse PU_PULSE based on the received signals SNOR and SNORD.

In the illustrated embodiment, the latch SR3 may use the signal SNOR as a setup signal, and may use the signal SNORD as a reset signal. The latch SR3 may output the pull-up pulse PU_PULSE to the pull-up circuit 112 by latching the signals SNOR and SNORD.

In an embodiment, the pulse generator 114 may further include a pull-down pulse generator circuit (not shown) that generates a pull-down pulse PLABDN. The pull-down pulse generating circuit may receive the precharge signal PRCG from the control logic 11 . The pull-down pulse generating circuit may generate the pull-down pulse PLABDN in response to the received pre-charge signal PRCG. In this case, the pull-down pulse PLABDN may be generated to have a level corresponding to logic '1' by the time tWR from the point in time when the pull-down pulse generating circuit receives the precharge signal PRCG. The pull-down pulse PLABDN may be transmitted to the pull-down circuit 113 .

8 is an exemplary flowchart of a method of operating a memory device according to an embodiment of the present invention. 1 to 4 and 8 , the memory device 10 may perform steps S100 to S300 .

In step S100 , the memory device 10 may activate a target word line. For example, the memory device 10 selects a word line corresponding to a command/address CA received from an external device, and supplies a voltage capable of turning on transistors connected to the selected word line to the selected word line. can

In step S200 , the memory device 10 restores data of the memory cell array 12 or writes data to the memory cell array 12 , and pulls up the voltage of the node LAB of the bit line sense amplifier 120 . can do. For example, the memory device 10 may detect data stored in memory cells connected to the target word line activated in step S100 . When data to be stored in the target memory cell among the memory cells connected to the target word line is not input to the memory device 10 , the memory device 10 may restore data to the memory cells connected to the target word line. Otherwise (eg, when new data is input to the memory device 10 ), the memory device 10 writes the new data input to the target memory cell, and the target memory cell among the memory cells connected to the target word line is Data can be restored to cells that are not. The memory device 10 may pull up the voltage VLAB of the node LAB in response to the word line active signal WLACT and the write enable signal WREN.

In operation S300 , the memory device 10 may pull down the voltage VLAB of the node LAB to the ground voltage VSS in response to the precharge signal PRCG. For example, the memory device 10 may pull down the voltage VLAB of the node LAB to the ground voltage VSS for a predetermined time in response to the precharge signal PRCG. Thereafter, the memory device 10 may charge the voltages of the bit line BL and the complementary bit line BLB to a precharge voltage (eg, 1/2 VINTA).

9 exemplarily shows a flowchart of a method of operating a system including a memory device according to an embodiment of the present invention. 1 to 4 and 7 to 9 , the external device of the memory device 10 may perform steps S1101, S1104, and S1106, and the memory device 10 may perform steps S1102, S1103, S1105, Steps S1107 and S1108 may be performed.

In step S1101 , the external device may transmit the first command/address CA1 to the memory device 10 . For example, the first command/address CA1 may include a row address ADDR_R corresponding to a target word line to be activated and an active command for activating the target word line.

In operation S1102 , the memory device 10 may generate the develop signals LANG and LAPG and activate the bit line sense amplifier 120 . For example, the memory device 10 may activate the target word line in response to the received first command/address CA1 . The memory device 10 generates a voltage VBL of a bit line BL and a voltage VBLB of a complementary bit line BLB based on the develop signals LANG and LAPG and the bit line sense amplifier enable signal BLSA_EN. ) can be developed.

In the illustrated embodiment, the memory device 10 may perform step S1102 after a time tCgShr has elapsed from the point in time when the first command/address CA1 is received. For example, the memory device 10 may generate the word line active signal WLACT based on the first command/address CA1 . Then, after the time tCgShr has elapsed, the memory device 10 may generate the develop signals LANG and LAPG and the bit line sense amplifier enable signal BLSA_EN.

In operation S1103 , the memory device 10 may generate a first pull-up pulse PU_PULSE1 and pull up the voltage level of the node LAB. In the illustrated embodiment, the memory device 10 may perform step S1103 after a time tRCD has elapsed from the point in time when the first command/address CA1 is received. For example, the memory device 10 may generate the first pull-up pulse PU_PULSE1 after a time tRCD has elapsed from a point in time when the word line active signal WLACT is generated. In response to the first pull-up pulse PU_PULSE1 , the bit line sense amplifier driving circuit 110 of the memory device 10 pulls up the voltage VLAB of the node LAB by the delta voltage dVLAB from the ground voltage VSS. can do. According to an embodiment, the first pull-up pulse PU_PULSE1 may correspond to the pull-up pulse PU_PULSE having a high level for a time tA in the third phase phase 3 of FIG. 7 .

In operation S1104 , the external device may transmit the second command/address CA2 to the memory device 10 . For example, the second command/address CA2 may include a write command and a column address ADDR_C indicating a target memory cell subject to a write operation.

In operation S1105 , the memory device 10 may generate a second pull-up pulse PU_PULSE2 and pull up the voltage level of the node LAB. For example, the memory device 10 may write data to the target memory cell in response to the second command/address CA2 . Next, the memory device 10 may generate a second pull-up pulse PU_PULSE2 . In response to the second pull-up pulse PU_PULSE2 , the bit line sense amplifier driving circuit 110 may pull up the voltage VLAB of the node LAB by the delta voltage dVLAB from the ground voltage VSS. According to an embodiment, the second pull-up pulse PU_PULSE2 may correspond to the pull-up pulse PU_PULSE having a high level for a time tB in the third phase phase 3 of FIG. 7 .

In operation S1106 , the external device may transmit the third command/address CA3 to the memory device 10 . For example, the third command/address CA3 may include a precharge command for requesting to perform a precharge operation on the bit line BL and the complementary bit line BLB.

In operation S1107 , the memory device 10 may generate a pull-down pulse PLABDN and pull down the voltage level of the node LAB to the ground voltage GND. For example, the memory device 10 may generate the precharge signal PRCG in response to the received third command/address CA3 . The memory device 10 may generate a pull-down pulse PLABDN based on the precharge signal PRCG. In response to the pull-down pulse PLABDN, the bit line sense amplifier driving circuit 110 may pull down the voltage VLAB of the node LAB to the ground voltage GND.

In operation S1108 , the memory device 10 may charge the bit line BL and the complementary bit line BLB with a precharge voltage. In the illustrated embodiment, the memory device 10 may perform step S1108 after a time tWR has elapsed from the point in time when the precharge signal PRCG is generated.

The above are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present invention will include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the claims described below as well as the claims and equivalents of the present invention.

10: memory device
100: sense amplifier unit
110: bit line sense amplifier driving circuit
120: bit line sense amplifier

Claims (10)

a bit line sense amplifier connected to a bit line connected to a memory cell and a complementary bit line, and configured to sense and amplify a voltage difference between a voltage of the bit line and a voltage of the complementary bit line; and
a sense amplifier driving circuit for adjusting a level of a bit line low level voltage of the bit line sense amplifier to be higher than a level of a ground voltage in response to a command received from a host;
The command includes an active command, a write command, a read command, or a precharge command. The method of claim 1,
The memory cell includes a transistor having a floating body structure. The method of claim 1,
The sense amplifier driving circuit includes a pull-up circuit and a pulse generator generating a first pull-up pulse and a second pull-up pulse, the pull-up circuit comprising:
a delta voltage generator for generating a delta voltage;
a first pull-up transistor including a first end to which a first internal voltage is applied, a gate to which the second pull-up pulse from the pulse generator is applied, and a second end;
a second pull-up transistor including a first end connected to the second end of the first pull-up transistor, a gate to which a pull-up gate voltage is applied, and a second end to which the bit line low level voltage is applied;
A first end connected to the second end of the second pull-up transistor to which the bit line low level voltage is applied, a gate to which the pull-up gate voltage is applied, and a first terminal connected to the delta voltage generator for applying a delta voltage. a third pull-up transistor comprising two stages; and
and a first inverter configured to apply the pull-up gate voltage to the gate of the second pull-up transistor based on the first pull-up pulse. 4. The method of claim 3,
wherein the delta voltage generator includes a first end coupled to the second end of the third pull-up transistor, a gate coupled to the second end of the third pull-up transistor, and a second end coupled to the ground voltage. A memory device comprising a transistor. The method of claim 1,
The sense amplifier driving circuit includes a pulse generator for generating a first pull-up pulse and a second pull-up pulse, the pulse generator comprising:
A sense amplifier enable signal and the sense amplifier based on an active signal for activating a word line to which the memory cell is connected and a precharge signal for precharging the bit line among signals generated based on a command received from the host a first latch for outputting a first develop signal in which an enable signal is inverted to the bit line sense amplifier;
a second latch for outputting the second pull-up pulse based on the active signal and the precharge signal;
a first XOR gate receiving the sense amplifier enable signal and the second pull-up pulse, and outputting a second develop signal to the bit line sense amplifier;
a second XOR gate configured to output an intermediate signal based on a falling edge of a write enable signal and an active signal among signals generated based on a command received from the host; and
and a third latch outputting the first pull-up pulse based on the intermediate signal. a bit line sense amplifier coupled to a bit line coupled to the memory cell and a complementary bit line, and configured to sense and amplify data stored in the memory cell; and
A sense amplifier driving circuit comprising:
generate a first pull-up pulse and a pull-down pulse based on a command received from the host; and
adjusting a level of a bit line low voltage developed by the bit line sense amplifier in response to the first pull-up pulse and the pull-down pulse;
A level of the bit line low voltage becomes higher than a ground voltage by a delta voltage when a read operation is performed on the memory cell, and becomes equal to a ground voltage when a write operation is performed on the memory cell. 7. The method of claim 6,
The memory cell includes a transistor having a floating body structure. 7. The method of claim 6,
The first pull-up pulse is:
has a high level for a first adjustment time after a first delay time after an active signal is generated based on the command received from the host; and
A memory device having a high level for a second adjustment time after a second delay time after a write signal is received based on the command received from the host. A method of operating a memory device comprising a bit line sense amplifier coupled to a bit line and a complementary bit line, the method comprising:
detecting data stored in a target memory cell from among a plurality of memory cells connected to the bit line and the upper bit line;
if the first data to be stored in the target memory cell is not input to the memory device, restoring the data stored in the target memory cell and increasing a voltage level of a first node of the bit line sense amplifier from a ground voltage; ; and
When the first data to be stored in the target memory cell is input to the memory device, the first data is written to the target memory cell and the voltage level of the first node of the bitline sense amplifier is increased from a ground voltage. making; and
reducing the voltage level of the first node of the bitline sense amplifier to a ground voltage;
Each of the plurality of memory cells includes a transistor having a floating body structure, and
The voltage level of the bit line and the voltage level of the complementary bit line are associated with a voltage level of the first node. 10. The method of claim 9,
writing the first data to the target memory cell and increasing the voltage level of the first node of the bitline sense amplifier from a ground voltage comprises:
receiving a command/address from an external device;
increasing the voltage level of the first node of the bit line sense amplifier based on the command/address to be higher than a ground voltage by a delta voltage; and
and writing the first data to the target memory cell.

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