KR100868031B1 - Non-volatile memory device and the method for manufacturing the same - Google Patents

Abstract

The non-volatile memory device of the low voltage, micro type, highly integrated, high reliability the manufacturing process and a method of manufacture thereof are provided without complicated and additional processes. The non-volatile memory device comprises as follows. The memory layer is formed in which the turner insulating layer(510), first charge trapping layer(520), electric charge isolation layer(530), second charge trapping layer(540), blocking insulation film(550) are successively formed on a semiconductor substrate. The gate electrode layer(560) is formed on the blocking insulation film. The first-level is shown in the state that the electric charge is not injected in the first charge trapping layer and the second charge injecting layer. The second level is shown in case the electric charge is injected in the first charge trapping layer. The third level is shown in case the electric charge is injected in the second charge trapping layer. The fourth level is shown in case the electric charge is altogether injected in the first charge trapping layer and the second charge trapping layer. The electric charge is injected through the blocking insulation film from the gate electrode layer to the second charge trapping layer in order to show the third level.

Description

Non-volatile memory device and method for manufacturing the same

The present invention relates to a semiconductor device, and more particularly, to a nonvolatile memory device and a method of manufacturing the same.

In general, semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), are fast memory inputs and outputs, but lose their stored data when power is lost. In contrast, a nonvolatile memory device is a memory device that retains stored data even when power is cut off.

Flash memory devices are a type of nonvolatile memory device that can be programmed and erased, and can be programmed and erased. It is a highly integrated device developed by combining the advantages of Read Only Memory. Flash memory devices are classified into floating gate type flash memory devices and floating trap type flash memory devices according to types of data storage layers constituting a unit cell.

Unlike a floating gate type flash memory device storing charge in a polysilicon layer, a charge trapping flash memory device stores charge in a trap formed in a non-conductive charge trapping layer. The memory cell of the charge trapping memory device has a stacked structure of a gate insulating film formed on a silicon substrate, a silicon nitride film as a charge trapping layer, a blocking insulating film and a conductive film.

1 is a cross-sectional view of a nonvolatile memory device 10 having a silicon oxide nitride (SONOS) structure according to the prior art. Referring to FIG. 1, a memory cell of the memory device 10 includes an oxide film 12, a nitride film 13, and an oxide film on a channel region 18 between regions of source / drain 17 formed in a substrate 11. The ONO film 15 made of 14) and the polysilicon 16 are stacked in this order. This memory cell has a single bit structure showing either a logic '0' or a logic '1' state depending on the presence or absence of charge trapped in the nitride film 13 of the ONO film 15. Accordingly, there is a need for a memory device having an increased information storage capability because the memory device can represent two or more states without increasing the size of the memory device.

Recently, with the development of nanotechnology, nonvolatile memory devices using nanocrystals have been studied.

2 and 3 are cross-sectional views of nonvolatile memory devices 20 and 30 using nanocrystals according to the related art.

First, referring to FIG. 2, a channel region 28 is disposed between the source / drain regions 27 formed in the substrate 21. The memory cell includes a memory layer 25 and a gate electrode 26 formed on the channel region 28. The memory layer 25 includes a tunnel insulating film 22, a charge trapping layer 23, and a blocking insulating film 24 that are sequentially stacked. The charge trapping layer 23 includes so-called nanocrystals 23NC in the form of clusters or dots of several to several tens of nm in size. Since the charge injected into the nanocrystal 23NC is not easily moved between the nanocrystals, the memory device using the nanocrystal is suppressed in the lateral diffusion of the charge as compared to the memory device of the conventional Sonos structure, It is advantageous to implement a multi-bit memory device.

However, when a conventional non-crystal memory device using nanocrystals is to be implemented as a multi-bit (for example, 1 cell-2 bit) nonvolatile memory device, there is a limit to scaling down the size. In other words, in order to use a memory device using a nanocrystal as a memory device having a multi-bit structure, charge must be locally injected into a charge trapping layer near the source / drain region 27. However, in the case of a short channel memory device, not only an overlap phenomenon may occur during charge injection, but also a lateral diffusion of the injected charge may occur and a disturb phenomenon may occur. As a result, the operation of 1 cell-2 bits may not be performed. In order to solve this problem, the channel length of the memory device must be maintained at a certain level, which is contrary to the high integration of the memory device. To solve this problem, a structure for separating the memory layer into two has been proposed.

Referring to FIG. 3, two memory layers 35L and 35R are disposed on the channel region 38 between the source / drain regions 37 formed on the substrate 31 and separated from the left and right through the insulating layer 35C. do. The two memory layers 35L and 35R each include a tunnel insulating film 32L and 32R, a charge trapping layer 33L and 33R, and a blocking insulating film 34L and 34R which are sequentially stacked. The gate electrode 36 is positioned on the two memory layers 35L and 35R and the insulating layer 35C. This structure can scale down the memory device to some extent. However, according to the number of nanocrystals 33NC included in the charge trap layers 33L and 33R while being scaled down, the difference in threshold voltage shift is large, resulting in a problem that the reliability of the device is degraded.

The technical problem to be solved by the present invention is to provide a low voltage, ultra small, ultra-high integration, high performance, high reliability non-volatile memory device and a manufacturing method thereof without adding a complicated manufacturing process.

A nonvolatile memory device for achieving the above-mentioned problem includes a memory layer in which a tunnel insulation film, a first charge capture layer, a charge isolation layer, a second charge capture layer, and a blocking insulation film are sequentially formed on a semiconductor substrate; And a gate electrode layer formed on the blocking insulating film.

In addition, the above-mentioned second charge trapping layer may be formed to a thickness greater than or equal to the first charge trapping layer.

In addition, the above-mentioned first charge trap layer may be formed to a thickness of 3 to 150 nm.

In addition, the second charge trap layer may be formed to a thickness of 4 to 160 nm.

In addition, the first and second charge trap layers described above may be formed of any one of a nitride film, a material having a high dielectric constant, and an amorphous polysilicon material.

In addition, the above-mentioned first and second charge trapping layers may be formed of one metal selected from the group consisting of tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium and iridium, or a mixture thereof or an alloy thereof. have.

In addition, the above-mentioned first and second charge trapping layers may be formed of one semiconductor material selected from the group consisting of silicon, germanium, a mixture of silicon and germanium, a group III-V compound or a group II-VI compound. have.

In addition, the nonvolatile memory device of the present invention described above exhibits a first level in a state where no charge is injected into the first charge trapping layer and the second charge injection layer, and when charge is injected only into the first charge trapping layer. The second level, the third level when charge is injected only to the second charge trapping layer, and the fourth level when charge is injected to both the first charge trapping layer and the second charge trapping layer, Programmable in multi bit.

In addition, in order to show the third level in the nonvolatile memory device of the present invention, charge may be injected from the gate electrode layer to the second charge trapping layer through the blocking insulating film.

Further, in order to show the fourth level in the nonvolatile memory device of the present invention, charge may be injected from the semiconductor substrate to the first charge trapping layer and the second charge trapping layer through the tunnel insulating film.

Meanwhile, in the method of manufacturing the nonvolatile memory device of the present invention for achieving the above technical problem, (a) a tunnel insulating film, a first charge trapping layer, a charge isolation layer, a second charge trapping layer, and a blocking insulating film are sequentially formed on a semiconductor substrate. Forming a memory layer; (b) forming a gate electrode layer on the blocking insulating film; (c) forming a hard mask layer pattern on the gate electrode layer and etching the gate electrode layer and the memory layer until the semiconductor substrate is exposed using the hard mask layer as an etching mask; And (d) forming a source region and a drain region in the semiconductor substrate.

In addition, in the above-described step (a), the second charge trapping layer may be formed to a thickness greater than or equal to the first charge trapping layer.

In addition, in the above-described step (a), the first charge trap layer may be formed to a thickness of 3 to 150 nm.

In addition, in the above-described step (a), the second charge trapping layer may be formed to a thickness of 4 to 160 nm.

In addition, in step (a) described above, the first and second charge trap layers may be formed of any one of a nitride film, a material having a high dielectric constant, and an amorphous polysilicon material.

Further, in the above-mentioned step (a), the first and second charge trapping layers are one metal selected from the group consisting of tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium and iridium or mixtures thereof or It may be formed of an alloy of.

Further, in the above-mentioned step (a), the first and second charge trapping layers are one semiconductor selected from the group consisting of silicon, germanium, a mixture of silicon and germanium, a group III-V compound or a group II-VI compound. It can be formed of a material.

The nonvolatile memory device of the present invention includes a plurality of charge trapping layers separated by a charge isolation layer, so that in implementing a multilevel operation, a distribution of threshold voltages of each level can be easily separated, thereby achieving multilevel operation. There is an effect that can be implemented.

In addition, the present invention enables multi-level operation by additionally forming a charge isolation layer and a charge trapping layer in the structure of the conventional nonvolatile memory device, so that the manufacturing process implements the conventional multilevel nonvolatile memory device. Simpler than the manufacturing process has the effect of improving the manufacturing efficiency.

In addition, there is an effect that can be easily programmed to operate in a multi-level.

Hereinafter, a structure, a manufacturing method, and an operation of a nonvolatile memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 4 to 6C.

4 is a diagram illustrating a structure of a nonvolatile memory device according to a preferred embodiment of the present invention. Referring to FIG. 4, in the nonvolatile memory device of the present invention, a source region 504 and a drain region 508 are formed on a semiconductor substrate 500, and a channel region is positioned between the source and drain regions 508. .

The memory layer in which the tunnel insulating layer 510, the first charge trapping layer 520, the charge isolation layer 530, the second charge trapping layer 540, and the blocking insulating layer 550 are sequentially formed is formed on the channel region. The gate electrode layer 560 is formed on the blocking insulating layer 550, and the insulating layer spacer 590 is formed around the memory device.

In this case, the second charge trapping layer 540 may be formed to any thickness, but preferably, the second charge trapping layer 520 is formed to have a thickness greater than or equal to the first charge trapping layer 520.

Hereinafter, a method of manufacturing a nonvolatile memory device according to a preferred embodiment of the present invention will be described with reference to FIGS. 5A to 5F.

First, referring to FIG. 5A, a tunnel insulating layer 510 is formed on a semiconductor substrate 500 to manufacture a nonvolatile memory device of the present invention.

The tunnel insulating film 510 may be formed of a silicon oxide film (SiO 2) as an oxide film formed on the channel region with a thickness of several nm through a thermal oxidation process or a known thin film deposition process. As the thickness of the tunnel insulating layer 510 is thinner, a lower program voltage may be applied to the gate electrode layer 560, which enables fast programming and erasing, as well as a high probability of success of the program and erasing operation. There is a low problem. Therefore, the thickness of the tunnel insulating layer 510 is preferably selected as thin as possible at an appropriate level according to variables such as program and erase voltage and speed.

Meanwhile, after the tunnel insulating film 510 is formed, as illustrated in FIG. 5B, the first charge trap layer 520 is formed on the tunnel insulating film 510 to have a thickness of 3 to 150 nm. The first charge trap layer 520 may be formed of any material capable of storing charge as well as a nitride film.

For example, the first inversion trap layer may be formed of any one of a material having a high-k and an amorphous polysilicon material. In addition, the first charge trap layer 520 may be formed of a metal such as tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium, and iridium, a mixture thereof, or an alloy thereof. Further, the first charge trapping layer 520 may be formed of silicon, germanium, a mixture of silicon and germanium, a group III-V compound (combination of Al, Ga, In of group III and P, As, Sb of group V), or II-. It may be formed of a semiconductor material such as a Group VI compound (combination of Zn, Cd, Hg of Group II and O, S, Se, Te of Group VI). In addition, the first charge trapping layer 520 is also formed of an insulator having a high trapping density against charges such as aluminum oxide (Al 2 O 3), hafnium oxide (HfO), hafnium aluminum oxide (HfAlO), and hafnium silicon oxide (HfSio). Can be.

After the first charge trapping layer 520 is formed, as shown in FIG. 5C, a charge isolation layer 530 is formed thereon, and a second charge trapping layer 540 is formed over the charge isolation layer 530. . As described above, the second charge trapping layer 540 is preferably formed to have a thickness greater than or equal to the first charge trapping layer 520.

The charge isolation layer 530 may be formed to have a thickness of 3 to 150 nm using the same materials as those that may be used to form the tunnel insulating film 510 and the blocking insulating film 550 described later using a known deposition method. Can be. In general, multilevel operation using a polysilicon film is known to be very difficult to separate the distribution of the threshold voltage into four, but the present invention provides a charge isolation layer between the first charge trapping layer 520 and the second charge trapping layer 540. By forming 530, it is easy to distinguish threshold voltages, and thus it is possible to perform a 2-bit program operation as one cell.

On the other hand, the second charge trapping layer 540 has a thickness of 4 to 160 nm using materials that can be used to form the first charge trapping layer 520 in the same manner as the first charge trapping layer 520 described above. Can be formed.

As described above, the second charge trapping layer 540 is preferably formed to have a thickness greater than or equal to the thickness where the first charge trapping layer 520 is formed such that the charge storage space is greater than or equal to the first charge trapping layer 520.

After the second charge trapping layer 540 is formed, as shown in FIG. 5D, a blocking insulating layer 550 is formed on the second charge trapping layer 540, and a gate electrode layer 560 is formed on the blocking insulating layer 550. Is formed.

The blocking insulating film 550 is preferably formed to be at least thicker than the tunnel insulating film 510 in order to prevent the charge stored in the charge trapping layers from leaking to the gate electrode layer 560. In the preferred embodiment of the present invention, the blocking insulating film 550 550) is preferably formed to a thickness of 3 to 150 nm, and is formed to a thickness of 6 to 70 nm in consideration of scaling down while faithfully serving as a blocking oxide film. In addition, the blocking leading edge film may be formed using materials that may be used to form the tunnel insulating film 510 described above.

The gate electrode layer 560 may be formed of any conductive material typically used as a gate electrode, such as polysilicon, a metal, or a polyside structure in which metal-silicide is formed on polysilicon. In consideration of the increase in resistance when the line width of the gate electrode is narrowed according to the high integration of the device, the gate electrode layer 560 is preferably formed of a metal or polyside structure having better conductivity than polysilicon.

After the gate electrode layer 560 is formed, as shown in FIG. 5E, the hard mask film patterns 580 are formed in the region where the memory device is to be formed, and the hard mask film 580 is used as an etching mask. The gate electrode layer 560, the blocking insulating layer 550, the second charge trapping layer 540, the charge isolation layer 530, the first charge trapping layer 520, and the tunnel insulating layer 510 are exposed until 500 is exposed. Etch it. In the present invention, the separation distance between the source region 504 and the drain region 508 is several tens to hundreds of nm, and thus the memory device formed over the channel region located between the source region 504 and the drain region 508. The length also becomes tens to hundreds of nm. Therefore, the length of the hard mask film patterns is also determined according to the length of the memory element.

Thereafter, a source drain ion implantation process is performed to form a source region 504 and a drain region 508 on the semiconductor substrate 500, and an insulating film spacer 590 is formed to form the present invention as shown in FIG. 5F. This completes the nonvolatile memory device.

So far, the structure of the nonvolatile memory device and the method of manufacturing the same have been described. The multi-bit program and erase operations of the nonvolatile memory device of the present invention will be further described with reference to FIGS. 6A to 6D as follows.

First, a nonvolatile memory device according to a preferred embodiment of the present invention can program a 2-bit multi-bit level. For example, the first level may be programmed to correspond to 00, the second level to 01, the third level to 10, and the fourth level to 11, respectively.

First, in a preferred embodiment, the first level represents a state where no charge is trapped in the first charge trapping layer 520 and the second charge trapping layer 540 in the structure shown in FIG. 4.

On the other hand, when the substrate 500 is grounded to program the second level, and a first voltage having a positive voltage is applied to the gate electrode layer 560, charge is tunneled from the substrate 500 as shown in FIG. 6A. The insulating layer 510 is tunneled into the first charge trap layer 520 by tunneling the Fowler-Nordheim (FN), so that charge is trapped only in the first charge trap layer 520 and no charge is injected into the second charge trap layer 540. It is not in a state.

In this case, the first voltage is sufficient to inject the charge into the first charge trapping layer 520, and the charge injected into the first charge trapping layer 520 tunnels the charge isolation layer 530 again to form a second charge. A voltage insufficient to be injected into the capture layer 540 is applied. In a preferred embodiment of the present invention, a voltage of about + 5V is used as the first voltage. However, the magnitude of this voltage may be adaptively determined in consideration of the thicknesses of the tunnel insulating film 510 and the charge isolation layer 530.

On the other hand, when the substrate 500 is grounded to program the third level, and a second voltage having a negative voltage is applied to the gate electrode layer 560, as shown in FIG. 6B, the blocking insulating layer from the gate electrode layer 560 is shown. Charge tunneling 550 is injected into the second charge trapping layer 540 and filled, and charges existing in the first charge trapping layer 520 tunnel through the tunnel insulating film 510 to form the substrate 500. The channel is erased. Thus, only the second charge trapping layer 540 is filled with charge, and the first charge trapping layer 520 is not charged.

In this case, the second voltage is sufficient to inject the charge into the second charge trapping layer 540, and the charge injected into the second charge trapping layer 540 tunnels the charge isolation layer 530 again to form the first charge. A voltage insufficient to be injected into the capture layer 520 is applied. In a preferred embodiment of the present invention, a voltage of about -10V is used as the second voltage. However, the magnitude of this voltage may be adaptively determined in consideration of the thicknesses of the blocking insulating film 550 and the charge isolation layer 530.

Finally, in order to program the fourth level, a third voltage, which is a positive voltage, is applied to the gate electrode layer 560 while the substrate 500 is grounded. When the third voltage is applied, as shown in FIG. 6C, in the state where no charge is first injected into the first charge trapping layer 520, the substrate 500 may be formed by hot carrier injection, channel injection, or FN tunneling. Charge is injected into the first charge trapping layer 520. Thereafter, charges injected into the first charge trapping layer 520 are injected into the second charge trapping layer 540 again through the charge isolation layer 530. Therefore, at the fourth level, both the first charge trapping layer 520 and the second charge trapping layer 540 are filled with charge.

At this time, a positive voltage of a level substantially higher than the first voltage must be applied to the third voltage so that charges in the channel region can be injected to the second charge trapping layer 540. Therefore, in a preferred embodiment of the present invention, a voltage of about + 15V is used as the first voltage, and the magnitude of the third voltage may be adaptively determined in consideration of the thicknesses of the tunnel insulating film 510 and the charge isolation layer 530. Can be.

Meanwhile, a process of erasing data with respect to a memory device programmed by the above-described method will be described. First, when programmed to a second level, a negative voltage of −20 V is applied to the gate electrode layer 560 to erase data. When a negative voltage is applied, charges existing in the first charge trapping layer 520 are again tunneled through the tunnel insulation layer 510 using the FN tunneling method and injected into the channel region of the substrate 500. 520 returns to the state before it was programmed.

In addition, when programmed to the third level, a positive voltage is applied to the gate electrode for data erasing, and when the positive voltage is applied, charges existing in the second charge trapping layer 540 are transferred through the blocking insulating layer 550. Injected into the gate electrode layer 560, the second charge trapping layer 540 is in a state prior to being programmed.

In addition, when programmed to the fourth level, a negative voltage is applied to the gate electrode for data erasing, and when the negative voltage is applied, the negative charge is applied to the second charge trapping layer 540 and the first charge trapping layer 520. Charges are injected into the semiconductor substrate 500 through the tunnel insulating layer 510 so that the first charge trapping layer 520 and the second charge trapping layer 540 are in a state before being programmed.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

1 is a cross-sectional view of a nonvolatile memory device 10 having a silicon oxide nitride (SONOS) structure according to the prior art.

2 and 3 are cross-sectional views of nonvolatile memory devices 20 and 30 using nanocrystals according to the related art.

4 is a diagram illustrating a structure of a nonvolatile memory device according to a preferred embodiment of the present invention.

5A to 5F illustrate a method of manufacturing a nonvolatile memory device in accordance with a preferred embodiment of the present invention.

6A to 6D are diagrams for explaining a multi-bit program and erase operation of the nonvolatile memory device of the present invention.

Claims (17)

A memory layer in which a tunnel insulating film, a first charge trapping layer, a charge isolation layer, a second charge trapping layer, and a blocking insulating film are sequentially formed on the semiconductor substrate; And A gate electrode layer formed on the blocking insulating film, In a state where no charge is injected into the first charge trapping layer and the second charge injection layer, the first level is represented. When charge is injected only into the first charge trapping layer, the second level is displayed. When charge is injected only into the second charge trapping layer, the third level is represented. When charge is injected into both the first charge trapping layer and the second charge trapping layer, the fourth level is indicated, thereby enabling multi-bit programming. To indicate the third level And a charge is injected from the gate electrode layer to the second charge trapping layer through the blocking insulating layer. The method of claim 1, And the second charge trap layer is formed to a thickness greater than or equal to the first charge trap layer. The nonvolatile memory device of claim 1, wherein the first charge trap layer is formed to a thickness of 3 to 150 nm. The nonvolatile memory device of claim 1, wherein the second charge trap layer is formed to a thickness of 4 to 160 nm. The method of claim 1, wherein the first and second charge trapping layer is A nonvolatile memory device, comprising: a nitride film, a material having a high dielectric constant, and an amorphous polysilicon material. The method of claim 1, wherein the first and second charge trapping layer is A nonvolatile memory device, characterized in that it is formed of one metal selected from the group consisting of tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium and iridium, or a mixture thereof or an alloy thereof. The method of claim 1, wherein the first and second charge trapping layer is A nonvolatile memory device comprising: a semiconductor material selected from the group consisting of silicon, germanium, a mixture of silicon and germanium, a group III-V compound, or a group II-VI compound. delete delete The method of claim 1, wherein the fourth level is used to represent the fourth level. And a charge is injected into the first charge trapping layer and the second charge trapping layer from the semiconductor substrate through the tunnel insulating layer. A method of programming the memory element of any one of claims 1 to 7, and 10, Applying a first positive voltage to the gate electrode layer to inject charge from the substrate into the first charge trapping layer to store a 01 state; Applying a second negative voltage to the gate electrode layer to inject charge from the gate electrode layer into the second charge trapping layer to store ten states; And Applying a second voltage greater than the first voltage to the gate electrode layer to inject charge from the substrate into the first charge trapping layer and the second charge trapping layer to store the 11 state; A memory device program method. delete delete delete delete delete delete

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