CN103165612B - A kind of flash memories and preparation method thereof - Google Patents
A kind of flash memories and preparation method thereof Download PDFInfo
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- CN103165612B CN103165612B CN201110410003.9A CN201110410003A CN103165612B CN 103165612 B CN103165612 B CN 103165612B CN 201110410003 A CN201110410003 A CN 201110410003A CN 103165612 B CN103165612 B CN 103165612B
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Abstract
The invention provides a kind of flash memories, the charge storage layer of memory is isolated dielectric area and is divided into two electric charge storage regions, and the conductivity in described spacer medium district is less than the conductivity of described two electric charge storage regions, and the material of two electric charge storage regions is different.Correspondingly, the present invention also provides a kind of manufacture method of flash memories.The charge storage layer of flash memories of the present invention adopts the less spacer medium district of conductivity to be kept apart two electric charge storage regions, can suppress the stored charge crosstalk between two electric charge storage regions, ensure that the memory reliability of memory.In two other electric charge storage region, one adopts metal nitride nanocrystalline material, and another adopts the amorphous/nano crystal semi-conducting material that dielectric constant is higher, and when can avoid programming, source injects phenomenon to the impact of memory memory reliability.
Description
Technical field
The present invention relates to memory technology field, particularly relate to a kind of can the flash memories and preparation method thereof of multilevel storage.
Background technology
Along with the increase of the wireless communication data traffic and the raising of multimedia equipment integrated level, the requirement for embedded storage improves day by day, while requiring data high-speed to access, also requires to improve storage density.These all propose new requirement to the flash memory technology of NOR type array architecture.The flash memory technology of NOR type array architecture is mainly used in the middle of embedded storage, and wherein nano-crystal memory compiles wiping speed fast due to it, in the embedded memory technology of NOR type, occupy critical role.Simultaneously because the memory capacity of present communication need increases day by day, the storage density of this reservoir of will seeking survival will improve further, is suggested based on NROM storage organization flash memories.This device architecture make use of the localization storage characteristics of electric charge in trapped-charge memory, realizes the mirrored storage of electric charge in capture layer, realizes the storage of the multiple data of same unit, improves the storage density of memory cell.
The structural representation of NROM structure flash memory memory is see Fig. 1, comprise Semiconductor substrate 100, substrate comprises successively electric charge tunnel layer 101, charge storage layer 102, electric charge barrier layer 103 and grid layer 104, and be positioned at source area 105 and the drain region 106 of substrate.Channel hot electron is adopted to inject (CHEI, ChannelHot-Electron Injection) or channel hot idle injection (CHHI, Channel Hot-HoleInjection) mode iunjected charge time, add higher program voltage V at grid layer
g, drain electrode and source electrode making alive V respectively
dand V
shave electric charge to flow through between source electrode and drain electrode, meanwhile, Partial charge is crossed electric charge tunnel layer and is captured by the defect in charge storage layer under electric field action, these defects are equivalent to some discrete energy potential wells in being with, and these energy potential wells of defect hold onto the electric charge be embedded.Because the defect in charge storage layer is spatially localization distribution, be strapped in the feature that electronics in these defect potential wells and hole also have spatial localization, therefore, by controlling the position of electronics and hole injection, make to be injected into the electronics of charge storage layer or hole is intensive is stored in region Bit 1 and region Bit 2, the multidigit realizing NROM structure flash memory memory stores.Read and reverse read two kinds of channel current reading manners by forward, the data message preserved in region Bit 1 and region Bit 2 can be extracted respectively.
But, in order to adapt to the ever-reduced requirement of memory-size, the charge storage layer of NROM structure flash memory memory can constantly reduce, the charge density stored in region Bit 1 and region Bit 2 will increase, energy potential well is not enough to hold onto the electric charge be stored in region Bit 1 and region Bit 2, the electric charge stored spreads at charge storage layer, to be uniformly distributed in whole charge storage layer through electric charge after a period of time, the charge information undistinguishable preserved in region Bit 1 and region Bit 2, make the mutual crosstalk of information stored between different charge storage region, namely two bit strings disturb (Second-bit effect) phenomenon, this can reduce the memory reliability of flash memories.
In addition, due to the requirement of multilevel storage, the quantity of electric charge stored in electric charge storage region is needed to increase, this just requires to adopt higher voltage and longer burst length, increase the quantity of electric charge that memory block is injected, this can cause source to inject (SSI, Soured-side injection) phenomenon, make the program erase of Bit 1 can affect the information stored in Bit 2, cause the integrity problem of device.
Summary of the invention
The invention provides a kind of flash memories, solve in existing flash memories to disturb due to two bit strings and inject with source the memory reliability problem that phenomenon reduces flash memories.
For solving above-mentioned purpose, the invention provides a kind of flash memories, comprise Semiconductor substrate, the grid stacked media layer be positioned on substrate, be positioned at grid layer on grid stacked media layer and the source area be positioned on the substrate of grid stacked media layer both sides and drain region, described grid stacked media layer comprises:
Be positioned at the electric charge tunnel layer in Semiconductor substrate;
Be positioned at the charge storage layer on described electric charge tunnel layer, described charge storage layer is isolated dielectric area and is divided into two electric charge storage regions, and wherein, source area and drain region lay respectively at the both sides in spacer medium district; The conductivity in described spacer medium district is less than the conductivity of described two electric charge storage regions; Described two electric charge storage regions adopt different materials.
Be positioned at the electric charge barrier layer on described charge storage layer.
Preferably, described spacer medium district is elongated shape, and its length direction is along the direction being basically perpendicular to source electrode and drain electrode line.
Preferably, described spacer medium district adopts silicon-base oxide or silica-based nitrogen oxide.
Preferably, in described two electric charge storage regions, first electric charge storage region adopts metal nitride nanocrystalline material, and the second electric charge storage region adopts amorphous/nano crystal semi-conducting material, and described second electric charge storage region adopts the dielectric constant of dielectric constant higher than described electric charge tunnel layer material of material.
Preferably, described first electric charge storage region adopts that titanium nitride nano is brilliant or tantalum nitride is nanocrystalline.
Preferably, described second electric charge storage region adopts the binary oxide of the elements such as hafnium, zirconium, tantalum or ytterbium.
Wherein, described electric charge tunnel layer adopts silicon-base oxide or silica-based nitrogen oxide.
Wherein, described electric charge barrier layer adopts silicon-base oxide or silica-based nitrogen oxide.
Correspondingly, the present invention also provides a kind of flash memories manufacture method, comprises step:
Semiconductor substrate is provided;
Make electric charge tunnel layer over the substrate;
Described electric charge tunnel layer makes and is isolated separated first electric charge storage region, district and the second electric charge storage region, wherein, described first electric charge storage region and the second electric charge storage region adopt different materials;
At described isolated area deposition spacer medium material, the isolated area of filling between two electric charge storage regions forms spacer medium district, and the conductivity in described spacer medium district is less than described two electric charge storage regions;
Described first electric charge storage region, the second electric charge storage region and described spacer medium district make electric charge barrier layer;
Each layer of above-mentioned making is annealed, the material of the first electric charge storage region is formed nanocrystalline;
Described electric charge barrier layer makes grid layer;
Described grid layer forms figure by exposure, and deposition mask layer forms mask pattern, etching is not formed gate patterns by the grid layer that mask pattern blocks;
Etch each layer of the above-mentioned making do not covered by mask layer to exposing substrate, make source area and drain region in described exposing on substrate, described source area and drain region lay respectively at the both sides in described spacer medium district.
Preferably, described making on described electric charge tunnel layer is isolated separated first electric charge storage region, district and the second electric charge storage region is:
Described electric charge tunnel layer deposits the first electric charge storage region material, described charge storage layer material etches the first memory block figure;
The second memory block material is deposited after described first memory block figure applies photoresist;
Remove described photoresist by photoresist stripping process, described electric charge tunnel layer is formed the isolated area between the second memory block figure and two charge accumulators.
Preferably, the described grid layer that makes on described electric charge barrier layer is:
Depositing metal layers on described electric charge barrier layer;
Deposition of polysilicon layer on described metal level;
Described metal level and the annealed process of polysilicon layer, form metal silicide gate.
Compared with prior art, the present invention has following advantages:
Flash memories provided by the invention, the charge storage layer between electric charge tunnel layer and electric charge barrier layer is isolated dielectric area and is divided into two electric charge storage regions, and wherein, source area and drain region lay respectively at the both sides in spacer medium district; The conductivity in described spacer medium district is less than the conductivity of described two electric charge storage regions.Two electric charge storage regions keep apart by the spacer medium district adopting conductivity to be less than two independent charge memory blocks, in the material such as silicon-base oxide that spacer medium district adopts, defect concentration is very low, conductivity is less, higher energy barrier is formed between two electric charge storage regions, the electric charge diffusion phenomena between two electric charge storage regions can be suppressed, can not there is crosstalk in the electric charge stored separately in two memory blocks, ensure that the memory reliability of flash memories.
In addition, flash memories of the present invention, in two electric charge storage regions, an electric charge storage region adopts metal nitride nanocrystalline material, the material of another electric charge storage region adopts dielectric constant higher than the nonmetal character semi-conducting material of the dielectric constant of electric charge tunnel layer, due to bi-material separately trapped hole and electronics ability difference larger, when charge injection is carried out to an electric charge storage region, can not phenomenon be injected due to source and the electric charge of another electric charge storage region be impacted, ensure that the memory reliability of flash memories.Flash memories disclosed by the invention is the advantage of combining nano crystal technique and NROM device architecture, in the process keeping data fast access, improves the stability of device.
Accompanying drawing explanation
Shown in accompanying drawing, above-mentioned and other object of the present invention is more clear.Reference numeral identical in whole accompanying drawing indicates identical part.Deliberately do not draw accompanying drawing according to actual size equal proportion convergent-divergent, focus on purport of the present invention is shown.
Fig. 1 is existing NROM memory structural representation;
Fig. 2 is flash memories structural representation of the present invention;
Band structure schematic diagram when Fig. 3 is the grid stacked media layer electron injection of flash memories of the present invention;
Band structure schematic diagram when Fig. 4 is the grid stacked media layer hole injection of flash memories of the present invention;
Fig. 5 is the Making programme figure of flash memories of the present invention;
Fig. 6 to Figure 14 is flash memories manufacturing process schematic diagram of the present invention.
Embodiment
NROM structure flash memory memory make use of the localization storage characteristics of electric charge, realizes the multiple positions stored charge at same charge storage layer, improves the storage density of memory.But, along with memory-size constantly reduces, when existing NROM structure flash memory memory is programmed, multiple position may be caused to store mutual crosstalk and the source injection phenomenon of information, reduce the memory reliability of memory.
Based on above reason, the present invention proposes a kind of flash memories, charge storage layer is made as two mutual independently electric charge storage regions, adopts spacer medium district to be kept apart two electric charge storage regions, the material in described spacer medium district adopts the material that conductivity is lower.Compared with existing NROM structure memory, due to adding of spacer medium district, between two memory blocks, form higher energy barrier, the electric charge diffusion phenomena between electric charge storage region are inhibited, effectively can avoid the impact of two crosstalk phenomenons of memory.
In addition, along with the increase of memory magnitude of the stored charge, higher voltage and longer burst length must be adopted to increase the quantity of electric charge of electric charge storage region injection, when carrying out programming operation to the first electric charge storage region of NROM structure memory, may in the second electric charge storage region also iunjected charge, namely source injects (SSI, Soured-side injection) phenomenon, affect the information stored in the second electric charge storage region, cause the memory reliability of flash memories to reduce.In two electric charge storage regions of flash memories provided by the invention, an electric charge storage region adopts nanocrystalline material, another electric charge storage region adopts dielectric constant higher than the nonmetal character semi-conducting material of electric charge tunnel layer material therefor, by specific program erase parameter, the programming interference problem because source injection phenomenon causes can be avoided, ensure that the memory reliability of flash memories.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the schematic diagram of memory construction can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.
Fig. 2 is the flash memories structural representation of the present embodiment, flash memories comprises Semiconductor substrate 200, grid stacked media layer in Semiconductor substrate, grid layer 206 on grid stacked media layer, be positioned at source area 207 on grid stacked media layer both sides substrate 200 and drain region 208 and its expansion area, grid stacked media layer comprises electric charge tunnel layer 201, charge storage layer, electric charge barrier layer 205 successively.Wherein, described charge storage layer is isolated dielectric area 204 and is divided into two separate electric charge storage regions, first electric charge storage region 202 and the second electric charge storage region 203, source area 207 and drain region 208 lay respectively at the both sides in spacer medium district 204, first electric charge storage region 202 and source area 207 are positioned at the same side in spacer medium district 204, second electric charge storage region 203 and drain region 208 are positioned at the same side in spacer medium district 204, first electric charge storage region is metal nitride nanocrystalline material, second electric charge storage region is amorphous/nano crystal semi-conducting material, the dielectric constant of the second electric charge storage region is higher than the dielectric constant of electric charge tunnel layer.The flash memories of the present embodiment also comprises source electrode, the drain and gate electrode of passivation protection layer 209 and memory, and electrode does not illustrate in the drawings.The conductivity in described spacer medium district is less than the conductivity of two electric charge storage regions, can adopt the silicon-base oxide that defect concentration is very low.
In the present embodiment, the shape in spacer medium district can be strip, the length direction in spacer medium district is along the direction being basically perpendicular to source electrode and drain electrode line, and charge storage layer is divided into two electric charge storage regions, two electric charge storage regions lay respectively at the both sides in spacer medium district.
As can be seen from Figure 2, by concrete industrial manufacturing process, two separate physically electric charge storage regions are formed, i.e. the first electric charge storage region 201 and the second electric charge storage region 203.Physically, by silicon-base oxide or silica-based nitrogen oxide, two memory blocks are kept apart.Because the defect concentration in silicon-base oxide is very low, between two memory blocks, form higher energy barrier, the electric charge diffusion phenomena between memory block are inhibited.Read and reverse read two kinds of channel current reading manners by forward, the data message preserved in the first electric charge storage region and the second electric charge storage region can be extracted respectively.
First electric charge storage region is made up of the metallic nano crystal of titanium nitride or tantalum nitride, and the second electric charge storage region is formed by the binary oxide of hafnium, zirconium, tantalum, ytterbium.Silicon, electric charge tunnel layer is adopted to adopt silicon-base oxide as SiO with substrate
2, the first electric charge storage region adopts that titanium nitride TiN is nanocrystalline, the second electric charge storage region adopts the hafnium oxide HfO that dielectric constant is higher
2for example, Fig. 3 and Fig. 4 is respectively band structure schematic diagram during grid stacked media layer electron injection and the hole injection of the flash memories of the present embodiment, during electron injection, and voltage V on metal gate
gP,
when hole is injected, voltage-V on metal gate
gE,
v
gE, HfO2, V
gE, nc> 0.Electric charge tunnel layer SiO in Fig. 3 and Fig. 4
2can be with 1 with parallelogram signal, the position of the top edge of parallelogram represents SiO
2conduction band at the bottom of, the position of lower limb represents SiO
2top of valence band, HfO
2electric charge storage region can with 3 and electric charge barrier layer can be with 4 position classes seemingly, the nanocrystalline Fermi level 2 of TiN is discrete energy levels.The nanocrystalline electric charge storage region of TiN can with between 2 and grid for electric charge barrier layer can be with 4.E
c, E
vand E
frepresent the conduction band of substrate silicon, valence band and Fermi level respectively.
The work function W that TiN is nanocrystalline
ncrelative to SiO
2conduction band E
c, SiO2difference be about
with SiO
2valence band E
v, SiO2difference be about
hfO
2relative to SiO
2conduction band difference be about
valence band difference is about
therefore, TiN is nanocrystalline passes through SiO
2the ability of tunnel layer trapped electron much larger than the ability of trapped hole, HfO
2pass through SiO
2the ability of tunnel layer trapped electron is less than the ability of trapped hole.If the Fermi level E of substrate silicon
frelative to SiO
2conduction band difference be
valence band difference is
substrate silicon Fermi level and the nanocrystalline work function W of TiN can be obtained
ncthe difference of conduction band
substrate silicon Fermi level and HfO
2conduction band difference
therefore
the difference of substrate silicon Fermi level and the nanocrystalline work function valence band of TiN
substrate silicon Fermi level and HfO
2valence band difference
therefore
if the equivalent oxide thickness of electric charge tunnel layer is T in the present embodiment
oX, the electric field through electric charge tunnel layer is E
oX, the equivalent oxide thickness total through the whole grid stacked media lamination of the nanocrystalline electric charge storage region of TiN is T
eOT, nc, through HfO
2the equivalent oxide thickness that the whole grid stacked media lamination of electric charge storage region is total is
Adopt Fowler-Nordheim mode to carry out programming operation to the memory of the present embodiment, the first electric charge storage region, i.e. the nanocrystalline memory block of TiN, inject electronics by the mode of directly then wearing (direct tunneling), have
voltage on grid is V
gP, nc=E
oX, nc× T
eOT, nc.Second electric charge storage region, i.e. HfO2 memory block, inject electronics by the mode of directly then wearing (direct tunneling), have
grid need the voltage added be
wherein,
according to above-mentioned formula, the voltage that grid adds can be obtained
hfO
2electronics is injected by the direct mode of wearing then in memory block, and the nanocrystalline memory block of TiN assists tunnelling (TAT) mode to inject electronics by defect.Compared to directly then wearing mode, in short time pulse, the amount of electrons of tunneling injection is assisted to ignore by defect.Therefore, for the programming pulse of Millisecond, if
only has HfO
2memory block is filled with electronics.If V
gP> V
gP, nc, the nanocrystalline memory block of TiN and HfO
2all electronics is filled with in memory block.
Equally, adopt Fowler-Nordheim mode to the nanocrystalline memory block of TiN and HfO
2injected hole in memory block, the nanocrystalline memory block of TiN, by directly then wearing mode injected hole, has
grid need the voltage added be V
gE, nc=E
oX, nc× T
eOT, nc.HfO
2memory block, by directly then wearing mode injected hole, has
grid need the voltage added be
Wherein
According to above-mentioned formula, if the voltage added by grid can be obtained
the mode injected hole of the nanocrystalline memory block of TiN by directly then wearing, HfO
2the mode injected hole of tunnelling is assisted by defect in memory block.Compared to directly then wearing (direct tunneling) mode, assisting the hole of tunneling injection to measure by defect in short time pulse can ignore.Therefore, for the programming pulse of Millisecond, if
the nanocrystalline memory block of TiN is only had to be filled with hole.If
the nanocrystalline memory block of TiN and HfO
2all hole is filled with in memory block.
Therefore, if carry out programming operation by Fowler-Nordheim mode to memory, the grid voltage of its programming controls as V
gPwith-V
gE, wherein
v
gPto HfO
2when programming operation is carried out in memory block, TiN does not have electron injection in nanocrystalline memory block, can not affect the information that it stored originally; Otherwise ,-V
gEonly to TiN nanocrystalline memory block injected hole, the i.e. nanocrystalline memory block of TiN and HfO
2independently programming operation can be carried out respectively in memory block.
Electric charge in first electric charge storage region and the second electric charge storage region injects respectively by channel hot idle the mode that (CHHI) and channel hot electron inject (CHEI) and wipes, and concrete program erase operates see table 1.
The table nanocrystalline memory block of 1.TiN and HfO
2the program erase operating parameter that memory block is concrete
Wherein, 0 < V
1< V
2< V
3< V
gE, nc,
v
th, 1, V
th, 2, V
th, 3and V
th, 4for the threshold voltage of flash memories different storage states.
Therefore, in two electric charge storage regions of flash memories, an electric charge storage region adopts nanocrystalline material, another electric charge storage region adopts dielectric constant higher than the conventional material of the amorphous/nano crystal of electric charge tunnel layer material therefor, select program parameters, the programming interference problem because source injection phenomenon causes can be avoided, ensure that the memory reliability of flash memories.
The Making programme of the flash memories of the present embodiment, see Fig. 5, below in conjunction with the concrete manufacturing process that accompanying drawing 6-14 describes memory in detail, comprises the steps:
Step S1, provides Semiconductor substrate.
The Semiconductor substrate provided can be silicon or silicon-on-insulator (SOI, Silicon-On-Insulator) substrate, and this Semiconductor substrate can adjust the doping content of substrate by ion implantation technology.
Step S2, makes electric charge tunnel layer over the substrate.
See Fig. 6, Semiconductor substrate 301 makes electric charge tunnel layer 302.Electric charge tunnel layer 302 can adopt silicon-base oxide or silica-based nitrogen oxide, low temperature chemical vapor deposition technology depositing silicon base oxide or silica-based nitrogen oxide in above-mentioned Semiconductor substrate can be adopted, thermal oxidation technique also can be adopted after above-mentioned deposited on substrates polysilicon to form silica.
Step S3, described electric charge tunnel layer makes and is isolated separated first electric charge storage region, district and the second electric charge storage region, and wherein, described first electric charge storage region and the second electric charge storage region adopt different materials.
Charge storage layer of the present invention comprise two be isolated distinguish every electric charge storage region, the material of the first electric charge storage region can select metal nitride, such as titanium nitride, second electric charge storage region material can adopt the semi-conducting material that dielectric constant is higher, the binary oxide of the elements such as such as hafnium, zirconium, tantalum or ytterbium, this step detailed process is as follows:
See Fig. 6, the electric charge tunnel layer 302 made in step s 2 adopts electron beam evaporation technique plated metal nitride layer 303.
Metal nitride layer applies high temperature resistant photoresist 304, as photoresist NR600, photoetching forms the photoetching offset plate figure of the first electric charge storage region, metal nitride layer not covered by photoresist is removed to exposing electric charge tunnel layer by plasma etching technology etching, see Fig. 7, remaining titanium nitride layer 303 ' is the first electric charge storage region, and the first electric charge storage region can be elongated shape.
Make the second electric charge storage region below, see Fig. 8, retain photoresist layer 305, the photoetching offset plate figure and the electric charge tunnel layer that exposes of above-mentioned making adopt low temperature (< 300 DEG C) technique for atomic layer deposition to deposit the material 305 of the second electric charge storage region.Then the sandwich construction of above-mentioned making is immersed in acetone soln, photoresist is removed by peeling off (lift-off) technique, see Fig. 9, remove the second memory block material be covered in above the first electric charge storage region, stripping technology simultaneously owing to adopting, the the second charge accumulator material be covered on the first electric charge storage region sidewall also can come off, final formation first electric charge storage region 303 ' and the second electric charge storage region 306, and between them, being basically perpendicular to the groove in source and drain line direction, this groove is isolated area 307.
Also can first make the first electric charge storage region in this step, then make the second electric charge storage region.
Step S4, at described isolated area deposition spacer medium material, the isolated area of filling between two electric charge storage regions forms spacer medium district, and the conductivity in described spacer medium district is less than described two electric charge storage regions.
The Material selec-tion conductivity in spacer medium district is lower than the material of two electric charge storage regions, silica-based oxide or nitrogen oxide can be adopted, in the isolated area formed in step s3, deposition spacer medium material, is filled to identical with the electric charge storage region height of both sides by isolated area.
Step S5, described first electric charge storage region, the second electric charge storage region and described spacer medium district make electric charge barrier layer.
See Figure 10, deposited charge barrier layer 307 in the first electric charge storage region, the second electric charge storage region and spacer medium district.Electric charge barrier layer of the present invention for adopting the silicon-base oxide of low-pressure chemical vapor deposition fabrication techniques or silica-based nitrogen oxide, also can adopt identical material with the electric charge made in step S2 with wearing layer.
If electric charge barrier layer adopts identical material with spacer medium district, the making of spacer medium district and electric charge barrier layer can complete in one step.
So far, electric charge tunnel layer, charge storage layer and electric charge barrier layer form the grid stacked media layer of flash memories of the present invention.
Step S6, anneals to each layer of above-mentioned making, the material of the first electric charge storage region is formed nanocrystalline.
See Figure 11, by the sandwich construction that completes in step S5 600 DEG C of annealing in process, make the material nano of the first electric charge storage region 303 ' between electric charge tunnel layer 302 and electric charge barrier layer 307, form the nanocrystalline electric charge storage region 308 of metal nitride.
Step S7, described electric charge barrier layer makes grid layer.
The material of grid layer can be metal, also can be metal silicide, and the present embodiment adopts metal silicide as grid layer.
See Figure 12, utilize ion beam sputtering technology, depositing metal films on the electric charge barrier layer 307 formed in step s 6, the metals such as aluminium, tungsten, titanium can be selected, then on metallic film, pass through low-pressure chemical vapor deposition deposition techniques polysilicon membrane, annealed process forms metal silicide gate layer 309.
Step S8, described grid layer forms figure by exposure, and deposition mask layer forms mask pattern, and etching is not formed gate patterns by the grid layer that mask pattern blocks.
See Figure 12, grown silicon base nitride mask layer 310 on the grid layer 309 made in the step s 7 by low temperature chemical vapor deposition technology, photoetching technique is utilized to form figure on mask layer 310, and the metal silicide layer not having mask cover part is removed by plasma etch apparatus, form gate patterns.
Step S9, each layer etching the above-mentioned making do not covered by mask layer, to exposing substrate, makes source area and drain region in described exposing on substrate.
See Figure 13, each layer film of the grid stacked media Rotating fields utilizing ion beam etching equipment to remove successively not covered by mask layer 310, till being etched to Semiconductor substrate 301.
See Figure 14, utilize ion implantation device, by the ion implantation of various dose and energy, the substrate of grid stacked media layer both sides is formed source dopant region 311 and leaks doped region 312.Formed the source area and drain region that are positioned on the substrate of grid stacked media layer both sides by laser high temperature (1000 DEG C) activation of source drain region, the source area of making and drain region lay respectively at both sides, spacer medium district.
Finally, remove silica-based nitride mask layer, utilize low temperature chemical vapor deposition equipment to form the passivation protection layer of silica-based nitrogen oxide, and draw metal interconnection formation electrode from grid, source electrode and drain electrode respectively, complete the making of flash memories of the present invention.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. a flash memories, comprise Semiconductor substrate, the grid stacked media layer be positioned on substrate, be positioned at grid layer on grid stacked media layer and the source area be positioned on the substrate of grid stacked media layer both sides and drain region, it is characterized in that, described grid stacked media layer comprises:
Be positioned at the electric charge tunnel layer in Semiconductor substrate;
Be positioned at the charge storage layer on described electric charge tunnel layer, described charge storage layer is isolated dielectric area and is divided into two electric charge storage regions, and wherein, source area and drain region lay respectively at the both sides in spacer medium district; The conductivity in described spacer medium district is less than the conductivity of described two electric charge storage regions; Described two electric charge storage regions adopt different materials;
Be positioned at the electric charge barrier layer on described charge storage layer;
In described two electric charge storage regions, first electric charge storage region adopts metal nitride nanocrystalline material, second electric charge storage region adopts amorphous/nano crystal semi-conducting material, and described second electric charge storage region adopts the dielectric constant of dielectric constant higher than described electric charge tunnel layer material of material.
2. flash memories according to claim 1, is characterized in that, described spacer medium district is elongated shape, and its length direction is along the direction perpendicular to source electrode and drain electrode line.
3. flash memories according to claim 1 and 2, is characterized in that, described spacer medium district adopts silicon-base oxide or silica-based nitrogen oxide.
4. flash memories according to claim 1 and 2, is characterized in that, described first electric charge storage region employing titanium nitride nano is brilliant or tantalum nitride is nanocrystalline.
5. flash memories according to claim 1 and 2, is characterized in that, described second electric charge storage region adopts the binary oxide of hafnium, zirconium, tantalum or ytterbium element.
6. flash memories according to claim 1 and 2, is characterized in that, described electric charge tunnel layer adopts silicon-base oxide or silica-based nitrogen oxide.
7. flash memories according to claim 1 and 2, is characterized in that, described electric charge barrier layer adopts silicon-base oxide or silica-based nitrogen oxide.
8. a flash memories manufacture method, is characterized in that, comprises step:
Semiconductor substrate is provided;
Make electric charge tunnel layer over the substrate;
Described electric charge tunnel layer makes and is isolated separated first electric charge storage region, district and the second electric charge storage region, wherein, described first electric charge storage region and the second electric charge storage region adopt different materials;
At described isolated area deposition spacer medium material, the isolated area of filling between two electric charge storage regions forms spacer medium district, and the conductivity in described spacer medium district is less than described two electric charge storage regions;
Described first electric charge storage region, the second electric charge storage region and described spacer medium district make electric charge barrier layer;
Each layer of above-mentioned making is annealed, the material of the first electric charge storage region is formed nanocrystalline;
Described electric charge barrier layer makes grid layer;
Described grid layer forms figure by exposure, and deposition mask layer forms mask pattern, etching is not formed gate patterns by the grid layer that mask pattern blocks;
Etch each layer of the above-mentioned making do not covered by mask layer to exposing substrate, make source area and drain region in described exposing on substrate, described source area and drain region lay respectively at the both sides in described spacer medium district.
9. flash memories manufacture method according to claim 8, is characterized in that, described making on described electric charge tunnel layer is isolated separated first electric charge storage region, district and the second electric charge storage region is:
Described electric charge tunnel layer deposits the first electric charge storage region material, described charge storage layer material etches the first memory block figure;
The second memory block material is deposited after described first memory block figure applies photoresist;
Remove described photoresist by photoresist stripping process, described electric charge tunnel layer is formed the isolated area between the second memory block figure and two charge accumulators.
10. flash memories manufacture method according to claim 8 or claim 9, it is characterized in that, the described grid layer that makes on described electric charge barrier layer is:
Depositing metal layers on described electric charge barrier layer;
Deposition of polysilicon layer on described metal level;
Described metal level and the annealed process of polysilicon layer, form metal silicide gate.
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