KR100866120B1 - A sense amplifier - Google Patents

Abstract

Disclosed is a sense amplifier that maximizes an amplification effect by designing a transistor constituting an input portion of a sense amplifier by varying the size of a channel in advance. As in the present invention, if the channel size of the input transistor is deviated in advance, it is very unlikely that the sense amplifier as a whole malfunctions with respect to process variables. According to an embodiment of the present invention, a sense amplifier includes a first input unit for differentially amplifying a first transistor having a first input terminal applied to a gate and a second transistor having a second input terminal applied to a gate, and a first input terminal applied to a gate The third transistor and the fourth transistor, to which the second input terminal is applied to the gate, comprise a second input unit for differential amplification. At this time, the channel of the first transistor is larger than the channel of the second transistor, the channel of the third transistor is designed to be smaller than the channel of the fourth transistor.

Sense amplifiers, process variables, inputs, transistors, channels, differential amplification

Description

Sense Amplifiers {A SENSE AMPLIFIER}

1 is a circuit diagram of a sense amplifier according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier, and more particularly, to an amplifier that amplifies the data stored in a memory cell in a semiconductor device.

Since the data output from the memory cell and the bit line (bit, bitb) is small in size, a sense amplifier that senses and amplifies a minute voltage difference is required. The sense amplifier, which reliably detects, amplifies, and connects the data stored in the memory cell to the outside, is one of the most important core circuits of dynamic random access memory (DRAM). The requirements for the amplifier include i) high sensitivity, ii) high speed operation, i) wide operating voltage supply range, i) low power consumption and i) small area consumption. A sense amplifier is usually configured with an input structure in a differential amplifier structure. In order to accurately amplify the voltage difference across a bit line without being affected by process variables, a transistor constituting a differential amplifier of an input part is designed to have a long channel.                         

However, designing transistors at the inputs to have long channels is disadvantageous in increasing the density of memory cells. Sometimes, the amplification capability changes depending on process variables, and thus the entire sense amplifier may malfunction. In addition, there may be difficulties in manufacturing a semiconductor device, and the amplification ability thereof is limited.

The present invention has been proposed to solve such a problem, and an object of the present invention is to provide a sense amplifier insensitive to process variables. It is also another object to provide a sense amplifier with a maximized amplification effect.

In connection with this purpose, a sense amplifier is disclosed which maximizes an amplification effect by designing the channel size of a transistor constituting an input of a sense amplifier in advance. As in the present invention, if the channel size of the input transistor is deviated in advance, it is very unlikely that the sense amplifier as a whole malfunctions with respect to process variables.

According to an embodiment of the present invention, a sense amplifier includes a first input unit for differentially amplifying a first transistor having a first input terminal applied to a gate and a second transistor having a second input terminal applied to a gate, and a first input terminal applied to a gate The third transistor and the fourth transistor, to which the second input terminal is applied to the gate, comprise a second input unit for differential amplification. At this time, the channel of the first transistor is larger than the channel of the second transistor, the channel of the third transistor is designed to be smaller than the channel of the fourth transistor.                     

The latch circuit may further include a latch unit configured to output the voltage applied to the drain of the first transistor as it is, and to invert and output the voltage applied to the drain of the fourth transistor.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; In the drawings, the same reference numerals are used to refer to the same or similar components and signals for the sake of consistency of description.

1 is a circuit diagram of a sense amplifier according to an embodiment of the present invention. As shown in FIG. 1, the sense amplifier 100 includes two input units 110 and 120 that form a differential amplifier. In the input unit 110, two NMOS transistors N1 and N2 constitute a differential amplifier. In the NMOS transistor N1, where a signal of a bit line is applied to a gate, a signal of a bit line is connected to a gate. The channel width is wider than that of the applied NMOS transistor N2. In the input unit 120, two NMOS transistors N3 and N4 form a differential amplifier. In the NMOS transistor N3 to which the signal of the bit line is applied to the gate, the signal of the bit line is connected to the gate. The width is narrower than that of the applied NMOS transistor N4. In other words, two input units 110 and 120 having opposite channel levels are connected in parallel to the input terminals bit and bitb. In this embodiment, the channel length of the transistors N1, N2, N3, and N4 is fixed and only the channel width is controlled. However, the channel width may be fixed and the channel length may be controlled. In FIG. 1, the signal pse1i is an enable signal for controlling whether or not sense amplification is performed, and the signal pse2i is an enable signal for controlling whether or not the output of the sense amplification result is output.

An operation of the sense amplifier 100 will be described below with reference to FIG. 1. For convenience of explanation, a signal applied to a bit line is represented as a bit and a signal applied to a bit bar line is represented as a bit b as long as there is no risk of confusion. The signals bit and bitb constitute an input signal of the sense amplifier 100. First, a case in which a signal bit is at a high level and a signal bitb is at a low level will be described. In this case, the channels of the transistors N1 and N2 of the input unit 110 have a normal deviation with respect to the input signals bit and bitb. The node nd1 is turned low because the transistor N1 is turned on by the signal bit, and the node nd2 is turned high because the transistor N2 is turned off by the signal bitb. The signal of the node nd1 is input to the inverter I18 via the pass gate T0 while the enable signal pse2i is at the high level, and is inverted by the inverter I18 to invert the high level signal sense_out. Output The latch unit 130 maintains a low level signal of the node nd1. On the other hand, the node nd3 of the input unit 120 has a lower driving capability than the node nd1 and thus cannot change the level of data latched in the latch unit 130. When the signal bit is high level and the signal bitb is low level as described above, the high level signal sense_out is output through the input unit 110 and the latch unit 130.

Next, the case where the signal bit is at the low level and the signal bitb is at the high level will be described. In this case, the channels of the transistors N3 and N4 of the input unit 120 have a normal deviation with respect to the input signals bits and bitb. Since the transistor N3 is turned off by the signal bit, the node nd4 is at a high level, and the node nd3 is turned at the low level because the transistor N4 is turned on by a signal bitb. The signal of the node nd3 is inverted by the inverter I19 of the latch unit 130 and input to the pass gate TO. The input signal is input to the inverter I18 via the pass gate T0 while the enable signal pse2i is at the high level, and is inverted by the inverter I18 to output the low level signal sense_out. . The latch unit 130 maintains a low level signal of the node nd3. On the other hand, the node nd1 of the input unit 110 has a lower driving capability than the node nd3 and thus cannot change the level of data latched in the latch unit 130. When the signal bit is low level and the signal bitb is high level, the low level signal sense_out is output through the input unit 120 and the latch unit 130.

When the signal bit is at a high level and the signal bitb is at a low level, the amplification sensitivity is optimized at the input unit 110, and the amplification sensitivity may be lowered or amplified at the input unit 120. On the other hand, when the signal bit is at a low level and the signal bitb is at a high level, the amplification sensitivity is optimized at the input unit 120, and the amplification sensitivity may be lowered or reversely amplified at the input unit 110. Therefore, when the signal bit is high level and the signal bitb is low level, the signal is amplified using the input unit 110. When the signal bit is low level and the signal bitb is high level, the input unit 120 is used. By amplifying using a) to maximize the amplification effect by the sense amplifier (100).

The embodiments described herein are merely intended to enable those skilled in the art to easily understand and practice the present invention, and are not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications or changes are possible within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.

The sense amplifier of the present invention having such a configuration is insensitive to process variables and has an maximized amplification effect.

Claims (4)

In the sense amplifier for amplifying the difference between the voltage applied to the first input terminal and the second input terminal and outputs through the output terminal, A first input unit having a first transistor to which the first input terminal is applied to a gate and a second transistor to which the second input terminal is applied to a gate, wherein the first transistor and the second transistor constitute a differential amplifier Wow, A second input having a third transistor to which the first input terminal is applied to the gate and a fourth transistor to which the second input terminal is applied to the gate, wherein the third input and the fourth transistor constitute a differential amplifier; To call Include, And a channel of the first transistor is larger in size than a channel of the second transistor, and a channel of the third transistor is smaller in size than a channel of the fourth transistor. The method of claim 1, And a latch unit for outputting the voltage applied to the drain of the first transistor as it is, and inverting and outputting the voltage applied to the drain of the fourth transistor. The method of claim 1, The channel width of the channel of the first transistor is greater than the width of the channel of the second transistor, the width of the channel of the third transistor is smaller than the width of the channel of the fourth transistor sense amplifier. The method of claim 1, The channel length of the channel of the first transistor is smaller than the channel length of the second transistor, the length of the channel of the third transistor is greater than the length of the channel of the fourth transistor.

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