KR100864978B1 - Gamma-correction method and apparatus of liquid crystal display device - Google Patents

Abstract

The present invention relates to a gamma compensation method and apparatus for a liquid crystal display device to improve display quality.

The gamma compensation method of the liquid crystal display device uses the gamma reference voltages of GMA1 to GMAi in stages i (where i is a positive integer) generated at the output terminals of the voltage divider resistor circuit. A gamma compensation method of a liquid crystal display device for gamma compensating digital data belonging to each of the intermediate gray scale ranges between the white gray scale range and the black gray scale range, the gamma reference belonging to the black gray scale range and the intermediate gray scale range in the voltage divider resistor circuit. Generating a halftone between the gamma reference voltages by connecting resistors in series between the terminals for outputting voltages; The i-1 gamma reference voltage (GMAi-1) is removed by removing a resistance between terminals outputting the i-1 gamma reference voltage (GMAi-1) and the i-th gamma reference voltage (GMAi) respectively within the white gray scale range. Removing an intermediate gradation between the gradation of?) And the gradation of the i-th gamma reference voltage GMAi; And converting the digital data belonging to the white gradation range and the digital data belonging to a gradation range other than the white gradation range with the gamma reference voltages.

Description

Gamma Compensation Method and Apparatus for Liquid Crystal Display Device {GAMMA-CORRECTION METHOD AND APPARATUS OF LIQUID CRYSTAL DISPLAY DEVICE}             

1 illustrates a conventional gamma curve applied to a liquid crystal display device in a normally white mode.

2 is a circuit diagram schematically showing a conventional gamma compensation voltage generating circuit.

FIG. 3 is an enlarged circuit diagram of portion 'A' in FIG. 2.

4 is a graph schematically illustrating a gamma curve by rotating the positive portion shown in FIG. 1 by 90 °.

5 is a block diagram schematically illustrating a driving device of a liquid crystal display device according to an exemplary embodiment of the present invention.

6 is a block diagram illustrating in detail the data driver illustrated in FIG. 5.

FIG. 7 is a circuit diagram illustrating in detail a positive voltage divider circuit of the gamma voltage supply unit illustrated in FIG. 6.

FIG. 8 is a circuit diagram illustrating in detail a negative voltage divider resistance circuit of the gamma voltage supply unit illustrated in FIG. 6.

FIG. 9A is a graph illustrating a change between inter-gradation in a gray scale, a change in an intermediate gray scale, and a black gray scale in a gamma compensation method and apparatus according to an exemplary embodiment of the present invention.

9B is a graph showing an optimal 2.2 gamma curve.

FIG. 10 is a graph illustrating a gamma compensation voltage output from the voltage dividing resistor circuits of FIGS. 7 and 8 and a change in transmittance.

<Description of Symbols for Main Parts of Drawings>

1: Timing Controller 2: Data Driver

3: gate driver 4: gamma reference voltage supply

5 liquid crystal panel 21 data register

22: shift register 23, 24: latch

25: DAC 26: output circuit

27: gamma voltage supply unit

The present invention relates to a liquid crystal display device, and more particularly to a gamma compensation method and apparatus for a liquid crystal display device to improve the display quality.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. An active matrix liquid crystal display device in which switching elements are formed for each liquid crystal cell is suitable for displaying moving images. As a switching device used in an active matrix type liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used.

In such a liquid crystal display device, a gradation range that can be expressed by digital input data is set, and each gradation voltage is determined as a gamma compensation voltage. The gamma compensation voltage is set in consideration of the algebraic feeling of the stimulus value according to the visual perception characteristic when a person sees an image. When the brightness corresponding to each gray level, that is, the light transmittance is T and the gray level is G, the relationship between each gray level and its brightness is expressed by Equation 1 below.

(Gamma)는 1보다 큰 상수로 나타내고자 하는 실물과 화면의 느낌이 맞도록 정해진다. 액정표시소자의 감마보상방식에서 적용되는

는 2∼4이다. Where k is the proportional constant

Gamma is set to a constant greater than 1 so that the real and the screen feel fit. Applied in Gamma Compensation of Liquid Crystal Display Devices

Is 2-4.

는 2.2이다. Considering the liquid crystal characteristics and human visual perception characteristics, it is possible to obtain an optimum viewing angle and luminance in the liquid crystal display device.

Is 2.2.

As shown in FIG. 1, the driving circuit of the liquid crystal display generates gamma compensation voltages corresponding to the respective gray levels of the digital input data.

When the digital input data is 6 bits, the gamma compensation voltage is divided into 64 steps. The data driving circuit of the liquid crystal display device (not shown) decodes the digital input data and selects a gamma compensation voltage corresponding to the decoded gray value to supply the liquid crystal cell.
The gamma compensation voltage is divided by the gamma reference voltages GMA1 to GMA10 divided into 10 steps and the gamma reference voltages GMA1 to GMA10 divided into 10 levels in the entire gray scale range of 64 steps as shown in FIGS. 2 and 3. To gamma compensation voltages VH0 to VH63 respectively corresponding to the divided gray scales. In FIG. 1, dots represent subdivided gray levels corresponding to gamma compensation voltages VH0 to VH63, respectively.

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2 and 3, the conventional gamma compensation voltage generation circuit divides the supply voltage from the external power source 21 for the reference power supply and divides the positive and negative gamma divided into five stages in the positive and negative polarities, respectively. The reference voltages GMA1 to GMA10 are generated. The gamma reference voltages GMA1 to GMA10 are gamma compensation voltages corresponding to respective steps when the total gray scale to be expressed is divided into five levels. In the conventional gamma compensation voltage generation circuit, the gamma compensation voltages GAM1 to GMA10 are subdivided to generate gamma compensation voltages VH0 to VH63 corresponding to the respective gray levels. To this end, the conventional gamma compensation voltage generating circuit has 15 gamma reference voltages (GMA1 to GMA10) between adjacent stages, for example, between GMA1 and GMA2, between GMA2 and GMA3, ..., between GAM9 and GMA10, respectively. Or 16 resistors connected in series. That is, 15 or 16 equal numbers (R1 = R2 = R3 = R4 = R5 = R6 = R7 = R8) are formed between the gamma reference voltages GMA1 to GMA10.

Gamma tuning to implement the gamma curve is performed depending on the adjustment of the gamma reference voltage (GMA1 to GMA10). When the gamma reference voltages GMA1 to GMA10 are set, the gamma compensation voltages VH0 to VH63 are automatically set by 15 or 16 resistors R1 to R8 existing between the gamma reference voltages GMA1 to GMA10. Is determined. As a result, the divided gamma compensation voltages VH0 to VH63 between the gamma reference voltages GMA1 to GMA10 are divided stepwise by the number of resistors.

However, the conventional gamma compensation method has a problem in that gamma compensation is not precisely performed due to resistors existing in the same number between the gamma reference voltages GMA1 to GMA10. In particular, according to the conventional gamma compensation method, gamma compensation cannot be precise in the white gradation range having a high gradation value and the black gradation range having a low gradation value.

In detail, as shown in FIG. 1, the gamma curve region including the white gray scale range of approximately 56 (hexadecimal 38) to 64 (hexadecimal 3F) is nonlinear due to the 15 resistances in between. do. In addition, the gamma curve section including the black gradation range of approximately 0 to 8 causes the gamma curve to become nonlinear due to the 15 resistances therebetween. As a result, the conventional gamma curve is divided into a first non-linear section 61 and a second non-linear section 62 represented by an exponential function as shown in FIG.

가 2.2이고 전계조범위에서 계조간 변화가 선형화에 근접할 수 있는 최적의 2.2 감마커브는 도 9b와 같다. 제2 비선형구간(62)은 감마기준전압이나 저항들의 저항값을 튜닝하여 계조변화가 선형화에 근접하는 최적의 2.2 감마커브로 구현될 수 있다. 그러나 제1 비선형구간(61)은 저항들의 수만큼 계조변 화가 세분화되기 때문에 감마기준전압이나 저항들의 저항값 튜닝에 의해서 계조변화가 선형화에 근접하는 최적의 2.2 감마커브로 구현될 수 없다. In Equation 1

Is 2.2 and the optimal 2.2 gamma curve whose variation between gray levels in the full gray scale range is close to linearization is shown in FIG. 9B. The second nonlinear section 62 may be implemented with an optimal 2.2 gamma curve in which gray level change approaches linearization by tuning a gamma reference voltage or resistance values of resistors. However, since the gray scale variation is divided by the number of resistors, the first nonlinear section 61 may not be implemented as an optimal 2.2 gamma curve in which the gray scale variation approaches the linearization by tuning the gamma reference voltage or the resistance of the resistors.

As a result, according to the conventional gamma compensation circuit, the difference between the gray scales in the white gray scale range and the black gray scale range cannot be clearly distinguished by a human being, which inevitably reduces the clarity of the display image.

Accordingly, an object of the present invention is to provide a gamma compensation method and apparatus for a liquid crystal display device to improve display quality.

In order to achieve the above object, the gamma compensation method of a liquid crystal display device according to an embodiment of the present invention is the gamma reference of the GMA1 to GMAi of the step i (where i is a positive integer) generated at the output terminals of the voltage divider resistor circuit. A gamma compensation method of a liquid crystal display device which gamma compensates digital data belonging to each of a white gradation range, a black gradation range, and an intermediate gradation range between the white gradation range and the black gradation range by using voltages. Generating an intermediate gradation between the gamma reference voltages by connecting resistors in series between the terminals outputting the gamma reference voltages within the black gradation range and the intermediate gradation range at; The i-1 gamma reference voltage (GMAi-1) is removed by removing a resistance between terminals outputting the i-1 gamma reference voltage (GMAi-1) and the i-th gamma reference voltage (GMAi) respectively within the white gray scale range. Removing an intermediate gradation between the gradation of?) And the gradation of the i-th gamma reference voltage GMAi; And converting the digital data belonging to the white gradation range and the digital data belonging to a gradation range other than the white gradation range with the gamma reference voltages.
A gamma compensation device for a liquid crystal display device according to an embodiment of the present invention includes: a voltage source for generating gamma reference voltages of GMA1 to GMAi divided in step i; By connecting resistors in series between the terminals outputting the gamma reference voltages in the black gray range and the mid gray range, a half gray level is generated between the gamma reference voltages, and the i-1 gamma reference in the white gray range. The gray level of the i-1 gamma reference voltage GMAi-1 and the i-th gamma reference voltage GMAi are removed by removing a resistance between the terminals outputting the voltages GMAi-1 and i-gamma reference voltages GMAi, respectively. A voltage divider resistance circuit in which an intermediate gradation is removed between the gradations; And a data driver for converting digital data belonging to the white gradation range and digital data belonging to a gradation range other than the white gradation range with gamma output from the voltage divider resistor circuit.

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Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.                     

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 10.

Referring to FIG. 5, in the driving apparatus of the liquid crystal display according to the exemplary embodiment of the present invention, the data lines DL1 to DLm and the gate lines GL1 to GLn cross each other and drive the liquid crystal cell Clc at the intersection thereof. A liquid crystal panel 5 having TFTs formed therein, a data driver 2 for supplying data to the data lines DL1 to DLm of the liquid crystal panel 5, and gate lines GL1 to GLn of the liquid crystal panel 5. ), A gate driver 3 for supplying a scanning pulse to the gate driver, a gamma reference voltage generator 4 for supplying a gamma reference voltage GMA to the gate driver 3, a data driver 2, and a gate driver And a timing controller 1 for controlling 3).

In the liquid crystal panel 5, liquid crystal is injected between two glass substrates. On the lower glass substrate of the liquid crystal panel 5, the data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal to each other. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scanning pulse. The gate electrodes of the TFTs are connected to the gate lines GL1 to GLm, and the source electrodes of the TFTs are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The timing controller 1 supplies digital video data supplied from a digital video card (not shown) to the data driver 2. In addition, the timing controller 1 generates a data drive control signal DDC and a gate drive control signal GDC using the horizontal / vertical synchronization signals H and V input thereto. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and the like. This data drive control signal DDC is supplied to the data driver 2. The gate driving control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like. The gate drive control signal GDC is supplied to the gate driver 3.

The gate driver 3 sequentially generates scan pulses, that is, gate high pulses, in response to the gate driving control signal GDC supplied from the timing controller 1. The gate driver 3 includes a shift register for sequentially generating scan pulses, and a level shifter for shifting the swing width of the scan pulse voltage to be suitable for driving the liquid crystal cell Clc. The TFT is turned on in response to the scan pulse from the gate driver 3. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The gamma reference voltage generator 4 supplies a predetermined number of positive and negative gamma reference voltages GMA to the data driver 2, respectively. The gamma reference voltage generator 4 divides the reference voltage from the external power source 21 for reference power supply as shown in FIG. 2 into a voltage divider to generate a plurality of gamma reference voltages having different voltage levels in the positive and negative polarities. .

The data driver 2 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 1. After the data driver 2 samples the data RGB from the timing controller 1, the data driver 2 latches the data and converts the data into a gamma voltage. This data driver 2 is implemented with a plurality of integrated circuits (hereinafter referred to as " IC ") 2a having the configuration as shown in FIG.

Each data IC 2a comprises a data register 21 into which data RGB is input from the timing controller 1, a shift register 22 for generating a sampling clock, a shift register 22 and k (where , k is an integer smaller than m, and the first latch 23, the second latch 24, and the digital to analog converter (DAC) connected between the data lines DL1 to DLk. 25 and an output circuit 26, and a gamma voltage supply unit 27 connected between the gamma reference voltage generator 4 and the DAC 25.

The data register 21 temporarily stores the data RGB from the timing controller 1 and supplies the stored data RGB to the first latch 23.

The shift register 22 shifts the source start pulse SSP from the timing controller 1 in accordance with the source sampling clock signal SSC to generate a sampling signal. In addition, the shift register 22 shifts the source start pulse SSP to transfer the carry signal CAR to the next stage shift register 22.

In response to a sampling signal sequentially input from the shift register 22, the first latch 23 samples the data RGB from the data register 21 and latches the data by one line, and then simultaneously stores one line of data. Output

The second latch 24 latches data input from the first latch 23, and then simultaneously outputs the latched data in response to the source output enable signal SOE from the timing controller 1.

The DAC 25 converts the digital data from the second latch 24 to the gamma voltage from the gamma voltage supply unit 27. The DAC 25 includes a multiplexer for selecting any one of a positive gamma voltage and a negative gamma voltage in response to the polarity control signal POL.

The output circuit 26 includes a buffer connected to each of the data lines. The buffer of the output circuit 26 amplifies the data by its gain value to minimize signal attenuation.

The gamma voltage supplier 27 subdivides the gamma reference voltage GMA input from the gamma reference voltage generator 4 to supply the gamma voltage corresponding to each gray level to the DAC 25. The gamma voltage supply unit 27 is composed of a circuit for generating a gamma voltage of positive polarity and a voltage divider resistance circuit for generating a gamma voltage of negative polarity.

7 shows a positive voltage divider resistance circuit of the gamma voltage supply part 27, and FIG. 8 shows a negative voltage divider resistance circuit of the gamma voltage supply part 27. As shown in FIG.

7 and 8, in the positive voltage divider resistance circuit according to the exemplary embodiment of the present invention, the resistance is omitted between the positive gamma reference voltages GMA4 and GMA5 in the white gradation range. Eight resistors (R101 to R108) are connected in series between the positive gamma reference voltages GMA1 and GMA2 in the black gradation range, and between the positive gamma reference voltages GMA2 and GMA3 and GMA3 and GMA4 in the middle gradation range, respectively. Twenty six resistors R201 to R226 and R301 to R326 are connected in series. That is, the intermediate gray scale between the gamma reference voltages GMA4 and GMA5 is omitted in the white gray scale range, and the number of intermediate gray scales between the gamma reference voltages GMA1 and GMA2 in the black gray scale range, and between the gamma reference voltages GMA2 and GMA3 within the gray scale range. Or the number of halftones between GMA3 and GMA4 is different. Similarly, in the negative voltage divider resistance circuit, the resistance is omitted between the negative gamma reference voltages GMA6 and GMA7 in the white gradation range. Eight resistors (R101 to R108) are connected in series between the negative gray gamma reference voltages GMA9 and GMA10 in the black gradation range, and between the negative gamma reference voltages GMA8 and GMA9 and GMA8 and GMA9 respectively in the middle gray scale range. Twenty six resistors R201 to R226 and R301 to R326 are connected in series. That is, the intermediate gray scale between the gamma reference voltages GMA4 and GMA5 in the white gray scale range is omitted. The number of grayscales between the gamma reference voltages GMA6 and GMA7 in the black gray scale range and the number of grayscales between the gamma reference voltages GMA7 and GMA8 or GMA8 and GMA9 within the grayscale range are different.

In the conventional gamma compensation method, as shown in FIG. 9A, there are almost half the gray level difference between the gamma reference voltages GMA4 and GMA5 along the curve 91 indicated by the dotted lines in the white gray range and the black gray range. There was no. In contrast, in the gamma compensation method according to the embodiment of the present invention, there is no intermediate gray level between the gamma reference voltages GMA 5 and GMA 4 in the white gray scale range, and thus, the highest level corresponding to the gamma reference voltage GMA 5 as shown by arrow 92. The next gradation of the gradation becomes the gradation corresponding to GMA 4, and the number of resistances in the intermediate gradation range, that is, the number of intermediate gradations, increases, so that the change in transmittance according to the gamma compensation voltage in the intermediate gradation range and the white gradation range becomes almost linear, The difference in transmittance becomes apparent. In addition, the gamma compensation method according to the embodiment of the present invention reduces the number of resistances between the gamma reference voltages GMA 1 and GMA 2, that is, the number of intermediate gray levels, on the black gray scale, and thus the change in transmittance according to the gamma compensation voltage in the black gray range is almost reduced. It becomes linear and the difference in transmittance between gray levels becomes apparent.

10 illustrates a gamma curve of positive and negative polarity in a gamma compensation method and apparatus of a liquid crystal display according to an exemplary embodiment of the present invention.

As can be seen from the comparison of FIG. 1 and FIG. 10, the gamma compensation method and apparatus of the liquid crystal display according to the exemplary embodiment of the present invention linearize the gamma curve between gray scales in the white gray range, the intermediate gray range, and the black gray range. The difference in transmittance can be further equalized to achieve an optimal 2.2 gamma curve. In FIG. 10, when the digital input data is 6 bits, the gamma reference voltages GMA1 and GMA10 are gamma compensation voltages corresponding to grayscale values '0', and the gamma reference voltages GMA2 and GMA9 correspond to grayscale values '8'. Gamma compensation voltage. The gamma reference voltages GMA3 and GMA8 are gamma compensation voltages corresponding to the gray value '35', and the gamma reference voltages GMA4 and GMA7 are gamma compensation voltages corresponding to the gray value '62'. The gamma reference voltages GMA5 and GMA6 are gamma compensation voltages corresponding to the gray value '63'.

As described above, the gamma compensation method and apparatus of the liquid crystal display according to the present invention by linearizing the gamma curve in the entire range of gradations that can be expressed allows a person to feel the difference in brightness between each gradation to increase the sharpness of the display image. The display quality can be improved as much.                     

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. For example, in the exemplary embodiment of the present invention, the inversion of only one bit of the most significant bit is illustrated. However, the data voltage supplied to the liquid crystal cell may be changed in multiple steps by inverting two or more bits or other bits other than the most significant bit. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

White gradation range, black gradation range, and the white gradation range and the black gradation range using the gamma reference voltages of GMA1 to GMAi in stages i (where i is a positive integer) generated at the output terminals of the voltage divider resistor circuit. In the gamma compensation method of a liquid crystal display device for gamma compensating digital data belonging to each of the intermediate gradation ranges between Generating a halftone between the gamma reference voltages by connecting resistors in series between the terminals for outputting the gamma reference voltages in the black and midtone ranges in the voltage divider circuit; The i-1 gamma reference voltage (GMAi-1) is removed by removing a resistance between terminals outputting the i-1 gamma reference voltage (GMAi-1) and the i-th gamma reference voltage (GMAi) respectively within the white gray scale range. Removing an intermediate gray level between the gray level of the i) and the gray level of the i-th gamma reference voltage GMAi; And And converting the digital data belonging to the white gradation range and the digital data belonging to a gradation range other than the white gradation range with the gamma reference voltages. delete delete By using the gamma reference voltages of GMA1 to GMAi in steps i (where i is a positive integer) generated at the output terminals of the voltage divider resistance circuit, the white gray range, the black gray range, and the white gray range and the black gray range A gamma compensator of a liquid crystal display device for gamma compensating digital data belonging to each of the intermediate gradation ranges of A voltage source generating gamma reference voltages of GMA1 to GMAi divided into the i stages; By connecting resistors in series between the terminals outputting the gamma reference voltages in the black gray range and the mid gray range, a half gray level is generated between the gamma reference voltages, and the i-1 gamma reference in the white gray range. The gray level of the i-1 gamma reference voltage GMAi-1 and the i-th gamma reference voltage GMAi are removed by removing a resistance between the terminals outputting the voltages GMAi-1 and i-gamma reference voltages GMAi, respectively. A voltage divider resistance circuit in which an intermediate gradation is removed between the gradations; And And a data driver for converting the digital data belonging to the white gradation range and the digital data belonging to a gradation range other than the white gradation range with the gamma output from the voltage divider resistor circuit. delete delete The method of claim 4, wherein The voltage divider circuit, A first resistor string configured to generate gray voltages in the black gray range by eight resistors connected in series between terminals outputting a first gamma reference voltage GMA1 and a second gamma reference voltage GMA2; 26 resistors are connected in series between the terminals outputting the second gamma reference voltage GMA2 and the third gamma reference voltage GMA3, and the third gamma reference voltage GMA3 and the fourth gamma reference voltage ( And a second resistor string, in which 26 resistors are connected in series between the terminals for outputting the GMA4, to generate the gray scale voltages of the intermediate gray scale range.

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