KR100864623B1 - Method for forming flash memory device - Google Patents
Method for forming flash memory device Download PDFInfo
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- KR100864623B1 KR100864623B1 KR1020060028618A KR20060028618A KR100864623B1 KR 100864623 B1 KR100864623 B1 KR 100864623B1 KR 1020060028618 A KR1020060028618 A KR 1020060028618A KR 20060028618 A KR20060028618 A KR 20060028618A KR 100864623 B1 KR100864623 B1 KR 100864623B1
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- 238000000034 method Methods 0.000 title claims description 9
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 238000007667 floating Methods 0.000 claims abstract description 13
- 230000001681 protective effect Effects 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000000126 substance Substances 0.000 claims description 9
- 229910052945 inorganic sulfide Inorganic materials 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
Abstract
본 발명은 플로팅 게이트의 차지 트랩 사이트를 방지하는데 적합한 플래쉬 메모리 제조 방법을 제공하기 위한 것으로, 이를 위한 본 발명의 플래쉬 메모리 소자 제조 방법은 반도체 기판 상에 알루미늄산화막을 포함하는 게이트 절연막을 형성하는 단계; 상기 게이트 절연막 상에 플로팅 게이트를 형성하는 단계; 상기 알루미늄산화막의 양측벽에 측벽보호막을 형성하는 단계를 포함하고, 상기 측벽보호막을 형성하는 단계는, 상기 알루미늄산화막의 양측벽에 습식 처리를 실시하여 구현한다. 이에 따라 본 발명은 플래쉬 메모리 디바이스에 대한 수율 향상을 확보할 수 있는 효과가 있다.The present invention provides a flash memory manufacturing method suitable for preventing the charge trap site of the floating gate, the flash memory device manufacturing method of the present invention for forming a gate insulating film comprising an aluminum oxide film on a semiconductor substrate; Forming a floating gate on the gate insulating film; Forming a sidewall protective film on both sidewalls of the aluminum oxide film, and the forming of the sidewall protective film is implemented by performing wet treatment on both sidewalls of the aluminum oxide film. Accordingly, the present invention has the effect of ensuring a yield improvement for a flash memory device.
플래쉬 메모리, 고유전 물질, 알루미늄산화막, 플로팅 게이트 Flash memory, high dielectric materials, aluminum oxide, floating gate
Description
도 1은 종래 기술에 따른 플래쉬 메모리 제조 형성 방법을 도시한 단면도,1 is a cross-sectional view showing a flash memory manufacturing method according to the prior art,
도 2a 및 도 2b는 본 발명의 일실시예에 따른 플래쉬 메모리 제조 방법을 도시한 단면도. 2A and 2B are cross-sectional views illustrating a flash memory manufacturing method according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 터널산화막21
23 : 질화막 24 : 알루미늄산화막23
25 : 플로팅게이트용 폴리실리콘막 25: polysilicon film for floating gate
본 발명은 반도체 제조 기술에 관한 것으로, 플래쉬 메모리 소자 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and to a flash memory device and a method for manufacturing the same.
낸드 플래쉬(NAND FLASH) 디바이스의 경우 커플링 비(Coupling Ratio) 확보 및 누설 전류(Leakage Current) 감소를 위한 소자 개발이 진행중이며, 이에 따라 플로팅 게이트(Floating Gate) 역할을 수행하는데 있어서 고유전 물질(High-K)인 알루미늄산화막(Al2O3)을 게이트 산화막(Gate Oxide)으로 적용하는 공정을 개발중이다.In the case of NAND FLASH devices, development of devices for securing a coupling ratio and reducing leakage current is in progress. Accordingly, a high dielectric material (NFFL) serves as a floating gate. A process of applying aluminum oxide (Al 2 O 3 ), which is a high-K, as a gate oxide, is being developed.
도 1은 종래 기술에 따른 플래쉬 메모리 제조 방법을 나타낸 단면도이다.1 is a cross-sectional view showing a flash memory manufacturing method according to the prior art.
도 1에 도시된 바와 같이, 반도체 기판(11) 상에 터널산화막(12), 질화막(13), 알루미늄산화막(14) 및 플로팅게이트(15)가 차례로 적층된 게이트 패턴(G)을 형성한다. As shown in FIG. 1, a gate pattern G in which a
그러나, 종래 기술에서 게이트 산화막으로 사용된 알루미늄산화막은 다른 산화막에 비해 쉽게 산화되려는 경향이 강하다. 따라서, 게이트 패턴 형성시 사용되는 플라즈마 건식 식각 이후 노출되는 알루미늄산화막의 양측벽(도 1의 'A'참조)에 댕글링 본드가 형성되며, 댕글링 본드와 플라즈마 건식 식각시 사용된 플라즈마가 반응하여 케미컬 산화막(Chemical Oxide)이 형성된다. 이로 인해 알루미늄산화막의 표면 상태 밀도(Surface State Density) 증가하여 차지 트랩(Charge trap) 등 누설 소스로 작용하게 된다.However, the aluminum oxide film used as the gate oxide film in the prior art tends to be easily oxidized compared to other oxide films. Therefore, dangling bonds are formed on both sidewalls (see 'A' of FIG. 1) of the aluminum oxide film exposed after the plasma dry etching used to form the gate pattern, and the dangling bond reacts with the plasma used during the plasma dry etching. A chemical oxide film is formed. As a result, the surface state density of the aluminum oxide film is increased to act as a leakage source such as a charge trap.
이러한 상태는 후속 디바이스 제조시 수반되는 후속 열공정 적용시 디바이스의 신뢰성에도 문제를 끼칠 수 있다. 따라서, 알루미늄산화막을 적용할 때 알루미늄산화막의 차지 손실(Charge loss)을 방지하기 위하여는 알루미늄산화막에 따른 적절한 습식 처리(Wet Treatment)가 요구된다.This condition can also pose a problem for the reliability of the device in subsequent thermal process applications involved in subsequent device fabrication. Therefore, in order to prevent charge loss of the aluminum oxide film when applying the aluminum oxide film, an appropriate wet treatment according to the aluminum oxide film is required.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 플로팅 게이트의 차지 트랩 사이트를 방지하는데 적합한 플래쉬 메모리 및 그 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a flash memory suitable for preventing the charge trap site of the floating gate and a manufacturing method thereof.
삭제delete
또한, 본 발명의 플래쉬 메모리 소자 제조 방법은 반도체 기판 상에 알루미늄산화막을 포함하는 게이트 절연막을 형성하는 단계; 상기 게이트 절연막 상에 플로팅 게이트를 형성하는 단계; 상기 알루미늄산화막의 양측벽에 측벽보호막을 형성하는 단계를 포함하고, 상기 측벽보호막을 형성하는 단계는, 상기 알루미늄산화막의 양측벽에 습식 처리를 실시하는 것을 특징으로 한다.In addition, the flash memory device manufacturing method of the present invention comprises the steps of forming a gate insulating film comprising an aluminum oxide film on a semiconductor substrate; Forming a floating gate on the gate insulating film; Forming a sidewall protective film on both sidewalls of the aluminum oxide film, and the forming of the sidewall protective film is characterized by performing wet treatment on both sidewalls of the aluminum oxide film.
이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .
도 2a 및 도 2b는 본 발명의 일실시예에 따른 플래쉬 메모리 소자 제조 방법을 도시한 단면도이다.2A and 2B are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체 기판(21) 상에 터널산화막(22), 질화막(23), 알루미늄산화막(24) 및 플로팅게이트용 폴리실리콘막(25)이 차례로 적층된 게이트 패턴(G)을 형성한다.As shown in FIG. 2A, the gate pattern G in which the
먼저 게이트 패턴(G)을 형성하는 단계는, 반도체 기판(21) 상에 터널산화막(22)을 형성한다. 터널산화막(22)은 열산화막(Thermal Oxide)을 사용한다.First, in forming the gate pattern G, the
그리고 나서, 터널산화막(22) 상에 질화막(23), 알루미늄산화막(24) 및 플로팅게이트용 폴리실리콘막(25)을 차례로 증착한다. 여기서, 터널산화막(22), 질화막(23) 및 알루미늄산화막(24)은 게이트 산화막으로 사용된다.Then, the
다음으로, 플로팅게이트용 폴리실리콘막(25) 상에 포토레지스트 패턴(도시하지 않음)을 형성하고, 포토레지스트 패턴을 식각베리어로 플로팅게이트용 폴리실리콘막(25), 알루미늄산화막(24), 질화막(23) 및 터널산화막(22)을 차례로 식각하여 게이트 패턴(G)을 형성한다. 게이트 패터닝시 플라즈마 건식 식각으로 진행하며, 후속 공정으로 포토레지스트 패턴을 스트립한다.Next, a photoresist pattern (not shown) is formed on the floating
도 2b에 도시된 바와 같이, 게이트 패턴(G)을 형성한 후 측면이 노출된 알루미늄산화막(24)의 차지 트랩 사이트(Charge Trap Site)를 생성하지 못하게 무기 황화 케미컬 처리(Inorganic Sulfide Chemical Treatment)를 통하여 황으로 알루미늄산화막(24)의 양측벽에 측벽보호막(24a)을 형성하여 댕글링 본드(Dangling bond)를 패시베이션(Passivation) 시키므로서, 소자의 전기적 특성 저하를 방지할 수 있다.As shown in FIG. 2B, after forming the gate pattern G, an inorganic sulfide chemical treatment may be performed so as not to generate a charge trap site of the
측벽보호막(24a)은 습식 처리(Wet Treatment)를 실시하여 형성하며, 더 자세히는 무기 황화 케미컬 처리를 실시한다. 이 때 습식 케미컬은 (NH4)2Sx를 케미컬로 사용한다. 그리고, 습식 처리시 (NH4)2Sx-4%, 딥 타임은 적어도 10분 동안 진행한다.The sidewall
상술한 바와 같이, 플래쉬 메모리 소자의 게이트 패턴을 형성한 후 알루미늄산화막의 양측벽에 황화 케미컬 처리를 실시하여 측벽보호막을 형성하므로서, 차지 트랩 사이트 생성을 방지하여 후속 디바이스 제조시 수반되는 후속 열공정 적용시 디바이스의 신뢰성에도 문제를 끼칠 수 있다.As described above, after forming the gate pattern of the flash memory device, sulfide chemical treatment is performed on both side walls of the aluminum oxide film to form a sidewall protective film, thereby preventing charge trap sites from being generated, thereby applying subsequent thermal processes in subsequent device fabrication. It can also affect the reliability of the device.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 플래쉬 메모리 디바이스에 대한 수율 향상을 확보할 수 있는 효과가 있다.The present invention described above has the effect of ensuring a yield improvement for a flash memory device.
또한, 알루미늄산화막의 결함을 줄여 트랩 사이트를 줄임으로써 전하 소거 때에 알루미늄산화막에서의 전하 이동을 방지하므로 메모리셀의 특성 및 내구성을 높이는 효과가 있다.In addition, by reducing defects in the aluminum oxide film and reducing trap sites, charge transfer in the aluminum oxide film is prevented during charge erasing, thereby improving the characteristics and durability of the memory cell.
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| KR20060023489A (en) * | 2004-09-09 | 2006-03-14 | 삼성전자주식회사 | Method of forming gate pattern of semiconductor device |
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|---|---|---|---|---|
| KR20050064323A (en) * | 2003-12-23 | 2005-06-29 | 매그나칩 반도체 유한회사 | Method for forming gate of flash memory device |
| KR20050120297A (en) * | 2004-06-18 | 2005-12-22 | 매그나칩 반도체 유한회사 | Method for manufacturing merged eeprom and logic device |
| KR20060023489A (en) * | 2004-09-09 | 2006-03-14 | 삼성전자주식회사 | Method of forming gate pattern of semiconductor device |
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| Publication number | Publication date |
|---|---|
| KR20070097841A (en) | 2007-10-05 |
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