KR100850368B1 - Exposure system, semiconductor device and process for fabricating the same - Google Patents

Abstract

In order to link the defect inspection process before contact hole formation and the exposure process for contact hole formation, the position (physical coordinate) on the wafer of the defect detected in the defect inspection process before contact hole formation is stored, and in this part, the contact hole Exposure (dummy exposure) is performed on condition that this is not formed. According to this method, since a contact hole is not formed in a region where a defect exists, a defective cell is formed. However, short-circuit between word lines (control gates) and bit lines through the contact holes does not occur, and bit line redundancy has been conventionally used. It is possible to rescue only by carrying out.

Contact hole, dummy exposure, redundancy, word line, bit line

Description

Exposure system, semiconductor device and manufacturing method of semiconductor device {EXPOSURE SYSTEM, SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technology thereof, and more particularly, to a manufacturing technology of a nonvolatile semiconductor memory device having improved redundancy efficiency of a NOR type flash memory.

Flash memory, which is a nonvolatile semiconductor memory device, is a nonvolatile memory that includes both a RAM (Random Access Memory) feature that allows data to be rewritten, and a ROM (Read Only Memory) feature that retains data even after the power is turned off. It is a semiconductor memory device. Generally, the minimum storage unit in a memory device is called a cell, and one cell stores one bit. In SRAM or DRAM, a single cell is composed of a plurality of elements, whereas a single cell of a flash memory is composed of only one transistor, which is the minimum number of elements, so that the cost can be reduced. A plurality of single cells of such a flash memory are grouped together to form one sector (blockd), and a storage area is configured as a set of these sectors. Further, data erasing for this storage area is performed in sector units (or chip batches).

Flash memory is classified into NAND type and NOR type. NAND-type flash memory has 8- or 16-bit memory cells connected in series to one data line, and write-and-erase effects the Fowler-Nordheim tunnel effect using the front surface of the silicon substrate and the floating gate. I use it. On the other hand, in the NOR-type flash memory, individual memory cells are connected in parallel to one data line. Hot electrons are used for writing, and a Fowler-Nordheim tunnel phenomenon is used for erasing.

1 is a schematic cross-sectional view for explaining the shape of a connection between a NOR type flash memory cell and a bit line. One NOR flash memory cell 10 includes a semiconductor substrate 11, a floating gate 12 and a word line 13 formed in the insulating layer 17 provided thereon, and a contact portion formed in the insulating layer 17. (14) (consisting of a contact hole and a conductive member therein) and an insulating layer 17, and contacting the semiconductor substrate 11 (specifically, an impurity diffusion layer) via the contact portion 14. Has a bit line 15. In each cell 10 of the NOR type flash memory, the presence or absence of information can be identified by storing the electrons injected by the voltage application from the word line 13 in the floating gate 12.

In the manufacturing process of the cell having such a structure, the word line 13 and the contact portion 14 may be electrically shorted due to the presence of any defect 16, resulting in malfunction. However, even when bit line redundancy is performed when such a malfunction occurs, the word line 13 is still shorting the contact portion 14 connected to the redundant bit line 15. For this reason, when a sufficient voltage is not supplied to the word line 13 at the time of writing, reading, and erasing data, malfunction is not eliminated.

At this time, even if the word line redundancy is executed, only the erase operation is performed on the cell on the redundant word line 13 but connected to the non-redundant bit line 15, and the write operation is not performed. As a result, the threshold voltage of the cell becomes negative, resulting in an influence on the reading of another cell connected to the same bit line 15.

2 is a diagram for explaining a circuit configuration of a NOR type flash memory. As shown in this figure, if one memory cell 10 is connected between the word line 13 and the bit line 15, and any memory cell 10 connected to the bit line is conductive, the bit line The potential of (15) is lowered.

In FIG. 2, an electrical short circuit occurs between a contact hole having a cell 10-1 positioned at an intersection of a word line 13-1 and a bit line 15-1 and a word line 13-1. In this case, it is assumed that redundancy of the word line 13-1 and the bit line 15-1 has been executed to remedy this. Since the erase of the NOR type flash memory is performed in units of sectors (memory blocks), not only the cell 10-1 but also the cells connected to the redundant word line 13-1 and the bit line 15-1. At the same time, the erase operation is executed. On the other hand, since the write operation is performed by selecting the word line and the bit line, the cells connected to the redundant word line 13-1 and the bit line 15-1 cannot be selected and the write operation is not performed. Do not. Even if it is selectable, writing is impossible because the voltage cannot be sufficiently supplied to the word line.

The threshold voltage of a cell in which only erasing is performed and no writing is gradually made negative, and a current flows even when the gate voltage is 0V. In the NOR-type flash memory, the current of the cell is detected as the current flowing through the bit line, but the current of the cell connected to the non-redundant bit lines 15-0, 15-2, and 15-3 is the redundant word line. The current of the cell connected to (13-1) is affected. For this reason, it becomes difficult to accurately read the current of the selected cell.

In this way, malfunctions caused by electrical short-circuits between the word line 13 and the contact portion 14 caused by the defect cannot be redundant, and remedies are impossible.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and an object thereof is a manufacturing method of a nonvolatile semiconductor memory device which makes it possible to remedy a malfunction caused by a defect located between a word line and a contact hole only by bit line redundancy. To contribute to the improvement of the production yield.

In order to achieve the above object, the present invention provides an exposure system comprising: an inspection apparatus for detecting a defect on a surface of a semiconductor substrate, a controller for storing physical coordinates of the defect on the semiconductor substrate, and The exposure apparatus is controlled, and the exposure apparatus which does not form a contact hole in the said area | region by dummy exposure of the area | region corresponding to the physical coordinate of the said defect is provided. The dummy exposure is defocused condition exposure or empty exposure. The exposure apparatus is a scanner type electron beam exposure apparatus.

The present invention also provides a method of detecting a defect on a surface of a semiconductor substrate prior to forming a contact hole, storing physical coordinates on the semiconductor substrate of the defect detected in the first step, and predetermining a surface on the surface of the semiconductor substrate. And a step of exposing a contact hole in the region, and performing dummy exposure of the region corresponding to the physical coordinates stored in the storing step, thereby forming no contact hole in the region. . The dummy exposure in the exposing step is defocus condition exposure or empty exposure. In the exposing step, a contact hole is formed according to a NOR type memory cell arrangement. And further comprising replacing a bit line comprising said region with respect to said defect with a redundancy bit line.

The present invention also provides a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a bit line formed on the insulating layer, a contact portion formed in the insulating layer, and forming a contact between the bit line and the semiconductor substrate; And a semiconductor device having a floating gate and a word line formed in the insulating layer, wherein the contact portion is regularly arranged and includes a portion where no contact is formed during the regular arrangement. In this semiconductor device, the bit lines including the region related to the defect are replaced with redundancy bit lines.

According to the present invention, since a contact hole is not formed in a region where a defect exists, a defective cell is formed, but a short circuit between the word line (control gate) and the bit line through the contact hole does not occur, and the bit line has been conventionally used. Salvation can be achieved only by performing redundancy.

1 is a schematic cross-sectional view for explaining the shape of a connection between a NOR type flash memory cell and a bit line.

2 is a diagram for explaining a circuit configuration of a NOR type flash memory.

FIG. 3 is a block diagram for explaining a state in which a defect inspection apparatus for performing defect inspection before forming contact holes and a scanner type exposure apparatus for performing exposure for forming contact holes are connected.

4 is a flowchart for illustrating and explaining a part of a series of processes from a defect inspection process to an exposure process.

FIG. 5A is a first diagram for explaining the shape of components of a transistor formed by the process of the flowchart shown in FIG. 4, and FIG. 5B shows the components of a transistor formed by the process of the flowchart shown in FIG. FIG. 5C is a third diagram for explaining the components of a transistor formed by the process of the flowchart shown in FIG. 4, and FIG. 5D is a configuration of the transistor formed by the process of the flowchart shown in FIG. 4 is a diagram for explaining the elements.

FIG. 6A is a plan view from above for explaining a conventional method of avoiding a short circuit between the word line and the contact hole by not forming a contact hole, and FIG. 6B is a short circuit between the word line and the contact hole by not forming a contact hole. Top view from above for explaining the method of the present invention for avoiding the above.

The root cause of the above-mentioned malfunctions is that defects generated in the manufacturing process of the nonvolatile semiconductor memory device (for example, particles attached on a wafer (semiconductor substrate)) are normally contacted in subsequent processes. It is an obstacle to the formation of holes. In addition, an electrical short between the contact hole and the word line creates a situation in which redundancy is impossible. However, since such a defect can be detected by inspecting the defect prior to the contact hole forming process, shortening of the word line and the bit line through the contact hole does not occur as long as the contact hole is not formed in the portion where the defect exists. This can be accomplished by merely performing bit line redundancy conventionally used. In other words, by switching "defects such as particles" into the form of "defects without contact holes", it is possible to apply a conventional redundancy method to remedy a malfunction.

For this reason, in this invention, the defect inspection process before contact hole formation and the exposure process for contact hole formation are made to link. Specifically, the position (physical coordinate) on the wafer of the defect detected in the defect inspection step before forming the contact hole is stored, and exposure (dummy exposure) is performed under the condition that no contact hole is formed in the portion. In addition, dummy exposure here may be the same as "empty exposure" which does not perform exposure of the said part at all other than exposing under a defocus condition so that a contact hole may not be formed (for example, it does not irradiate an exposure beam). good. For convenience, in the following description, this dummy exposure will be described as exposure under defocus conditions, but the present invention is not limited to this form of dummy exposure. As described above, no contact hole is formed at the position (physical coordinate) on the wafer of the defect detected in the defect inspection process before forming the contact hole.

The position of such a defect is specified by the pattern recognition which compares the image of adjacent circuit patterns, and can measure not only a physical coordinate but also the spatial area (size) of a defect. In addition, the exposure apparatus used by this invention is of the "scanner type" (for example, EB exposure apparatus) which can set exposure conditions for each contact hole, and when the defect exists in a contact hole formation area, the said area | region The dummy exposure is performed so that the exposure condition to the target is consciously defocused so that the actual exposure is not performed.

EMBODIMENT OF THE INVENTION Hereinafter, the best form for implementing this invention with reference to drawings is demonstrated.

Fig. 3 is a block diagram of an exposure system for explaining the form of a link between a defect inspection apparatus for performing defect inspection before contact hole formation and a scanner type exposure apparatus for exposure exposure for contact hole formation. In this figure, 310 is a surface inspection apparatus, 320 is a scanner type exposure apparatus, and both are provided with stages 311 and 321 for mounting the wafer 301. In addition, the physical coordinate information of the defect (for example, particle) 302 on the wafer 301 detected in the defect inspection before the contact hole formation by the surface inspection apparatus 310 may be a controller (for example, personal). Computer 330). In addition, the surface inspection described above is performed by a general method. For example, the laser beam is obliquely incident on the surface of the wafer 301, and the scattered light is monitored by the detection unit 312, and the pattern of the image based on this signal is monitored. It is implemented by analyzing. Moreover, the magnitude | size of a defect can also be known by analyzing scattered light intensity at the time of the image analysis.

After the surface inspection, the wafer is exposed for forming contact holes. However, as described above, when the contact hole is formed at the coordinate position on the wafer 301 where the defect 302 is present, the defect is only caused by bit line redundancy. You will not be able to rescue. Accordingly, the controller 330 transmits a signal for defocusing the exposure condition to the exposure unit 322 when the exposure apparatus 320 performs exposure of a region on the wafer 301 corresponding to the defect 302. do. As described above, in the case of "empty exposure" rather than defocus exposure, a signal for not exposing to the area on the wafer 301 corresponding to the defect 302 is transmitted to the exposure unit 322.

4 is a flowchart for illustrating and explaining a part of a series of processes from the defect inspection process to the exposure process. 5A to 5D are diagrams for explaining the components of a transistor formed by the process of the flowchart shown in FIG.

After completion of the second gate etching step (step S201), the defect inspection apparatus checks the presence or absence of a defect on the wafer (step S202). At this time, when a defect is detected, physical coordinate information corresponding to the presence position of each defect is transmitted to the controller and stored (step S203). In addition, a deposition for forming the sidewall is executed (step S204), and after this step, a defect inspection is performed as described above (step S205), and the controller stores the result (step S206).

For example, as shown in FIG. 5A, the floating gate 12 and the control gate 13a are provided on the surface of the substrate 11 on which the source 11a and the drain 11b are formed, and on the side of these gates. It is assumed that sidewalls 17 are formed. Originally, contact holes are formed between the sidewalls 17 in the drain 11b region. However, in the case where the defect 16 is present in the region, it is necessary to prevent contact hole formation in this region. Therefore, the information of the physical coordinates of the defect 16 detected in step S205 is transmitted to and stored in the controller (step S206), and used as a position to be defocused by focus adjustment in the subsequent exposure process. In addition, as already demonstrated, when it sets to "empty exposure" instead of defocus exposure, the information of the physical coordinate of the defect 16 is used as a position which does not perform exposure.

After the mask process (step S207) and ion implantation (step S208) for introducing impurities into the source 11a and the drain 11b, deposition for embedding the gate is executed (step S209), and on this buried layer A mask of photoresist for forming contact holes is formed (step S210).

5B shows a photoresist mask 18 exposed so that contact holes are not formed in portions where defects 16 are present. The photoresist mask 18 is formed by being exposed so that only the region corresponding to the contact hole formation position of the photoresist uniformly coated on the buried layer 19 of the gate is opened. The region indicated by 18a in FIG. 5B originally corresponds to the region in which the opening for forming the contact hole is to be provided, but the defect 16 is present at this position. For this reason, the controller transmits physical coordinate information of the defect to the exposure apparatus so as not to form an opening at the position (step S211), and the exposure apparatus defocuses the exposure condition for the defect presence region based on this information. The dummy exposure is performed so that contact holes are not formed.

Using such a photoresist mask 18, etching for forming a contact hole is performed (steps S212 and 5C), and contacts are formed in this region to form bit lines 15 (steps S213 and 5D).

6A and 6B are plan views seen from above for explaining the avoidance of a short circuit between the word line and the contact hole by not forming a contact hole. In the conventional method of forming the contact portion 14 with or without the presence of the defect 16 (FIG. 6A), the contact portion 14 formed in the region where the defect 16 is present has a word line 13 and a bit. Since the line 15 is shorted, defects cannot be repaired only by bit line redundancy. On the other hand, according to the method (FIG. 6B) of the present invention, since the contact portion 14 (more specifically, the contact hole) is not formed in the region where the defect 16 exists, the contact portion becomes a defective cell. The short circuit between the word line (control gate 13a) and bit line 15 via 14 does not occur, and it is possible to remedy only by performing bit line redundancy conventionally used. In other words, by switching "defects such as particles" into the form of "defects without contact holes", it is possible to apply a conventional redundancy method to remedy a malfunction.

According to the configuration of the flash memory shown in FIG. 6B together with the configuration shown in FIG. 1, the flash memory includes a semiconductor substrate 11, an insulating layer 17 formed on the semiconductor substrate 11, and an insulating layer 17. A bit line 15 formed thereon, a contact portion 14 formed in the insulating layer 17 to form a contact between the bit line 15 and the semiconductor substrate 11, and a floating gate formed in the insulating layer 17. (12) and a word line 13, the contact portion 14 is arranged regularly, and includes a portion (parts corresponding to reference numeral 16) in which the contact portion is not formed irregularly during this regular arrangement. to be. In addition, redundancy processing is performed on the bit lines in which no contact portion is formed. According to the present invention, since the above problem can be solved only by bit line redundancy, it is possible to provide a semiconductor device which efficiently solves an operation defect.

In addition, although defect inspection is supposed to be performed twice after a 2nd gate etching process and after a sidewall deposition process here, it goes without saying that it is performed by a suitable number of times according to the process design of the device to manufacture.

According to the present invention, it is possible to provide a manufacturing method of a nonvolatile semiconductor memory device having improved redundancy efficiency and an exposure system that enables this.

Claims (9)

An inspection apparatus for detecting a defect on the surface of the semiconductor substrate; A control unit that stores physical coordinates on the semiconductor substrate of the defects; And And an exposure apparatus for exposing the semiconductor substrate such that an exposure condition is controlled by the control unit so that a contact hole is not formed in a region corresponding to the physical coordinates of the defect. The method of claim 1, And the exposure apparatus does not expose the region under the defocusing condition or irradiate the exposure beam to the region. The method according to claim 1 or 2, And the exposure apparatus is a scanner type electron beam exposure apparatus. Detecting defects on the surface of the semiconductor substrate prior to forming the contact holes; Storing physical coordinates on the semiconductor substrate of the defect detected in the detecting step; Performing exposure for forming contact holes in a predetermined region on the surface of the semiconductor substrate, and exposing the semiconductor substrate so as not to form contact holes in the region corresponding to the physical coordinates stored in the storing step. The manufacturing method of a semiconductor device. The method of claim 4, wherein The exposing step does not expose the region under the defocusing condition or irradiate a beam for exposure to the region. The method according to claim 4 or 5, And the exposing step forms a contact hole according to a NOR type memory cell arrangement. The method according to claim 4 or 5, And replacing the bit line including the defective area with a redundancy bit line. A semiconductor substrate; An insulating layer formed on the semiconductor substrate; A bit line formed on the insulating layer; Contact holes formed in the insulating layer between the bit line and the semiconductor substrate; And It includes a floating gate and a word line formed in the insulating layer, Wherein the contact holes are regularly arranged, and contact holes are not formed in a region corresponding to the physical coordinates on the semiconductor substrate of defects detected on the surface of the semiconductor substrate. The method of claim 8, And a bit line including an area where the contact hole is not formed is replaced with a redundancy bit line.

Images