KR100843741B1 - Method for preparing a silicon on sapphire thin film - Google Patents

Abstract

A method for manufacturing a sapphire thin film having a silicon-stacked structure is provided to obtain high quality by suppressing generation of crystalline defects due to lattice mismatch and a thermal expansion coefficient difference. Silicon ions having ion implantation energy of 1-200keV and ion dose of 1x10^14-5x10^17cm^-2 are implanted onto a sapphire substrate(1). A thermal process is performed to form nano-silicon seeds(3) by crystallizing the implanted silicon ions. A crystalline silicon layer is formed on the nano-silicon seeds during 1-5 minutes by controlling a flow rate, in order to form a flow rate of H2:SiH4 corresponding to 35-45:1 at 750-850 degrees centigrade and pressure of 1-2 Torr. A single crystalline silicon layer(4) is formed on the crystalline silicon layer during 30-90 minutes by controlling the flow rate, in order to form the flow rate of H2:SiH4 corresponding to 10-20:1 at 850-950 degrees centigrade and pressure of 2-3 Torr.

Description

Method for preparing a silicon laminated sapphire thin film {Method for preparing a silicon on sapphire thin film}

1 is a process chart according to a method for manufacturing a silicon laminated sapphire thin film according to the prior art.

Figure 2 is a process chart according to the manufacturing method of the silicon laminated sapphire thin film of the present invention.

Figure 3 is a schematic diagram of the first crystallization silicon layer is formed on the top of the nano silicon seeds by the method for producing a silicon laminated sapphire thin film of the present invention.

4 is an electron transmission microscope (TEM) photograph of a sapphire substrate on which nano silicon seeds are formed according to the present invention.

5 is an electron scanning micrograph (SEM) and an electron transmission micrograph of the crystallized silicon layer formed in the intermediate step of Example 1 of the present invention.

6 is an electron transmission micrograph of the silicon-laminated sapphire thin film prepared by Example 1 and Comparative Example 1 of the present invention.

7 is XRD data for the silicon-laminated sapphire thin film prepared by Example 1 and Comparative Example 1 of the present invention.

8 is Raman data for the silicon-laminated sapphire thin film prepared by Example 1 and Comparative Example 1 of the present invention.

<Description of the symbols for the main parts of the drawings>

1 ... sapphire substrate 2 ... ion implantation layer

3 ... nano silicon seed 4 ... monocrystalline silicon layer

4 '... silicon layer 5 ... crystallized silicon layer

6 ... thining layer

The present invention relates to a method for manufacturing a silicon laminated sapphire thin film, and more particularly, to a method for manufacturing a silicon laminated sapphire thin film using nanosilicon seeds.

Silicon on insulator (SOI) is characterized by a thin insulating layer between the substrate surface forming the circuit and the lower layer, thereby reducing parasitic capacitance and improving device performance. One of the technologies that is gaining in importance in next-generation integrated circuits because of its high operation speed and low supply voltage at the same speed, silicon on sapphire (SOS) is an SOI technology. It is one of the well developed technologies.

The conventional SOS structure forms a single crystal silicon layer on the sapphire (Sapphire A1 ₂ O ₃ ) substrate by epitaxy method. The conventional SOS structure thus manufactured has a lattice parameter between sapphire and silicon. ), Half of the thickness of the single crystal silicon layer disappears from the interface between the sapphire substrate and the single crystal silicon layer thereon, resulting in dislocations, stacking faults, and twinning in the thin film. It contains significant amounts of crystal defects such as microtwins. This defect has a problem of reducing the transmitter mobility of the device and increasing the leakage current.

Therefore, in order to solve this problem, various processes such as recrystallization, double implantation, and double epitaxy are known, and a representative process is a solid phase epitaxy process. .

The SPE process comprises the steps of (i) growing a silicon layer on a sapphire (1-102) substrate by CVD, (ii) implanting silicon ions into the silicon layer, (iii) implanted silicon ions And recrystallizing the silicon layer through heat treatment, and (iv) removing the uppermost thinning layer to thin the film. FIG. 1 is a process diagram according to a method for manufacturing a SOS thin film according to the prior art. In the step (a), a sapphire (1-102) substrate 1 is used, and in step (b), the silicon layer 4 'is CVD. After recrystallization through silicon ion implantation and heat treatment in step (c), the thinning layer 6 is formed, and in step d), the thinning layer 6 is etched and removed, Steps 3) and (d) may be added to repeat the steps. In the step (e), the SOS thin film in which the silicon layer 4 'is formed on the sapphire substrate 1 can be obtained.

Meanwhile, the regrowth method includes further growing an additional Si layer after performing the SPE process, and the double implantation method further includes injecting secondary Si ions and a heat treatment process after performing the SPE process. do.

US Patent No. 4,177,084 includes the steps of epitaxially depositing a single crystal silicon layer on a sapphire substrate; Implanting ions at an interface between silicon and sapphire in the silicon layer in a direction parallel to a main crystal axis of the silicon layer to form an amorphous silicon region; And converting the amorphous silicon into single crystal silicon by heat-treating the substrate. However, since the silicon layer has already been formed, ion implantation is performed as a post-treatment process. There is a problem that the flatness of is poor, and after the heat treatment, impurities and the like are collected in the outermost layer (thining layer), and thus an additional process of removing the outermost layer is required.

Meanwhile, Korean Patent Publication No. 88-2385 discloses a silicon layer on sapphire by a known method in the SOS structure of a semiconductor device, and then forms an SiO ₂ oxide layer on the silicon layer. After implanting nitrogen ions inside and heat-treating to form a silicon nitride layer at the site where the nitrogen ions exist, remove the SiO ₂ oxide layer, and then grow a single thickness Si single crystal layer on the silicon layer. A method for improving the SOS structure of a semiconductor device, which comprises forming a silicon layer, has been disclosed, but a manufacturing process is very complicated.

In addition, the Republic of Korea Patent Publication No. 407719, forming an epitaxial silicon layer on the sapphire substrate to form an SOS structure; Implanting ions on the epitaxial silicon layer; Annealing the sapphire silicon structure; Oxidizing the epitaxial silicon layer to form a silicon dioxide layer from a portion of the epitaxial silicon layer to leave the thin film epitaxial silicon layer; A method of manufacturing a liquid crystal display array and a control circuit is disclosed that includes removing a silicon dioxide layer to expose a thin film epitaxial silicon layer, but, as already mentioned, removing the silicon dioxide layer of the outermost layer is further described. There is a problem that the number of processes increases and the quality of the final thin film is not so good because it is included.

Although the prior art as described above attempts to obtain a high quality SOS thin film through a complex process of several steps, the effect of removing crystal defects caused by lattice mismatch and thermal expansion difference between Si and sapphire in the Si growth step through the post-treatment process. In addition, the Si thin film grown due to the surface energy due to lattice mismatch has a problem that the process efficiency is also lowered because the surface of the thin film is roughened and a mechanical polishing process is required during device fabrication.

Therefore, the technical problem to be achieved by the present invention is to provide a method for producing a silicon laminated sapphire thin film on a high quality through a simple process.

The present invention to achieve the above technical problem,

(a) implanting silicon ions into a sapphire substrate so as to be positioned near the surface of the substrate;

(b) performing a heat treatment process to crystallize the implanted silicon ions to form nano silicon seeds;

(c) forming a crystalline silicon layer on the nano silicon seeds; And

(d) forming a single crystal silicon layer on top of the crystallized silicon layer.

According to an embodiment of the present invention, after step (d), the method may further include repeating steps (c) and (d).

According to another embodiment of the present invention, the implantation of the silicon ions in the step (a) is the implantation energy of 1 ~ 200keV and 1X10 ¹⁴ It can be carried out with an ion dose of ˜5 × 10 ¹⁷ cm ⁻² .

In addition, the heat treatment temperature of step (b) may be 500 ~ 1200 ℃, the heat treatment time may be 5 minutes to 3 hours.

According to another embodiment of the present invention, the silicon deposition of the steps (c) and (d) is preferably performed by the RTCVD method.

In addition, the hydrogen baking process may be further included before the step (c).

According to a preferred embodiment of the present invention, step (c) adjusts the flow rate such that the flow rate ratio of H ₂ and SiH ₄ is 35 to 45: 1 at a temperature of 750 to 850 ° C. and a pressure of 1 to 2 torr. 1 to 5 minutes, and step (d) adjusts the flow rate so that the flow rate ratio of H ₂ and SiH ₄ is 10 to 20: 1 at a temperature of 850 to 950 ° C. and a pressure of 2 to 3 torr. And 30 to 90 minutes.

Hereinafter, the present invention will be described in more detail.

According to an aspect of the present invention, there is provided a method of fabricating a silicon-laminated sapphire thin film, comprising: (a) implanting silicon ions into a sapphire substrate so as to be positioned near a surface of the substrate; (b) performing a heat treatment process to crystallize the implanted silicon ions to form nano silicon seeds; (c) forming a crystalline silicon layer on the nano silicon seeds; And (d) forming a single crystal silicon layer on top of the crystallized silicon layer, wherein after the single crystal silicon layer is grown, ion implantation is not performed as a post-treatment process, but before the single crystal silicon layer is grown. As a pretreatment process, silicon ions are implanted into the surface of the sapphire substrate, silicon seeds are formed through heat treatment, and then, as a seed, a high quality SOS thin film can be manufactured. Therefore, there is an advantage in that the surface state and silicon crystallinity of the single crystal silicon layer are excellent.

FIG. 2 is a process diagram according to a method for manufacturing a SOS thin film according to the present invention, and in the step (a), silicon ions are sapphire substrate 1 as indicated by an arrow on the sapphire (1-102) substrate 1 of γ-plane. It is implanted to be located near the surface to generate the ion implantation layer (2) dl, in step (b) to form a nano-silicon seed (nano-Si seed) (3) by heat treatment to crystallize the implanted silicon ions In step (c), the step of growing the single crystal silicon layer 4 by RTCVD to form an SOS thin film is shown.

Meanwhile, FIG. 3 is a schematic diagram in which a crystallization silicon layer 5 is primarily formed on the nano silicon seed 3, in which silicon is further formed on the crystallization silicon layer 5. As it is deposited, the single crystal silicon layer 4 of FIG. 2 is formed.

According to the manufacturing method of the present invention, after the step (d), it may further include the step (c) and (d) repeating, whereby the surface roughness of the single crystal silicon layer (4) A reduced effect can be obtained.

On the other hand, the implantation of the silicon ions in step (a) may be performed with an implantation energy of 1 to 200 keV and an ion dose of 1X10 ¹⁴ to 5X10 ¹⁷ cm ^-2 . When the implantation energy is less than 1 keV, ion implantation is insufficient. When exceeding 200 keV, excessive physical damage to the surface of the sapphire substrate and crystalline silicon may occur inside the sapphire substrate. It is preferable that the said injection energy is 10-100 keV, and it is more preferable that it is 13-50 keV. On the other hand, the ion dose amount is 1X10 ¹⁴ If it is less than ² cm ^{- 2} , the ion implantation amount is insufficient, so that it is difficult to form a nano silicon seed 3 having an appropriate density in a later process, and if it exceeds 5X10 ¹⁷ cm ^-2 , physical damage may occur on the surface of the sapphire substrate 1. There is. The ion dose amount is 5X10 ¹⁴ - it may be a 1X10 ¹⁷ cm ^-2, 1X10 ¹⁵ It is more preferable that it is-5X10 ¹⁶ cm <^-2> .

In addition, the heat treatment temperature of the step (b) may be 500 ~ 1200 ℃, when the heat treatment temperature is less than 500 ℃ nano silicon seed 3 may not be formed properly, when exceeding 1200 ℃ excessive heat Consumption is undesirable in terms of process efficiency.

On the other hand, the heat treatment time may be 5 minutes to 3 hours, when less than 5 minutes there is a fear that the nano silicon seed (3) is not formed properly, when it exceeds 3 hours is not preferable in terms of process efficiency.

According to another embodiment of the present invention, the silicon deposition of the steps (c) and (d) is preferably carried out by the Rapid Thermal Chemical Vapor Deposition (RTCVD) method, which heats the reactor with the light generated from the lamp. As a CVD method for performing vapor deposition, the reaction energy is lowered because it serves to excite atoms or molecules of the reaction gas in addition to raising the internal temperature through light.

Prior to the step (c), it is preferable to perform a hydrogen baking process, which may include water vapor, SiO _{2 and} other impurities on the surface of the ion implanted layer 2 into which the silicon ions are implanted. This is to remove these impurities because the deposition of silicon is inhibited. This process refers to a process of removing impurities adhering to the surface of the sapphire substrate while flowing an appropriate flow rate of H ₂ gas for 1 minute to several minutes at a temperature of about 900 ° C. and a pressure of about 1 torr.

According to a preferred embodiment of the present invention, step (c) adjusts the flow rate such that the flow rate ratio of H ₂ and SiH ₄ is 35 to 45: 1 at a temperature of 750 to 850 ° C. and a pressure of 1 to 2 torr. It may be performed for 1 to 5 minutes, by the low-temperature growth according to the present process, the crystallized silicon layer 5 is formed by using the nano silicon seed (3) as a seed. When the temperature is less than 750 ℃ single crystal silicon is not grown, there is a problem that polycrystalline or amorphous silicon is grown, when the temperature exceeds 850 ℃ excessive silicon growth excessive crystallized silicon volume is difficult to grow high quality single crystal silicon layer There is. On the other hand, when the reaction pressure is less than 1 torr, there is a problem that the growth rate of silicon is low, and when it exceeds 2 torr, there is a problem that optimum single crystal silicon layer growth is difficult. The flow rate of the gas is preferably such that the flow rate ratio of H ₂ and SiH ₄ is 35 to 45: 1. When the flow rate ratio is less than 35: 1, there is a problem of inhibiting optimum single crystal growth due to excessive reaction rate. If it exceeds 1, the growth rate may be too small. In addition, the reaction time is preferably 1 to 5 minutes, when less than 1 minute there is a fear that the silicon crystals are not produced, when more than 5 minutes there is a risk that the silicon film is generated without the crystallized silicon.

On the other hand, step (d) is carried out for 30 to 90 minutes by adjusting the flow rate so that the flow rate ratio of H ₂ and SiH ₄ is 10 to 20: 1 at a temperature of 850 ~ 950 ℃ and a pressure of 2 to 3 torr Forming a single crystal epitaxy layer on top of the crystallized silicon layer (5), when the temperature is less than 850 ℃ single crystal silicon is not grown and polycrystalline or non-wetting There is a concern that silicon may be grown, and when it exceeds 950 ° C., there is a fear that it is difficult to grow a high quality single crystal silicon layer with excessive silicon growth rate. On the other hand, when the reaction pressure is less than 2 torr, the growth rate of the silicon layer is too low, and when it exceeds 3 torr, there is a fear that optimal single crystal silicon layer growth is difficult. The flow rate of the gas is preferably such that the flow rate ratio of H ₂ and SiH ₄ is 10 to 20: 1. When the flow rate ratio is less than 10: 1, there is a possibility that optimum single crystal growth is inhibited due to excessive reaction rate. If it exceeds 1, there is a problem that the growth rate is too small. In addition, the reaction time is preferably 30 to 90 minutes, when less than 30 minutes, there is a concern that the thin film of the single crystal silicon layer from the crystalline silicon may be difficult, and when it exceeds 90 minutes, the thickness of the single crystal silicon layer may be too thick.

Hereinafter, the present invention will be described in more detail with reference to preferred examples, but the present invention is not limited thereto.

Example 1

The ion implantation was performed such that the silicon ions were positioned near the surface of the sapphire (1-102) substrate on the γ-plane, and the implantation energy of the silicon ions was fixed at 30 keV and the dose was 1 × ^{10 16} cm ⁻² . Next, nano silicon seeds were formed by performing heat treatment at 1000 ° C. for 1 hour to crystallize the implanted silicon ions, and FIG. 4 shows an electron transmission microscope (TEM) image of the sapphire substrate. Referring to the figure, it can be seen that the ion implantation layer 2 is identifiable on the sapphire substrate 1, and that the nano silicon seed 3 is formed on the ellipse portion formed by the dotted line in the ion implantation layer 2. Can be. Next, after the substrate treated above was charged into the reactor, the vacuum in the reactor of RTCVD maintained an initial basic vacuum of about 10 ⁻⁶ torr, followed by 1 minute at a temperature of 900 ° C. and a pressure of 1 torr. While flowing a hydrogen (H ₂ ) gas at a rate of 80 sccm, the H ₂ baking process for completely removing impurities adhering to the surface of the ion implantation layer was performed. Then, in order to form the crystallized silicon layer in one step growth, the reactor temperature was adjusted to 800 ° C., and SiH ₄ having a purity of 99.9999% for 2 minutes was introduced at ₂ sccm and H ₂ was introduced at 80 sccm under a pressure of 1 torr. After the inflow of 82 sccm (H ₂ / SiH ₄ = 40), a layer of about 50 nm thick crystalline silicon was grown while flowing the gases into the reactor. Finally, SiH ₄ and H ₂ were flowed at ₂ sccm and 30 sccm (H ₂ / SiH ₄ = 15), respectively, at a temperature of about 900 ° C. and a pressure of about 3 torr for 60 minutes, with about 400-800 nm thick single crystal silicon. A silicon laminated sapphire thin film was prepared by growing the layer.

Comparative Example 1

A silicon layer having a thickness of 3000 mW was deposited on the sapphire substrate by known epitaxy growth, and then silicon ions were implanted at an ion implantation energy of about 180ekV and an ion dose of 10 ¹⁶ / cm ² . At this time, the temperature of the substrate was maintained at 100 ° C. or less, thereby forming an amorphous silicon layer having a thickness of about 2000 μs from the interface between the sapphire and the silicon layer. Next, the substrate is charged to a reactor, heat treated at a reaction temperature of 600 ° C. for about 60 minutes under a nitrogen atmosphere, and then heat treated at 900 ° C. for about 15 minutes to cause recrystallization from the top single crystal silicon layer. A laminated sapphire thin film was prepared.

Test Example 1

Identification of Crystallized Silicon Layer

In order to confirm the crystallized silicon layer formed in the intermediate step of Example 1, an electron micrograph (SEM) and an electron transmission micrograph (TEM) were taken and the results are shown in FIG. 5. Referring to FIG. 5, it can be seen that a crystalline silicon layer is formed on the sapphire substrate.

Test Example 2

SOS  Electron Transmission Microscopy for Thin Films

Electron transmission micrographs were taken of the silicon laminate sapphire thin films prepared by Example 1 and Comparative Example 1, and the results are shown in FIG. 6. Referring to this drawing, in the case of the thin film according to Comparative Example 1, very many defects were found at the interface between Al ₂ O ₃ and Si, but in the case of the thin film manufactured according to Example 1 of the present invention, Al ₂ O ₃ It can be seen that the state of the interface between and Si is very good.

Test Example 3

XRD  Experiment

The XRD data of the silicon laminated sapphire thin films prepared by Example 1 and Comparative Example 1 were measured using an X-ray spectrometer (DCRC) and the results are shown in FIG. 7. Referring to this drawing, the DCRC half-width (FWHM) of the thin film manufactured by Comparative Example 1 is 1205 sec ^−1, and the DCRC half-width of the thin film manufactured by the method of the present invention is 700 sec ⁻¹ . It can be confirmed that the crystallinity of the excellent crystallinity of the single crystal silicon layer of the silicon laminated sapphire thin film prepared according to the present invention is excellent.

Test Example 4

Raman  Experiment

The Raman data of the silicon-laminated sapphire thin films prepared by Example 1 and Comparative Example 1 were measured and compared with bulk silicon, and the results are shown in FIG. 8. Raman data is a data that can measure the crystallinity and strain of the material. Basically, unstressed silicon has a peak at 521 cm ^-1 and knows how much stress is affected by the change of position of the peak. Referring to FIG. 8, the center of the peak is indicated by red diagonal lines, and Example 1 is located closer to bulk silicon than Comparative Example 1, which is a lattice mismatch in the silicon-laminated sapphire thin film manufactured by Example 1 It can be seen that the stresses that can occur are alleviated. In addition, since the size of the peak half-width (FWHM) indicates the crystallinity, the smaller the half-width value is, the better the crystallinity is, so that the crystallinity of the thin film according to the present invention is superior to that of Comparative Example 1.

As described above, according to the present invention, a single crystal silicon layer is formed on the substrate on which the nano silicon seeds are formed, and since the physical properties of the nano silicon seeds are similar to those of the single crystal silicon layer, the lattice mismatch and the coefficient of thermal expansion Since the generation of crystal defects due to the difference can be suppressed, there is an advantage that a high quality silicon-laminated sapphire thin film can be obtained by a simple process.

Claims (9)

(a) implanting silicon ions into the sapphire substrate at an implantation energy of 1 to 200 keV and an ion dose of ¹ × ^{10 14} to 5X10 ¹⁷ cm ⁻² ; (b) performing a heat treatment process to crystallize the implanted silicon ions to form nano silicon seeds; (c) at a temperature of 750-850 ° C. and a pressure of 1-2 torr, the flow rate was adjusted such that the flow rate ratio of H ₂ and SiH ₄ was 35-45: 1 and crystallized on the nano silicon seed for 1-5 minutes. Forming a silicon layer; And (d) At a temperature of 850 to 950 ° C. and a pressure of 2 to 3 torr, the flow rate is adjusted so that the flow rate ratio of H ₂ and SiH ₄ is 10 to 20: 1, and the upper part of the crystallized silicon layer is A method of manufacturing a silicon laminated sapphire thin film comprising the step of forming a single crystal silicon layer. The method of claim 1, further comprising repeating steps (c) and (d) after the step (d). delete The method of claim 1, wherein the temperature of the heat treatment process of step (b) is 500 ~ 1200 ℃. The method of claim 1 or 4, wherein the heat treatment is performed for 5 minutes to 3 hours. The method of claim 1, wherein the forming of the silicon layer of steps (c) and (d) is performed by RTCVD. The method of claim 1, further comprising a hydrogen baking process before step (c). delete delete

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