KR100835148B1 - 디지털 신호처리기 - Google Patents

디지털 신호처리기 Download PDF

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Publication number
KR100835148B1
KR100835148B1 KR1020067005980A KR20067005980A KR100835148B1 KR 100835148 B1 KR100835148 B1 KR 100835148B1 KR 1020067005980 A KR1020067005980 A KR 1020067005980A KR 20067005980 A KR20067005980 A KR 20067005980A KR 100835148 B1 KR100835148 B1 KR 100835148B1
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KR
South Korea
Prior art keywords
instruction
data
memory
bit
command
Prior art date
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Expired - Lifetime
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KR1020067005980A
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English (en)
Korean (ko)
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KR20060040749A (ko
Inventor
길버트 씨 시
퀴즈헨 조우
산자이 케이 자
인엽 강
지안 린
퀘이드 모티왈라
디푸 존
리 장
하이타오 장
웨이싱 리
찰스 이 사카마키
프라샨트 에이 칸타크
Original Assignee
퀄컴 인코포레이티드
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Priority claimed from US09/044,088 external-priority patent/US6496920B1/en
Priority claimed from US09/044,086 external-priority patent/US6425070B1/en
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20060040749A publication Critical patent/KR20060040749A/ko
Application granted granted Critical
Publication of KR100835148B1 publication Critical patent/KR100835148B1/ko
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Memory System (AREA)
KR1020067005980A 1998-03-18 1999-03-04 디지털 신호처리기 Expired - Lifetime KR100835148B1 (ko)

Applications Claiming Priority (13)

Application Number Priority Date Filing Date Title
US4408998A 1998-03-18 1998-03-18
US4410498A 1998-03-18 1998-03-18
US4410898A 1998-03-18 1998-03-18
US4408798A 1998-03-18 1998-03-18
US09/044,088 1998-03-18
US09/044,087 1998-03-18
US09/044,088 US6496920B1 (en) 1998-03-18 1998-03-18 Digital signal processor having multiple access registers
US09/044,104 1998-03-18
US09/044,086 US6425070B1 (en) 1998-03-18 1998-03-18 Variable length instruction decoder
US09/044,089 1998-03-18
US09/044,108 1998-03-18
US09/044,086 1998-03-18
KR1020007010577A KR100940465B1 (ko) 1998-03-18 1999-03-04 디지털 신호처리기

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020007010577A Division KR100940465B1 (ko) 1998-03-18 1999-03-04 디지털 신호처리기

Publications (2)

Publication Number Publication Date
KR20060040749A KR20060040749A (ko) 2006-05-10
KR100835148B1 true KR100835148B1 (ko) 2008-06-04

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KR1020067005980A Expired - Lifetime KR100835148B1 (ko) 1998-03-18 1999-03-04 디지털 신호처리기
KR1020067005979A Expired - Lifetime KR100896674B1 (ko) 1998-03-18 1999-03-04 디지털 신호처리기
KR1020007010577A Expired - Fee Related KR100940465B1 (ko) 1998-03-18 1999-03-04 디지털 신호처리기

Family Applications After (2)

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KR1020067005979A Expired - Lifetime KR100896674B1 (ko) 1998-03-18 1999-03-04 디지털 신호처리기
KR1020007010577A Expired - Fee Related KR100940465B1 (ko) 1998-03-18 1999-03-04 디지털 신호처리기

Country Status (11)

Country Link
EP (2) EP1457876B1 (enExample)
JP (4) JP2002507789A (enExample)
KR (3) KR100835148B1 (enExample)
CN (2) CN1279435C (enExample)
AR (5) AR026078A2 (enExample)
AT (1) ATE297567T1 (enExample)
AU (1) AU2986099A (enExample)
CA (1) CA2324219C (enExample)
DE (1) DE69925720T2 (enExample)
DK (1) DK1066559T3 (enExample)
WO (1) WO1999047999A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DK1066559T3 (da) * 1998-03-18 2005-10-03 Qualcomm Inc Digital signalprocessor
JP4100300B2 (ja) * 2003-09-02 2008-06-11 セイコーエプソン株式会社 信号出力調整回路及び表示ドライバ
JP4661169B2 (ja) * 2003-11-14 2011-03-30 ヤマハ株式会社 ディジタルシグナルプロセッサ
JP4300151B2 (ja) * 2004-04-19 2009-07-22 Ｏｋｉセミコンダクタ株式会社 演算処理装置
US7246218B2 (en) * 2004-11-01 2007-07-17 Via Technologies, Inc. Systems for increasing register addressing space in instruction-width limited processors
US7337272B2 (en) * 2006-05-01 2008-02-26 Qualcomm Incorporated Method and apparatus for caching variable length instructions
US11768689B2 (en) 2013-08-08 2023-09-26 Movidius Limited Apparatus, systems, and methods for low power computational imaging
US10001993B2 (en) 2013-08-08 2018-06-19 Linear Algebra Technologies Limited Variable-length instruction buffer management
FR3021427B1 (fr) * 2014-05-22 2016-06-24 Kalray Structure de paquet d'instructions de type vliw et processeur adapte pour traiter un tel paquet d'instructions
EP3982234A3 (en) * 2014-07-30 2022-05-11 Movidius Ltd. Low power computational imaging
WO2016016726A2 (en) * 2014-07-30 2016-02-04 Linear Algebra Technologies Limited Vector processor
CN109496306B (zh) * 2016-07-13 2023-08-29 莫鲁米有限公司 多功能运算装置及快速傅里叶变换运算装置
JP7384374B2 (ja) * 2019-02-27 2023-11-21 株式会社ウーノラボ 中央演算処理装置
US11204768B2 (en) 2019-11-06 2021-12-21 Onnivation Llc Instruction length based parallel instruction demarcator
EP4080354A1 (en) * 2021-04-23 2022-10-26 Nxp B.V. Processor and instruction set

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4099229A (en) * 1977-02-14 1978-07-04 The United States Of America As Represented By The Secretary Of The Navy Variable architecture digital computer
US5293611A (en) * 1988-09-20 1994-03-08 Hitachi, Ltd. Digital signal processor utilizing a multiply-and-add function for digital filter realization
US5710914A (en) * 1995-12-29 1998-01-20 Atmel Corporation Digital signal processing method and system implementing pipelined read and write operations

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2791086B2 (ja) * 1989-03-15 1998-08-27 富士通株式会社 命令プリフェッチ装置
EP0436341B1 (en) * 1990-01-02 1997-05-07 Motorola, Inc. Sequential prefetch method for 1, 2 or 3 word instructions
US5295249A (en) * 1990-05-04 1994-03-15 International Business Machines Corporation Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
JP2560889B2 (ja) * 1990-05-22 1996-12-04 日本電気株式会社 マイクロプロセッサ
JP2682761B2 (ja) * 1991-06-18 1997-11-26 松下電器産業株式会社 命令プリフェッチ装置
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
JPH06103068A (ja) * 1992-09-18 1994-04-15 Toyota Motor Corp データ処理装置
JPH06250854A (ja) * 1993-02-24 1994-09-09 Matsushita Electric Ind Co Ltd 命令プリフェッチ装置
JP3168845B2 (ja) * 1994-10-13 2001-05-21 ヤマハ株式会社 ディジタル信号処理装置
US5819056A (en) * 1995-10-06 1998-10-06 Advanced Micro Devices, Inc. Instruction buffer organization method and system
JP3655403B2 (ja) * 1995-10-09 2005-06-02 株式会社ルネサステクノロジ データ処理装置
JP2806359B2 (ja) * 1996-04-30 1998-09-30 日本電気株式会社 命令処理方法及び命令処理装置
DK1066559T3 (da) * 1998-03-18 2005-10-03 Qualcomm Inc Digital signalprocessor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4099229A (en) * 1977-02-14 1978-07-04 The United States Of America As Represented By The Secretary Of The Navy Variable architecture digital computer
US5293611A (en) * 1988-09-20 1994-03-08 Hitachi, Ltd. Digital signal processor utilizing a multiply-and-add function for digital filter realization
US5710914A (en) * 1995-12-29 1998-01-20 Atmel Corporation Digital signal processing method and system implementing pipelined read and write operations

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Morris Mano, Computer Engineering, International Ed, Prentice-Hall(1998)*

Also Published As

Publication number Publication date
CN1523491A (zh) 2004-08-25
HK1035594A1 (en) 2001-11-30
KR20010082524A (ko) 2001-08-30
AR026078A2 (es) 2002-12-26
KR20060040749A (ko) 2006-05-10
JP2010282637A (ja) 2010-12-16
JP6300284B2 (ja) 2018-03-28
DE69925720T2 (de) 2006-03-16
EP1066559B1 (en) 2005-06-08
WO1999047999A1 (en) 1999-09-23
CA2324219C (en) 2011-05-10
DK1066559T3 (da) 2005-10-03
JP5677774B2 (ja) 2015-02-25
KR100940465B1 (ko) 2010-02-04
AR026082A2 (es) 2002-12-26
AR026081A2 (es) 2002-12-26
EP1457876B1 (en) 2017-10-04
JP6152558B2 (ja) 2017-06-28
CA2324219A1 (en) 1999-09-23
HK1094608A1 (zh) 2007-04-04
JP2016146189A (ja) 2016-08-12
KR100896674B1 (ko) 2009-05-14
AU2986099A (en) 1999-10-11
EP1066559A1 (en) 2001-01-10
CN1301363A (zh) 2001-06-27
AR026079A2 (es) 2002-12-26
EP1457876A2 (en) 2004-09-15
DE69925720D1 (de) 2005-07-14
EP1457876A3 (en) 2006-11-02
AR026080A2 (es) 2002-12-26
JP2015028793A (ja) 2015-02-12
JP2002507789A (ja) 2002-03-12
KR20060040748A (ko) 2006-05-10
CN1279435C (zh) 2006-10-11
ATE297567T1 (de) 2005-06-15

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