AR026082A2 - Un procesador de senales digitales para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable, y un metodo para realizaruna operacion de multiplicacion de doble precision que utiliza dicho procesador de senales - Google Patents
Un procesador de senales digitales para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable, y un metodo para realizaruna operacion de multiplicacion de doble precision que utiliza dicho procesador de senalesInfo
- Publication number
- AR026082A2 AR026082A2 ARP000105486A ARP000105486A AR026082A2 AR 026082 A2 AR026082 A2 AR 026082A2 AR P000105486 A ARP000105486 A AR P000105486A AR P000105486 A ARP000105486 A AR P000105486A AR 026082 A2 AR026082 A2 AR 026082A2
- Authority
- AR
- Argentina
- Prior art keywords
- digital signal
- signal processor
- instructions
- processing
- processing units
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 3
- 230000004044 response Effects 0.000 title abstract 2
- 239000012634 fragment Substances 0.000 abstract 2
- 238000009825 accumulation Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0886—Variable-length word access
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30112—Register structure comprising data of variable length
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30141—Implementation provisions of register files, e.g. ports
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
- Memory System (AREA)
Abstract
Un procesador de senales digitales para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable. Almacenar una parte de lasinstrucciones con longitudes variables en lugares adyacentes dentro del espacio de la memoria yen el que el comienzo y el fin de las instrucciones tienenlugar entre los límites de palabras de memoria. Adicionalmente, otros aspectos adicionales de la presente se llevan a la práctica al contar con instruccionesque contengan cantidades variablesde fragmentos de instruccion. Cada fragmento de instruccion hace que se lleve a cabo una o más operaciones en particular, loque permite que se realicen multiples operaciones durante el ciclo de reloj. De esta manera, se llevan a cabo multiples operaciones durante caca ciclo de reloj, algo que reduce la cantidad total de ciclos de reloj necesarios para la realizacion de una tarea. Un método para realizar una operacion de multiplicacion dedoble precision que utiliza dicho procesador de senales digitales, se realiza por el uso de un banco de registro que cuenta con registros a los que puedenacceder al menos dos unidades de procesamiento. Esto hace posible que las multiples unidades de procesamiento puedan realizar multiples operaciones en ungrupode datos particular sin leer ni escribir los datos en y desde una memoria. Las unidades de procesamiento en la forma de realizacion ejemplar de la invencionincluyen una unidad aritmética logica (ALU) y una unidad de multiplicacion-acumulacion (MAC). Cuando se las combina con el uso de una arquitectura con busesmultiples, de instrucciones sumamente paralelas, o ambas, puede ponerse en práctica un aspecto adicional de la invencion, en el que se lleva a cabo unprocesamiento extremadamente encauzado y de multiples operaciones.
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US4410498A | 1998-03-18 | 1998-03-18 | |
US4408998A | 1998-03-18 | 1998-03-18 | |
US4408798A | 1998-03-18 | 1998-03-18 | |
US4410898A | 1998-03-18 | 1998-03-18 | |
US09/044,088 US6496920B1 (en) | 1998-03-18 | 1998-03-18 | Digital signal processor having multiple access registers |
US09/044,086 US6425070B1 (en) | 1998-03-18 | 1998-03-18 | Variable length instruction decoder |
Publications (1)
Publication Number | Publication Date |
---|---|
AR026082A2 true AR026082A2 (es) | 2002-12-26 |
Family
ID=27556460
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ARP000105484A AR026080A2 (es) | 1998-03-18 | 2000-10-18 | Una disposicion para controlar un procesador de senales digitales con instrucciones de longitud variable |
ARP000105482A AR026078A2 (es) | 1998-03-18 | 2000-10-18 | Un procesador de senales digitales, para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable |
ARP000105483A AR026079A2 (es) | 1998-03-18 | 2000-10-18 | Un metodo para operar un procesador de senales digitales que utiliza instrucciones de longitud variable y un procesador de senales digitales para llevar ala practica dicho metodo |
ARP000105486A AR026082A2 (es) | 1998-03-18 | 2000-10-18 | Un procesador de senales digitales para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable, y un metodo para realizaruna operacion de multiplicacion de doble precision que utiliza dicho procesador de senales |
ARP000105485A AR026081A2 (es) | 1998-03-18 | 2000-10-18 | Un metodo para controlar un procesador de senales digitales en respuesta a instrucciones de longitud variable |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ARP000105484A AR026080A2 (es) | 1998-03-18 | 2000-10-18 | Una disposicion para controlar un procesador de senales digitales con instrucciones de longitud variable |
ARP000105482A AR026078A2 (es) | 1998-03-18 | 2000-10-18 | Un procesador de senales digitales, para el procesamiento de una senal digital en respuesta a instrucciones de longitud variable |
ARP000105483A AR026079A2 (es) | 1998-03-18 | 2000-10-18 | Un metodo para operar un procesador de senales digitales que utiliza instrucciones de longitud variable y un procesador de senales digitales para llevar ala practica dicho metodo |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ARP000105485A AR026081A2 (es) | 1998-03-18 | 2000-10-18 | Un metodo para controlar un procesador de senales digitales en respuesta a instrucciones de longitud variable |
Country Status (12)
Country | Link |
---|---|
EP (2) | EP1457876B1 (es) |
JP (4) | JP2002507789A (es) |
KR (3) | KR100835148B1 (es) |
CN (2) | CN1279435C (es) |
AR (5) | AR026080A2 (es) |
AT (1) | ATE297567T1 (es) |
AU (1) | AU2986099A (es) |
CA (1) | CA2324219C (es) |
DE (1) | DE69925720T2 (es) |
DK (1) | DK1066559T3 (es) |
HK (2) | HK1094608A1 (es) |
WO (1) | WO1999047999A1 (es) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1457876B1 (en) * | 1998-03-18 | 2017-10-04 | Qualcomm Incorporated | Systems for and method of controlling a digital signal processor using a variable length instruction set, method of generating and storing said instructions and memory comprising said instructions |
JP4100300B2 (ja) | 2003-09-02 | 2008-06-11 | セイコーエプソン株式会社 | 信号出力調整回路及び表示ドライバ |
JP4661169B2 (ja) * | 2003-11-14 | 2011-03-30 | ヤマハ株式会社 | ディジタルシグナルプロセッサ |
JP4300151B2 (ja) * | 2004-04-19 | 2009-07-22 | Okiセミコンダクタ株式会社 | 演算処理装置 |
US7246218B2 (en) * | 2004-11-01 | 2007-07-17 | Via Technologies, Inc. | Systems for increasing register addressing space in instruction-width limited processors |
US7337272B2 (en) * | 2006-05-01 | 2008-02-26 | Qualcomm Incorporated | Method and apparatus for caching variable length instructions |
US11768689B2 (en) | 2013-08-08 | 2023-09-26 | Movidius Limited | Apparatus, systems, and methods for low power computational imaging |
US10001993B2 (en) | 2013-08-08 | 2018-06-19 | Linear Algebra Technologies Limited | Variable-length instruction buffer management |
FR3021427B1 (fr) * | 2014-05-22 | 2016-06-24 | Kalray | Structure de paquet d'instructions de type vliw et processeur adapte pour traiter un tel paquet d'instructions |
EP3175320B1 (en) * | 2014-07-30 | 2019-03-06 | Linear Algebra Technologies Limited | Low power computational imaging |
BR112017001981B1 (pt) * | 2014-07-30 | 2023-05-02 | Movidius Limited | Método para gerenciar buffer de instruções, sistema e memória legível por computador relacionados |
CN109496306B (zh) | 2016-07-13 | 2023-08-29 | 莫鲁米有限公司 | 多功能运算装置及快速傅里叶变换运算装置 |
JP7384374B2 (ja) * | 2019-02-27 | 2023-11-21 | 株式会社ウーノラボ | 中央演算処理装置 |
US11204768B2 (en) | 2019-11-06 | 2021-12-21 | Onnivation Llc | Instruction length based parallel instruction demarcator |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
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US4099229A (en) * | 1977-02-14 | 1978-07-04 | The United States Of America As Represented By The Secretary Of The Navy | Variable architecture digital computer |
US5293611A (en) * | 1988-09-20 | 1994-03-08 | Hitachi, Ltd. | Digital signal processor utilizing a multiply-and-add function for digital filter realization |
JP2791086B2 (ja) * | 1989-03-15 | 1998-08-27 | 富士通株式会社 | 命令プリフェッチ装置 |
EP0436341B1 (en) * | 1990-01-02 | 1997-05-07 | Motorola, Inc. | Sequential prefetch method for 1, 2 or 3 word instructions |
US5295249A (en) * | 1990-05-04 | 1994-03-15 | International Business Machines Corporation | Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel |
JP2560889B2 (ja) * | 1990-05-22 | 1996-12-04 | 日本電気株式会社 | マイクロプロセッサ |
JP2682761B2 (ja) * | 1991-06-18 | 1997-11-26 | 松下電器産業株式会社 | 命令プリフェッチ装置 |
US5438668A (en) * | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
JPH06103068A (ja) * | 1992-09-18 | 1994-04-15 | Toyota Motor Corp | データ処理装置 |
JPH06250854A (ja) * | 1993-02-24 | 1994-09-09 | Matsushita Electric Ind Co Ltd | 命令プリフェッチ装置 |
JP3168845B2 (ja) * | 1994-10-13 | 2001-05-21 | ヤマハ株式会社 | ディジタル信号処理装置 |
US5819056A (en) * | 1995-10-06 | 1998-10-06 | Advanced Micro Devices, Inc. | Instruction buffer organization method and system |
JP3655403B2 (ja) * | 1995-10-09 | 2005-06-02 | 株式会社ルネサステクノロジ | データ処理装置 |
US5710914A (en) * | 1995-12-29 | 1998-01-20 | Atmel Corporation | Digital signal processing method and system implementing pipelined read and write operations |
JP2806359B2 (ja) * | 1996-04-30 | 1998-09-30 | 日本電気株式会社 | 命令処理方法及び命令処理装置 |
EP1457876B1 (en) * | 1998-03-18 | 2017-10-04 | Qualcomm Incorporated | Systems for and method of controlling a digital signal processor using a variable length instruction set, method of generating and storing said instructions and memory comprising said instructions |
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1999
- 1999-03-04 EP EP04005665.7A patent/EP1457876B1/en not_active Expired - Lifetime
- 1999-03-04 WO PCT/US1999/004887 patent/WO1999047999A1/en active IP Right Grant
- 1999-03-04 CN CNB998063665A patent/CN1279435C/zh not_active Expired - Lifetime
- 1999-03-04 EP EP99911150A patent/EP1066559B1/en not_active Expired - Lifetime
- 1999-03-04 CA CA2324219A patent/CA2324219C/en not_active Expired - Fee Related
- 1999-03-04 DK DK99911150T patent/DK1066559T3/da active
- 1999-03-04 JP JP2000537132A patent/JP2002507789A/ja not_active Withdrawn
- 1999-03-04 DE DE69925720T patent/DE69925720T2/de not_active Expired - Lifetime
- 1999-03-04 KR KR1020067005980A patent/KR100835148B1/ko not_active IP Right Cessation
- 1999-03-04 AT AT99911150T patent/ATE297567T1/de not_active IP Right Cessation
- 1999-03-04 KR KR1020007010577A patent/KR100940465B1/ko not_active IP Right Cessation
- 1999-03-04 CN CNA031530303A patent/CN1523491A/zh active Pending
- 1999-03-04 KR KR1020067005979A patent/KR100896674B1/ko not_active IP Right Cessation
- 1999-03-04 AU AU29860/99A patent/AU2986099A/en not_active Abandoned
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2000
- 2000-10-18 AR ARP000105484A patent/AR026080A2/es unknown
- 2000-10-18 AR ARP000105482A patent/AR026078A2/es unknown
- 2000-10-18 AR ARP000105483A patent/AR026079A2/es unknown
- 2000-10-18 AR ARP000105486A patent/AR026082A2/es unknown
- 2000-10-18 AR ARP000105485A patent/AR026081A2/es unknown
-
2001
- 2001-09-04 HK HK07101408.7A patent/HK1094608A1/xx not_active IP Right Cessation
- 2001-09-04 HK HK01106221A patent/HK1035594A1/xx not_active IP Right Cessation
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2010
- 2010-07-09 JP JP2010157075A patent/JP5677774B2/ja not_active Expired - Lifetime
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2014
- 2014-09-05 JP JP2014181387A patent/JP6152558B2/ja not_active Expired - Lifetime
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2016
- 2016-03-03 JP JP2016040960A patent/JP6300284B2/ja not_active Expired - Lifetime
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