KR100819662B1 - Data output apparatus of semiconductor memory device - Google Patents

Abstract

The data output device of the semiconductor memory device according to the present invention forms a dummy path composed of the same elements as the path through which normal data is output, and configures the tracking signal to be transmitted through the dummy path in the same manner as the data transmission operation. Outputs the data output strobe signal in accordance with the tracking signal transmitted through the dummy path at the timing when the signal is input to the output driver, drives the output driver to transmit data to the data output pad, thereby reducing the data setup time A data output device of a semiconductor memory device capable of driving a semiconductor memory device in operation.

Description

Data output apparatus of semiconductor memory device

1 is a block diagram of a data output apparatus of a semiconductor memory device according to the prior art.

FIG. 2 is a detailed circuit diagram of a data output strobe signal generator in the data output device of the semiconductor memory device shown in FIG. 1.

3 is a block diagram showing a data output device of a semiconductor memory device according to the present invention;

4 is a detailed circuit diagram of a data output strobe signal generator in the data output device of the semiconductor memory device shown in FIG.

FIG. 5 is a detailed circuit diagram illustrating a tracking signal generator of a data output device of the semiconductor memory device shown in FIG. 3.

FIG. 6 is a detailed circuit diagram illustrating another example of a tracking signal generator of a data output device of the semiconductor memory device shown in FIG. 3.

FIG. 7 is a timing diagram illustrating an operation of a data output device of the semiconductor memory device shown in FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output device of a semiconductor memory device, and more particularly, to prevent a malfunction in outputting wrong data by driving the data output driver when data is substantially input to the data output driver, and to reduce data setup time. The present invention relates to a data output device of a semiconductor memory device capable of operating a semiconductor memory device at high speed.

In order to improve system performance, semiconductor memory devices, especially DRAMs, are continuously increasing in density and speed. In other words, DRAMs that process more data at a faster rate are required.

1 is a block diagram of a data output apparatus of a semiconductor memory device according to the prior art.

The data output device is controlled by the I / O sense amplifier strobe signal IOSASTB, an I / O sense amplifier (1) for sensing and amplifying data carried on the local I / O lines LIO and / LIO, and transmitting the data to the global lead I / O line GRIO, and the global lead I / O line. A multiplexer (2) for multiplexing the data carried on the GRIO, a pipe latch (3) for latching the multiplexed data sequentially and outputting in a first in first out manner, and controlled by a data output strobe signal And an output driver 4 for driving and outputting data output from the latch 3. Here, the output driver 4 is controlled by the data output strobe signal DOUTSTB generated by the data output strobe signal generator 5.                         

The input / output sense amplifier 1 senses and amplifies data loaded on the local I / O lines LIO and / LIO and transmits the data to the global read I / O line GRIO, and the multiplexer 2 multiplexes the data loaded on the global read I / O line GRIO. The multiplexed data is sent to the pipe latch 3.

The pipe latch 3 sequentially latches data loaded on the global read I / O line GRIO to output data in a first in first out manner, and outputs the latched data in response to an internal clock signal. In order).

The output driver 4 outputs data in synchronization with the data output strobe signal DOUTSTB, and is composed of pull-up means and pull-down means (not shown) that pull up or pull down according to the level of data transmitted from the pipe latch 3. .

FIG. 2 is a detailed circuit diagram of a data output strobe signal generator in the data output device of the semiconductor memory device shown in FIG. 1.

The data output strobe signal generation unit 5 includes a PMOS transistor PM1 for applying the enable signal EN to the gate and transmitting the power supply voltage VCC, and a latch unit 6 for latching the power supply voltage transferred by the PMOS transistor PM1. And an enable signal EN is applied to the gate and the NMOS transistor NM1 to which the pulse is connected to the ground supply voltage VSS, the substrate is connected to the ground supply voltage VSS, and the pulse clock signal DCLKp is applied to the gate. The NMOS transistor NM2, which is connected in series between the power supply voltage VCC and the ground power supply voltage VSS, is applied to the PMOS transistor PM2 and the gate to which the latch unit 6 and the voltage of the common node of the NMOS transistor NM1 are applied to the gate. NMOS transistor NM3 to which data output strobe signal DOUTSTB1 is applied, and PMOS transistors PM2 and NMOS transistors in common drain. Reset signal RST is applied to the latch portion 7 and the gate to invert the PMOS transistor PM3 and the reset signal RST to initialize the latch portion 6 and the common node of the NMOS transistor NM1 to the power supply voltage VCC. The inverter INV1 and an output signal of the inverter INV1 are applied to the gate, and the NMOS transistor NM4 initializes the output terminal of the latch unit 7 to the ground power supply voltage VSS. Here, the latch units 6 and 7 are non-inverting latches, and are configured in such a manner that output signals of the inverters INV2 and INV4 are applied as input signals of the other inverters INV3 and INV5, respectively.

Since the global lead input / output line GRIO of the semiconductor memory device is composed of one line, the pipe latch 3 always stores "0" or "1" data.

For example, if you want to output "0" data while "1" data is stored in the pipe latch 3, the data output strobe when the "0" data has not yet arrived in the pipe latch 3 When the signal DOUTSTB is enabled, the "1" data stored in the pipe latch 3 is driven by the output driver 4 to be output, and when "0" data arrives at the pipe latch 3, it is "0" from that point on. The data is driven and output by the output driver 4.

Therefore, in order to read accurate data from the data output pad DQ, a long data setup time must be set.                         

If the data setup time is set long, a problem arises in that the semiconductor memory device cannot be driven at high speed.

An object of the present invention for solving the above problems is to drive the data output driver when the data is input to the data output driver, thereby reducing the data setup time to improve the operation speed of the semiconductor memory device.

The present invention for achieving the above object is an input / output sense amplifier which is controlled by the input and output sense amplifier strobe signal to sense and amplify the data carried on the local input and output lines to transmit to the global read input and output lines;

A multiplexer which multiplexes data carried on the global read I / O lines;

Pipe latch means for sequentially latching data multiplexed by the multiplexer;

Output driver means controlled by a data output strobe signal to drive data transmitted from said pipe latch means and transmit it to a data output pad;

Tracking signal generating means for outputting a tracking signal using the input / output sense amplifier strobe signal;

A dummy multiplexer configured to be identical to the multiplexer and configured to multiplex the tracking signal;

Dummy pipe latch means configured to sequentially latch a tracking signal multiplexed by the dummy multiplexer, the same configuration being made of the same components as the pipe latch means; And

And a data output strobe signal generating means controlled by a tracking signal latched by the dummy pipe latch means and generating the data output strobe signal using a clock signal.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a data output device of a semiconductor memory device according to the present invention.

The data output device is controlled by an input / output sense amplifier strobe signal IOSASTB, an input / output sense amplifier 11 which senses and amplifies data carried on the local input / output line LIO, / LIO, and transmits the data to the global lead input / output line GRIO, and the global lead input / output line A multiplexer 12 for multiplexing the data carried in GRIO, a pipe latch 13 for sequentially latching the multiplexed data and outputting it in a first in first out manner, and controlled by a data output strobe signal. And an output driver 14 for driving and outputting data output from the latch 13. Here, the output driver 14 is controlled by the data output strobe signal DOUTSTB generated by the data output strobe signal generator 15, and the data output strobe signal generator 15 is controlled by the tracking signal generator 16. The data is transmitted to the data output driver 14 by the dummy multiplexer 17 and the dummy pipe latch 18, in which the tracking signal TRK generated using the amplifier strobe signal IOSASTB is configured to be the same as the multiplexer 12 and the pipe latch 13. Controlled by tracking signal TRK to generate data output strobe signal DOUTSTB at the time of input.

4 is a detailed circuit diagram of a data output strobe signal generator in the data output device of the semiconductor memory device shown in FIG. 3.

The data output strobe signal generation unit 15 includes a PMOS transistor PM11 for applying the enable signal EN to the gate to transmit the power supply voltage VCC, and a latch unit 19 for latching the power supply voltage transferred by the PMOS transistor PM11. And a transmission gate TG1 controlled by the signal inverted by the tracking signal TRK and the inverter INV16 to selectively transmit the pulse clock signal DCLKp, and connected in series between the latch portion 19 and the ground power supply voltage VSS, and the substrate being grounded. An NMOS transistor NM11 connected to a power supply voltage VSS and to which a pulse clock signal DCLKp selectively transmitted by a transfer gate TG1 is applied to a gate, and an NMOS transistor NM12 to which an enable signal EN is applied to a gate, a power supply voltage VCC and ground A node connected in series between the power supply voltage VSS and connected to a gate of which the output terminal of the latch portion 19 and the drain of the NMOS transistor NM11 are commonly NMOS transistor NM13 to which the next data output strobe signal DOUTSTB1 is applied to the PMOS transistor PM12 to which voltage is applied, and the latch part 20 which latches the voltage in the common drain of PMOS transistor PM12 and NMOS transistor NM13. And a reset signal RST applied to the gate to initialize the node where the output terminal of the latch unit 19 and the drain of the NMOS transistor NM11 are commonly connected to the power supply voltage VCC, and the inverter INV11 which inverts the reset signal RST. And an NMOS transistor NM14 for applying the output signal of the inverter INV11 to the gate to initialize the output terminal of the latch unit 20 to the ground power supply voltage VSS. Here, the latch units 19 and 20 are non-inverting latches, and are configured in such a manner that output signals of the inverters INV12 and INV14 are applied as input signals of the other inverters INV13 and INV15, respectively.

Therefore, when the data loaded on the local input / output lines LIO and / LIO are sensed and amplified by the input / output sense amplifier 11 and transmitted to the global read input / output line GRIO, the tracking signal generator 16 generates the tracking signal TRK. Here, since the input / output sense amplifier 11 and the tracking signal generator 16 are controlled by the same input / output sense amplifier strobe signal IOSASTB, the amplified data and the tracking signal TRK can be output at the same timing.

Data loaded on the global lead input / output line GRIO is input to the output driver 14 through the multiplexer 12 and the pipe latch 13, where the tracking signal TRK also has a dummy multiplexer 17 and a dummy pipe latch (with the same configuration). 18 is input to the data output strobe signal generator 15.

Therefore, when data is input to the output driver 14, the data output strobe signal generator 15 outputs the data output strobe signal DOUTSTB to drive the output driver 14 to transmit data to the data output pad DQ.                     

Here, in the data output strobe signal generator 15, the pulse clock signal DCLKp is transmitted by the transmission gate TG1 only when the tracking signal TRK transmitted through the dummy multiplexer 17 and the dummy pipe latch 18 is enabled. Generate the output strobe signal DOUTSTB. Therefore, since the output driver 14 is substantially driven when data is input to the output driver 14, the data setup time can be optimized.

FIG. 5 is a detailed circuit diagram illustrating the tracking signal generator 16 of the data output device of the semiconductor memory device shown in FIG. 3.

The tracking signal generator 16 is controlled by the signals inverted by the reset signal RST and the inverter INV21 to the transmission gates TG11 and TG12 for selectively transmitting the input / output sense amplifier strobe signal IOSASTB, and the transmission gates TG11 and TG12. A latch unit 21, 22 for latching a signal transmitted by each, and is connected in series between a power supply voltage VCC and a ground power supply voltage VSS, and to which a signal latched by the latch units 21, 22 is applied to a gate, respectively. MOS transistors PM21 and NMOS transistors NM23 and NMOS transistors NM21 and NM22 for applying the reset signal RST to the gate to initialize the input terminals of the latch portions 21 and 22 to the ground power supply voltage VSS. The tracking signal TRK is output from the common drain of the PMOS transistor PM21 and the NMOS transistor NM23. Here, the latch units 21 and 22 are inverted latches, and are configured such that output signals of the inverters INV22 and INV24 are applied to input terminals of the other inverters INV23 and INV25, respectively.

Therefore, when the input / output sense amplifier strobe signal IOSASTB is enabled at the high level, the tracking signal generator 16 turns on the PMOS transistor PM21, which is a pull-up means, to generate the high level tracking signal TRK.

FIG. 6 is a detailed circuit diagram of another example of a tracking signal generator of a data output device of a DRAM illustrated in FIG. 3.

The tracking signal generator 16 is controlled by the signals inverted by the reset signal RST and the inverter INV31 to the transmission gates TG21 and TG22 for selectively transmitting the input / output sense amplifier strobe signal IOSASTB, and the transmission gates TG21 and TG22. A latch unit 23, 24 for latching a signal transmitted by the latch, and a series connected between a power supply voltage VCC and a ground power supply voltage VSS, and to which a signal latched by the latch units 23 and 24 is applied to a gate, respectively. PMOS transistors PM31 for applying the MOS transistor PM33 and the NMOS transistor NM35 and a signal whose cascade latency signal CL3 is inverted by the inverter INV36 to set the input terminals of the latch portions 23 and 24 to the high level VCC, respectively. Transistors NM31 and NM connected in series between PM32 and the input terminals of the latch units 23 and 24 and the ground power supply voltage, respectively, and a reset signal RST is applied to the gate. 33 and NMOS transistors NM32 and NM34 which apply the cas latency signal / CL3 inverted by the inverter INV36 to set the input terminals of the latch portions 23 and 24 to the ground power supply voltage VSS. The tracking signal TRK is output from the common drain of the MOS transistor PM33 and the NMOS transistor NM35. Here, the latch units 23 and 24 operate as inverting latches, and are configured such that output signals of the inverters INV32 and INV34 are applied to input terminals of the other inverters INV33 and INV35, respectively.                     

7 is an operation timing diagram of a data output device of a semiconductor memory device according to the present invention. Here, the case where CAS Latency (CL) is "2" and Burst Length (BL) is set to "4" is described, for example.

When the bank is activated according to the active command ACT and data stored in the memory cell is loaded on the local I / O line LIO and / LIO by the read command RD, the I / O sense amplifier 11 reads the data loaded on the local I / O line LIO and / LIO. The sensing signal is amplified and output to the global lead input / output line GRIO. At this time, the tracking signal generator 16 also outputs the tracking signal TRK.

Thus, the data and tracking signal TRK on the global lead I / O line GRIO are output driver 14 and data output strobe signals respectively through paths formed through identically configured multiplexers 12 and 17 and pipe latches 13 and 18, respectively. It is applied to the generator 15.

At this time, the data output strobe signal generator 15 transmits the pulse clock signal DCLKp through the transmission gate TG1 in accordance with the timing of the tracking signal TRK to substantially transmit the data output strobe signal DOUTSTB when data is input to the output driver 14. And outputs the data through the data output pad DQ by driving the output driver 14.

As described above, the data output device of the semiconductor memory device according to the present invention can operate at a high speed because the output driver 14 is substantially driven when data is inputted, thereby reducing the data setup time.

 As described above, the data output device of the semiconductor memory device according to the present invention includes a device having the same configuration as a passage through which data is transmitted, and transmits a control signal to thereby output data when the data is substantially applied to the output driver. Since the data setup time can be reduced because the output driver is driven by generating the strobe signal, the semiconductor memory device can be operated at high speed.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (7)

Input / output sense amplifiers An input / output sense amplifier controlled by a strobe signal senses and amplifies data carried on a local input / output line and transmits the data to a global read input / output line; A multiplexer which multiplexes data carried on the global read I / O lines; Pipe latch means for sequentially latching data multiplexed by the multiplexer; Output driver means controlled by a data output strobe signal to drive data transmitted from said pipe latch means and transmit it to a data output pad; Tracking signal generating means for outputting a tracking signal using the input / output sense amplifier strobe signal; A dummy multiplexer configured to be identical to the multiplexer and configured to multiplex the tracking signal; Dummy pipe latch means configured to sequentially latch a tracking signal multiplexed by the dummy multiplexer, the same configuration being made of the same components as the pipe latch means; And And data output strobe signal generation means controlled by a tracking signal latched by said dummy pipe latch means and generating said data output strobe signal using a clock signal. The method of claim 1, The tracking signal generating means, A first transmission gate and a second transmission gate controlled by a reset signal to selectively transmit the input / output sense amplifier strobe signal; First and second latching means for latching the input / output sense amplifier strobe signal selectively transmitted by the first and second transmission gates; And And pull-up means and pull-down means for outputting the tracking signal by pulling up or pulling down the signals latched by the first latching means and the second latching means, respectively. The method of claim 2, The tracking signal generating means, And a first initialization means and a second initialization means for initializing the input terminals of the first latching means and the second latching means to ground power potentials, respectively. The method of claim 3, wherein The tracking signal generating means, And a first driving means and a second driving means controlled by a cas latency signal to set the input terminals of the first latching means and the second latching means to a high level, respectively. . The method of claim 1, The data output strobe signal generating means, Transmission means controlled by the tracking signal to selectively transmit the clock signal; Driving means for driving a clock signal selectively transmitted by said transmission means; And And latching means for latching a clock signal driven by said driving means. The method of claim 5, wherein The data output strobe signal generating means, Enable means controlled by an enable signal to enable the driving means; And And a latch means for latching a power supply voltage transmitted to said enable means. The method of claim 5, wherein The data output strobe signal generating means, First initialization means controlled by an initialization signal to initialize an input terminal of the driving means; And And a second initialization means controlled by the initialization signal to initialize the output terminal of the latch means.

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