KR100811524B1 - Plasma display apparatus - Google Patents

Abstract

A plasma display apparatus is provided to reduce a manufacturing cost by generating commonly at least two of plural driving signals. A plasma display apparatus includes a plasma display panel(100) and a driver(110). The plasma display panel includes first and second electrodes, and third electrodes which are formed to cross with the first and second electrodes. The driver supplies a ramp-down signal in which a voltage is decreased gradually, to the first electrodes during a reset period for initialization, supplies a scan bias signal and a scan signal which is decreased from the scan bias signal, to the first electrode during an address period, supplies a data signal to the third electrode corresponding to the scan signal, supplies a sustain signal to at least one of the first and second electrodes during a sustain period, and generates the voltages of the scan, ramp-down, scan bias signals based on the voltages of the sustain signal or data signal.

Description

Plasma Display Apparatus {Plasma Display Apparatus}

1 is a view for explaining an example of the configuration of a plasma display device according to an embodiment of the present invention.

2 is a view for explaining an example of the structure of a plasma display panel that can be included in the plasma display panel according to an embodiment of the present invention.

3 is a view for explaining an example where at least one of the first electrode or the second electrode is a plurality of layers;

4 is a view for explaining an example in the case where at least one of the first electrode or the second electrode is a single layer;

FIG. 5 is a diagram for describing an image frame for implementing gray levels of an image in a plasma display device according to an embodiment of the present invention. FIG.

6A to 6B are views for explaining an example of the configuration of the drive unit.

7A to 7C are diagrams for explaining an example of the operation of the driving unit.

<Description of the numbers for the main parts of the drawings>

100: plasma display panel 110: driver

The present invention relates to a plasma display device (Plasma Display Apparatus).

The plasma display apparatus includes a plasma display panel having electrodes formed thereon and a driving unit supplying driving signals to the electrodes of the plasma display panel.

In general, a phosphor layer is formed in a discharge cell (Cell) partitioned by a partition, and a plurality of electrodes are formed in the plasma display panel.

The driver supplies a driving signal to the discharge cell through the electrode.

Then, the discharge is generated by the drive signal supplied in the discharge cell. Here, when discharged by a drive signal in the discharge cell, the discharge gas filled in the discharge cell generates light such as ultraviolet rays, and the light such as ultraviolet light emits phosphors formed in the discharge cell. Generates visible light The visible light displays an image on the screen of the plasma display panel.

On the other hand, the conventional plasma display device is provided with a plurality of voltage generation circuit for generating a voltage of the drive signal. As a result, a problem arises in that the manufacturing cost increases.

In order to solve the above problems, an embodiment of the present invention is to provide a plasma display device in which one voltage generating circuit generates at least two driving signals among a plurality of driving signals.

Plasma display device according to an embodiment of the present invention for achieving the above object is a plasma display panel including a first electrode and a second electrode parallel to each other and a third electrode crossing the first electrode and the second electrode, and initialization Supply a falling ramp signal to which the voltage gradually falls to the first electrode in a reset period for the second period; supply a scan signal that falls from the scan bias signal and the scan bias signal to the first electrode in the address period after the reset period; The data signal is supplied to the electrode in correspondence with the scan signal, the sustain signal is supplied to at least one of the first electrode and the second electrode in the sustain period after the address period, the voltage of the scan signal, the voltage of the falling ramp signal, and the scan bias. The voltage of the signal to the voltage of the sustain signal or the voltage of the data signal It includes a driving unit for generating from.

Further, the voltage of the scan bias signal is generated from a part of the voltage of the scan signal or the voltage of the falling ramp signal.

The driving unit may include a scan top switch unit and a scan bottom switch unit, and a scan drive integrated circuit unit connected to the first electrode between the scan top switch unit and the scan bottom switch unit. And a voltage of the falling ramp signal or the voltage of the scan signal is supplied to the first electrode through the scan bottom switch unit by being turned on in a reset period or a part of the address period, and is turned off in a part of the address period to be off And a scan and reset common switch configured to supply a voltage of the scan bias signal to the first electrode through the switch.

In addition, a portion having a first voltage between two nodes is included between the scan and reset common switch unit and the scan top switch unit, and between the two nodes between the scan and reset common switch unit and the scan bottom switch unit. A portion having one voltage and a node having a second voltage between the two nodes are included, the second voltage being substantially equal to the voltage of the scan bias signal.

Also, the sum of the first voltage and the second voltage is substantially equal to the voltage of the scan signal or the voltage of the falling ramp signal.

Hereinafter, a plasma display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view for explaining an example of the configuration of a plasma display device according to an embodiment of the present invention.

1, a plasma display apparatus according to an embodiment of the present invention includes a plasma display panel 100 and a driver 110.

The plasma display panel 100 includes a first electrode and a second electrode which are parallel to each other, and a third electrode which crosses the first electrode and the second electrode.

The driver 110 supplies a ramp-down signal in which a voltage gradually decreases to the first electrode of the plasma display panel 100 during a reset period. In addition, in the address period after the reset period, a scan bias signal and a scan signal falling from the scan bias signal are supplied to the first electrode, and a data signal is supplied to the third electrode corresponding to the scan signal. In the sustain period after the address period, the sustain signal is supplied to at least one of the first electrode and the second electrode.

Here, the driver 110 generates the voltage of the scan signal, the voltage of the falling ramp signal, and the voltage of the scan bias signal from the voltage of the sustain signal or the voltage of the data signal.

Here, in FIG. 1, only the case in which the driving unit 110 is formed in one board form is illustrated, but in the present invention, the driving unit 110 is divided into a plurality of board forms according to electrodes formed on the plasma display panel 100. It is also possible to lose.

For example, the driver 110 may include a first driver (not shown) for driving the first electrode of the plasma display panel 100, a second driver for driving the second electrode, and a third for driving the third electrode. It can be divided into a driving unit (not shown).

The driving unit 110 of the plasma display device of the present invention will be more clearly described later.

Next, FIG. 2 is a view for explaining an example of a structure of a plasma display panel that may be included in a plasma display device according to an embodiment of the present invention.

Referring to FIG. 2, a plasma display panel that may be included in a plasma display apparatus according to an exemplary embodiment of the present invention has a front substrate 201 in which first electrodes 202 and Y and second electrodes 203 and Z are parallel to each other. ) And the back substrate 211 on which the third electrodes 213 and X intersecting the first electrodes 202 and Y and the second electrodes 203 and Z are formed.

An electrode such as first electrodes 202 and Y and second electrodes 203 and Z may be formed on the front substrate 201. The first electrodes 202 and Y and the second electrodes 203 and Z may generate a discharge in a discharge space, that is, a discharge cell, and maintain the discharge of the discharge cell.

The dielectric layer covers the first electrode 202 and the second electrode 203 and Z on the front substrate 201 where the first electrode 202 and the second electrode 203 and Z are formed. For example, upper dielectric layer 204 may be formed.

This upper dielectric layer 204 limits the discharge current of the first electrode 202, Y and the second electrode 203, Z and between the first electrode 202, Y and the second electrode 203, Z. Can be insulated.

A protective layer 205 may be formed on the upper dielectric layer 204 to facilitate a discharge condition. The protective layer 205 may be formed through a method of depositing a material such as magnesium oxide (MgO) on the upper dielectric layer 204.

Meanwhile, electrodes, for example, third electrodes 213 and X are formed on the rear substrate 211, and third electrodes 213 and X are formed on the rear substrate 211 on which the third electrodes 213 and X are formed. A dielectric layer, such as lower dielectric layer 215, may be formed to cover the gap.

The lower dielectric layer 215 may insulate the third electrodes 213 and X.

On top of the lower dielectric layer 215, a partition 212, such as a stripe type, a well type, a delta type, a honeycomb type, for partitioning a discharge cell, that is, a discharge cell, is formed. Can be formed. Accordingly, discharge cells such as red (R), green (G), and blue (B) may be formed between the front substrate 201 and the rear substrate 211.

In addition to the red (R), green (G), and blue (B) discharge cells, it is also possible to further form a white (W) or yellow (Yellow: Y) discharge cell.

On the other hand, the pitch of the red (R), green (G) and blue (B) discharge cells in the plasma display panel that can be included in the plasma display device according to an embodiment of the present invention may be substantially the same. The pitches of the red (R), green (G) and blue (B) discharge cells may be varied to match the color temperature in the red (R), green (G) and blue (B) discharge cells.

In this case, the pitch may be different for each of the red (R), green (G), and blue (B) discharge cells, but the pitch of one or more discharge cells among the red (R), green (G), and blue (B) discharge cells. May be different from the pitch of other discharge cells. For example, the pitch of the red (R) discharge cells is the smallest, and the pitch of the green (G) and blue (B) discharge cells may be larger than the pitch of the red (R) discharge cells.

Here, the pitch of the green (G) discharge cells may be substantially the same as or different from the pitch of the blue (B) discharge cells.

In addition, the plasma display panel that may be included in the plasma display apparatus according to an exemplary embodiment of the present invention may have not only the structure of the partition 212 illustrated in FIG. 2 but also the structure of the partition having various shapes. For example, the partition 212 includes a first partition 212b and a second partition 212a, where the height of the first partition 212b and the height of the second partition 212a are different from each other. At least one of the first barrier rib 212b and the second barrier rib 212a, and a channel type barrier rib structure having a channel usable as an exhaust passage, at least one of the first barrier rib 212b and the second barrier rib 212a. Grooved partition wall structure having a groove formed in the groove will be possible.

Here, in the case of the differential partition structure, the height of the first partition 212b of the first partition 212b or the second partition 212a may be lower than the height of the second partition 212a. In addition, in the case of the channel barrier rib structure or the groove barrier rib structure, a channel or a groove may be formed in the first barrier rib 212b.

On the other hand, in the plasma display panel that can be included in the plasma display device according to an embodiment of the present invention, although the red (R), green (G) and blue (B) discharge cells are shown and described as being arranged on the same line, It may be possible to arrange them in other shapes. For example, a delta type arrangement in which red (R), green (G) and blue (B) discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may also be a variety of polygonal shapes, such as pentagonal, hexagonal, as well as rectangular.

In addition, in FIG. 2, only the case where the partition wall 212 is formed on the rear substrate 211 is illustrated, but the partition wall 212 may be formed on at least one of the front substrate 201 and the rear substrate 211.

Here, a predetermined discharge gas may be filled in the discharge cell partitioned by the partition wall 212.

In addition, a phosphor layer 214 that emits visible light for image display may be formed in the discharge cells partitioned by the partition wall 212. For example, red (R), green (G), and blue (B) phosphor layers may be formed.

In addition to the red (R), green (G), and blue (B) phosphors, it is also possible to further form a white (W) and / or yellow (Y) phosphor layer.

In addition, the phosphor layers 214 of the red (R), green (G), and blue (B) discharge cells may have substantially the same thickness or may differ from one or more. For example, if the thickness of the phosphor layer 214 in at least one of the red (R), green (G), and blue (B) discharge cells is different from the other discharge cells, green (G) or blue (B) The thickness of the phosphor layer 214 in the discharge cell may be thicker than the thickness of the phosphor layer 214 in the red (R) discharge cell. Here, the thickness of the phosphor layer 214 in the green (G) discharge cell may be substantially the same as or different from the thickness of the phosphor layer 214 in the blue (B) discharge cell.

In the above description, only one example of the plasma display panel which may be included in the plasma display apparatus according to the exemplary embodiment of the present invention is illustrated and described. However, one embodiment of the present invention is not limited to the plasma display panel having the above-described structure. To reveal. For example, the description hereinabove illustrates only the case where the top dielectric layer at number 204 and the bottom dielectric layer at number 215 are each one layer, but one or more of these top dielectric layers and bottom dielectric layers are a plurality of layers. It can also be layered.

In addition, a black layer (not shown) may be further formed on the partition 212 to prevent reflection of the external light due to the partition 212.

In addition, a black layer (not shown) may be further formed at a specific position on the front substrate 201 corresponding to the partition 212.

In addition, the width or thickness of the third electrode 213 formed on the rear substrate 211 may be substantially constant, but the width or thickness inside the discharge cell may be different from the width or thickness outside the discharge cell. will be. For example, the width or thickness inside the discharge cell may be wider or thicker than that outside the discharge cell.

Next, FIG. 3 is a figure for explaining an example in the case where at least one of a 1st electrode or a 2nd electrode is a some layer.

Referring to FIG. 3, at least one of the first electrode 202 or the second electrode 203 may be formed of a plurality of layers, for example, two layers.

For example, in consideration of light transmittance and electrical conductivity, at least one of the first electrode 202 or the second electrode 203 is made of silver (silver) to emit light generated in the discharge cell to the outside and to secure driving efficiency. Bus electrodes 202b and 203b including a substantially opaque material such as Ag) and transparent electrodes 202a and 203a including a transparent material such as transparent indium tin oxide (ITO). .

As such, when the first electrode 202 and the second electrode 203 include the transparent electrodes 202a and 203a, visible light generated in the discharge cell can be effectively emitted when emitted to the outside of the plasma display panel. .

In addition, when the first electrode 202 and the second electrode 203 include the bus electrodes 202b and 203b, the first electrode 202 and the second electrode 203 include only the transparent electrodes 202a and 203a. In this case, the driving efficiency can be reduced because the electrical conductivity of the transparent electrodes 202a and 203a is relatively low, and it is possible to compensate for the low electrical conductivity of the transparent electrodes 202a and 203a which can cause such a reduction in the driving efficiency. Can be.

As described above, in the case where the first electrode 202 and the second electrode 203 include the bus electrodes 202b and 203b, the transparent electrodes 202a and 203b may be used to prevent reflection of external light by the bus electrodes 202b and 203b. Black layers 320 and 321 may be further provided between the 203a and the bus electrodes 202b and 203b.

Next, FIG. 4 is a figure for explaining an example in the case where at least one of a 1st electrode or a 2nd electrode is a single layer.

Referring to FIG. 4, the first electrodes 202 and Y and the second electrodes 203 and Z are one layer. For example, the first electrodes 202 and Y and the second electrodes 203 and Z may be electrodes (ITO-Less) in which the transparent electrode of numeral 202a or 203a is omitted in FIG. 3.

At least one of the first electrode 202 and Y or the second electrode 203 and Z may include a substantially opaque electrically conductive metal material. For example, it may include a material having excellent electrical conductivity such as silver (Ag), copper (Cu), aluminum (Al), and the like, and a material having a lower cost than a transparent material such as indium tin oxide (ITO). .

In addition, at least one of the first electrode 202 and the second electrode 203 and Z may be darker in color than the upper dielectric layer of FIG. 2.

As such, when at least one of the first electrode 202 and the second electrode 203 and Z is a single layer, the manufacturing process is simpler than in the case of FIG. 3. For example, in the case of FIG. 3, the bus electrodes 202b and 203b are formed after the transparent electrodes 202a and 203a are formed in the process of forming the first electrodes 202 and Y and the second electrodes 203 and Z. 4 again, the first electrode 202 and Y and the second electrode 203 and Z can be formed in one process because the single layer structure of FIG.

In addition, as shown in FIG. 4, when the first electrodes 202 and Y and the second electrodes 203 and Z are formed in a single layer, the manufacturing process is simplified and relatively expensive indium-tin-oxide (ITO) or the like. Since it is not necessary to use a transparent material of the manufacturing cost can be reduced.

Meanwhile, discoloration of the front substrate 201 is prevented between the first electrodes 202 and Y and the second electrodes 203 and Z and the front substrate 201, and the first electrode 202 or Y or the second electrode ( Black layers 400a and 400b having a darker color than at least one of 203 and Z) may be further provided. That is, when the front substrate 201 and the first electrode 202, Y or the second electrode 203, Z are in direct contact, the first electrode 202, Y or the second electrode 203, Z is directly in contact with each other. Migration phenomenon may occur in which a predetermined area of the front substrate 201 that is in contact with the yellow color is changed. The black layers 400a and 400b may prevent the migration of the front substrate 201 by preventing the migration phenomenon. It can be.

The black layers 400a and 400b may include a black material having a substantially dark color, for example, ruthenium (Rb).

As such, when the black layers 400a and 400b are provided between the front substrate 201 and the first electrodes 202 and Y and the second electrodes 203 and Z, the first electrodes 202 and Y may be provided. Even if the second electrodes 203 and Z are made of a material having high reflectance, generation of reflected light can be prevented.

As such, the structure of the plasma display panel which may be included in the plasma display apparatus according to the exemplary embodiment may be variously changed.

Next, FIG. 5 is a diagram for describing an image frame for implementing gradation of an image in a plasma display device according to an embodiment of the present invention.

Referring to FIG. 5, an image frame for implementing gray levels of an image in a plasma display device according to an embodiment of the present invention may be divided into a plurality of subfields having different emission counts.

Although not shown, one or more subfields among the plurality of subfields may be grayed out according to a reset period for initializing discharge cells, an address period for selecting discharge cells to be discharged, and the number of discharges. It can be divided into the sustain period to implement.

For example, when an image is to be displayed with 256 gray scales, for example, one image frame is divided into eight subfields SF1 to SF8 as shown in FIG. 5, and each of the eight subfields SF1 to SF8, respectively. Can be subdivided into a reset period, an address period and a sustain period.

The gray scale weight of the corresponding subfield may be set by adjusting the number of the sustain signals supplied in the sustain period. That is, a predetermined gray scale weight can be given to each subfield using the sustain period. For example, the gray scale weight of each subfield is 2 ⁿ by setting the gray scale weight of the first subfield to 2 ⁰ and the gray scale weight of the second subfield to 2 ¹ (where n = 0, 1). , 2, 3, 4, 5, 6, and 7) to increase the gray scale weight of each subfield. As described above, the number of sustain signals supplied in the sustain period of each subfield is adjusted according to the gray scale weight in each subfield, thereby implementing gray levels of various images.

A plasma display panel according to an embodiment of the present invention uses a plurality of image frames to implement an image, for example, to display an image of 1 second. For example, 60 image frames are used to display an image of 1 second. In this case, the length T of one image frame may be 1/60 second, that is, 16.67 ms.

In FIG. 5, only one image frame is composed of eight subfields. However, the number of subfields constituting one image frame may be variously changed. For example, one video frame may be configured with 12 subfields from the first subfield to the twelfth subfield, or one video frame may be configured with 10 subfields.

In addition, in FIG. 5, subfields are arranged in increasing order of gray scale weight in one image frame. Alternatively, subfields may be arranged in order of decreasing gray scale weight in one image frame. Alternatively, subfields may be arranged regardless of the gray scale weight.

6A to 6B are diagrams for explaining an example of the configuration of the drive unit.

First, referring to FIG. 6A, the driving unit may include a scan drive integrated circuit 630 and a scan and reset common switch unit 640.

The scan drive integrated circuit unit 630 includes a scan top switch unit S7 and a scan bottom switch unit S8. Here, the first electrode of the plasma display panel is connected between the scan top switch unit S7 and the scan bottom switch unit S8.

The scan and reset common switch unit 640 may include a scan and reset common switch S9 and a second variable resistance unit VR2 connected to a gate terminal of the scan and reset common switch S9. Here, although all switching elements are shown as switches in FIG. 6A, transistors such as FETs can also be used. The foregoing is referred to as the gate terminal of the scan and reset common switch S9 because the scan and reset common switch S9 may include a transistor such as a FET.

The scan and reset common switch unit 640 is turned on during a reset period or an address period for initialization, and thus the voltage of the falling ramp signal or the scan signal is transferred to the first electrode through the scan bottom switch unit S8. The voltage is supplied and turned off in a part of the address period so that the voltage of the scan bias signal is supplied to the first electrode through the scan top switch S7.

Here, a portion having the first voltage V1 between two nodes is included between the scan and reset common switch unit 640 and the scan top switch unit S7. For example, the first voltage V1 is between the seventh node n7 and the sixth node n6.

In addition, a portion having a first voltage V1 between two nodes and a node having a second voltage V2 between two nodes are included between the scan and reset common switch unit 640 and the scan bottom switch unit S8. do. For example, the second voltage V2 is between the sixth node n6 and the fifth node n5.

Here, the second voltage V2 may be substantially the same as the voltage of the scan bias signal, that is, Vsc. In addition, the sum of the first voltage V1 and the second voltage V2 may be substantially equal to the voltage Vy of the scan signal or the voltage of the falling ramp signal. This will be further clarified in the following description.

In addition to the scan drive integrated circuit 630 and the scan and reset common switch unit 640, the driver further includes an energy recovery circuit 600, a sustain lamp supply unit 610, and a blocking unit 620. can do.

The energy recovery circuit unit 600 may include a voltage storage unit 601, a storage voltage supply unit 602, a voltage recovery unit 603, a resonator unit 606, a sustain voltage supply unit 604, and a base voltage supply unit 605. Can be.

The voltage storage unit 601 includes a voltage storage capacitor unit C, and stores the voltage using the energy storage capacitor unit C.

The storage voltage supply unit 602 includes a storage voltage supply control switch unit S1, and the voltage stored in the voltage storage unit 601 by using the storage voltage supply control switch unit S1 is the first of the plasma display panel. Supply to the electrode or the second electrode.

The voltage recovery unit 603 includes a voltage recovery control switch unit S2, and the reactive energy of the first electrode or the second electrode of the plasma display panel is reduced by using the voltage recovery control switch unit S2. 601) to be recovered and stored.

The resonator 606 includes a resonant inductor part L. When the voltage stored in the voltage storage part 601 is supplied to the first electrode or the second electrode by using the resonant inductor part L, Generate resonance. In addition, the resonator 606 generates LC resonance when the voltage is recovered from the first electrode or the second electrode to the voltage storage unit 601.

The sustain voltage supply unit 604 includes a sustain voltage supply control switch unit S3, and the sustain voltage source Vs generated by the sustain voltage source using the sustain voltage supply control switch unit S3 is the first electrode or the second electrode. To be supplied to the electrode.

The base voltage supply unit 605 includes a base voltage supply control switch unit S4, and the base voltage GND generated by the base voltage source using the base voltage supply control switch unit S4 is the first electrode or the second electrode. To be supplied to the electrode. That is, the first electrode or the second electrode is grounded.

The sustain lamp supply unit 610 includes a rising ramp supply control switch unit S5 and a first variable resistor unit VR1 connected to the gate terminal of the rising ramp supply control switch unit S5. The supply of the rising ramp voltage to the scan electrode Y is controlled by using the switch section S5 and the first variable resistance section VR1.

The blocking part 620 includes a blocking switch part S6, and inverts the current from the direction of the fifth node n5 to the ground GND through the base voltage supply part 605 by using the blocking switch part S6. To prevent Ryu.

Next, referring to FIG. 6B, an example of generation of the first voltage V1 and the second voltage V2 is illustrated.

For example, when an input voltage Vin is applied to an input terminal of the converter 670, the converter 670 converts the input voltage Vin into direct current (DC-DC) to output an output voltage Vout having a predetermined magnitude. do.

The input voltage Vin may be a voltage of the sustain signal or a voltage of the data signal. Also, the output voltage Vout may be the voltage Vy of the scan signal or the voltage of the falling ramp signal.

The voltage of the sustain signal, the voltage of the scan signal, the voltage of the falling ramp signal, and the voltage of the data signal mentioned above will be clearer from the following description.

The output voltage Vout may be divided into the first voltage V1 and the second voltage V2 by the first resistor portion R1 and the second resistor portion R2. Here, the second voltage V2 is a voltage of the scan bias signal. As such, the voltage of the scan bias signal is generated from a portion of the voltage of the scan signal or the voltage of the falling ramp signal.

Next, FIGS. 7A to 7C are diagrams for explaining an example of the operation of the driving unit. Here, in FIGS. 7A to 7C, the first voltage V1 and the second voltage are generated from the voltage of the sustain signal or the data voltage, as shown in FIG. 6A, between the seventh node n7 and the sixth node n6. It is assumed that the first voltage V1 is applied and the second voltage V2 is applied between the fifth node n5 and the sixth node n6. Alternatively, between the seventh node n7 where the first voltage V1 is applied and the sixth node n6 are constant voltage sources that supply the first voltage V1, and the fifth node where the second voltage V2 is applied. Between the n5 and the sixth node n6 may be a constant voltage source supplying the second voltage V2.

First, referring to FIG. 7A, the scan and reset common switch S9 of the scan and reset common switch unit 640 and the scan bottom switch unit S8 of the scan drive integrated circuit unit 630 are turned off in the setup period of the reset period. (Off), the scan top switch unit S7 of the scan drive integrated circuit unit 630, the blocking switch unit S6 of the blocking unit 620, and the base voltage supply control switch unit S4 of the base voltage supply unit 605. Is On.

Accordingly, the voltage between the sixth node n6 and the fifth node n5, that is, the second voltage V2 is supplied to the first electrode via the sixth node n6 and the scan top switch unit S7. . Here, note the voltage direction of the second voltage V2 shown in Fig. 6A. This process is shown in Figure 7c.

Then, as in the setup period of the reset period of FIG. 7A, the voltage of the first electrode may rise to the second voltage V2. That is, the voltage may rise up to the voltage Vsc of the scan bias signal.

Thereafter, the sustain lamp supply control switch S5 of the sustain lamp supply unit 610 is turned on.

Here, while the channel width of the sustain lamp supply control switch unit S5 is adjusted by the first variable resistor unit VR1 connected to the gate terminal of the sustain lamp supply control switch unit S5, the voltage gradually increases. A rise ramp signal is generated and this rise ramp signal can be supplied to the first electrode.

Accordingly, as in the setup period of the reset period, the voltage of the first electrode is from the second voltage V2, that is, the voltage Vs of the sustain signal and the voltage Vsc of the scan bias signal from the voltage Vsc of the scan bias signal. Can gradually rise to the sum of. As such, a signal that gradually rises from the voltage Vsc of the scan bias signal to the sum of the voltage Vs of the sustain signal and the voltage Vsc of the scan bias signal is called a ramp-up signal.

As the rising ramp signal is supplied, dark discharge, that is, setup discharge, occurs in the discharge cell. By this setup discharge, some wall charges can be accumulated in the discharge cells.

Here, the voltage of the first electrode may gradually increase even when the voltage of the first electrode increases to the voltage Vsc of the scan bias signal.

Next, in the set-down period of the reset period, the scan and reset common switch S9 of the scan and reset common switch unit 640 and the scan bottom switch unit S8 of the scan drive integrated circuit unit 630 are turned on, and the scan drive integrated circuit unit is turned on. The scan top switch S7 of 630 and the blocking switch S6 of the blocking 620 are turned off.

Accordingly, current paths of the scan and reset common switch unit S9, the seventh node n7, the sixth node n6, the fifth node n5, and the scan bottom switch unit S8 are formed. The voltage between the seventh node n7 and the sixth node n6, the first voltage V1 and the voltage between the sixth node n6 and the fifth node n5, that is, the second voltage V2 Supplied to the first electrode. Here, note the voltage directions of the first voltage V1 and the second voltage V2 shown in FIG. 6A.

Here, the voltage is gradually decreased while the channel width of the scan and reset common switch unit S9 is adjusted by the second variable resistor unit VR2 connected to the gate terminal of the scan and reset common switch unit S9. A falling ramp signal is generated, and this falling ramp signal may be supplied to the first electrode. As such, the process is shown in FIG. 7B.

Then, as in the set-down period of the reset period of FIG. 7A, the voltage of the first electrode may gradually decrease. As such, the signal in which the voltage gradually falls is referred to as a ramp-down signal.

As the falling ramp signal is supplied, a weak erase discharge, that is, a setdown discharge, occurs in the discharge cell. By this set-down discharge, wall charges such that address discharge can be stably generated in the discharge cells remain uniformly.

Next, in the address period after the reset period, the scan and reset common switch S9 and the scan top switch unit S7 of the scan and reset common switch unit 640 are turned on, and the scan bottom switch unit S8 and the blocking unit ( The blocking switch S6 of 620 and the base voltage supply control switch S4 of the base voltage supply 605 are turned off.

Accordingly, the voltage between the seventh node n7 and the sixth node n6, that is, the first voltage V1 is supplied to the first electrode via the sixth node n6 and the scan top switch unit S7. . Then, as in the address period after the reset period of FIG. 7A, the voltage of the first electrode may increase by the voltage Vsc of the scan bias signal from the end of the falling ramp signal. Accordingly, the scan bias signal is supplied to the first electrode.

As such, the scan and reset common switch S9 of the scan and reset common switch unit 640 and the scan bottom switch unit S8 of the scan drive integrated circuit unit 630 are turned on while the scan bias signal is supplied, and the scan drive is turned on. The scan top switch unit S7 of the integrated circuit unit 630 and the blocking switch unit S6 of the blocking unit 620 may be turned off.

Accordingly, current paths of the scan and reset common switch unit S9, the seventh node n7, the sixth node n6, the fifth node n5, and the scan bottom switch unit S8 are formed, and the seventh The voltage between the node n7 and the sixth node n6, the first voltage V1 and the voltage between the sixth node n6 and the fifth node n5, that is, the second voltage V2 It is supplied to one electrode.

Then, as in the address period of FIG. 7A, the scan signal Sp falling from the scan bias signal may be supplied to the first electrode.

On the other hand, the width of the scan signal in units of subfields may vary. That is, the width of the scan signal Scan in at least one subfield may be different from the width of the scan signal Scan in other subfields. For example, the width of the scan signal Scan in the subfield located later in time may be smaller than the width of the scan signal Scan in the subfield located earlier. In addition, the scan signal scan width decreases according to the arrangement order of the subfields, such as 2.6 Hz (microsecond), 2.3 Hz (microsecond), 2.1 Hz (microsecond), 1.9 Hz (microsecond), and the like. Or 2.6 ㎲ (microseconds), 2.3 ㎲ (microseconds), 2.3 ㎲ (microseconds), 2.1 ㎲ (microseconds) ... 1.9 ㎲ (microseconds), 1.9 ㎲ (microseconds) It could be done.

As such, when the scan signal Scan is supplied to the first electrode, a data signal rising by the magnitude ΔVd of the data voltage may be supplied to the third electrode to correspond to the scan signal.

As the scan signal Scan and the data signal Data are supplied, the voltage difference between the voltage of the scan signal and the data voltage Vd of the data signal and the wall voltage generated by the wall charges generated in the reset period are In addition, address discharge may occur in a discharge cell to which the voltage Vd of the data signal is supplied.

Here, a sustain bias signal may be supplied to the second electrode Z to prevent address discharge from becoming unstable due to interference of the second electrode Z in the address period.

Here, the sustain bias signal may maintain a substantially constant sustain bias voltage Vz smaller than the voltage of the sustain signal supplied in the sustain period and greater than the voltage of the ground level GND.

In the sustain period after the above address period, first, the storage voltage supply unit 602 is turned on while the voltage recovery unit 603, the sustain voltage supply unit 604, and the base voltage supply unit 605 are turned off. ) do.

Then, the voltage storage unit 601, the first node n1, the storage voltage supply unit 602, the second node n2, the resonator unit 606, the blocking unit 620, and the scan bottom switch unit S8 are removed. An energy supply path via it is formed. Accordingly, the voltage stored in the voltage storage unit 601 is supplied to the first electrode through LC resonance by the resonance inductor unit L of the resonance unit 606.

Next, the sustain voltage supply control switch section S3 of the sustain voltage supply section 604 is turned on. Then, the sustain voltage Vs generated by the sustain voltage source is supplied to the first electrode via the third node n, the blocking unit 620, and the scan bottom switch unit S8.

As a result, the first electrode maintains the sustain voltage Vs substantially constant.

Next, the voltage recovery of the voltage recovery unit 603 is performed when both the sustain voltage supply control switch unit S3 of the sustain voltage supply unit 604 and the storage voltage supply control switch unit S1 of the storage voltage supply unit 602 are turned off. The control switch unit S2 is turned on.

Then, the first electrode, the scan bottom switch unit S8, the blocking unit 620, the third node n3, the second node n2, the resonator unit 606, the voltage recovery unit 603, and the first node. (n1), an energy recovery path via the voltage storage unit 601 is formed. Then, the voltage of the first electrode is recovered and stored in the voltage storage unit 601 through LC resonance by the inductor unit 606.

As a result, the voltage of the first electrode may drop from the sustain voltage Vs to the lowest base voltage GND.

In this way, the sustain signal SUS may be supplied to the first electrode in the sustain period.

When the sustain signal SUS is supplied, the discharge cell selected by the address discharge is added with the wall voltage in the discharge cell and the sustain voltage Vs of the sustain signal SUS, and the first electrode when the sustain signal SUS is supplied. A sustain discharge, that is, a display discharge, may be generated between (Y) and the second electrode Z. Here, the manner in which the sustain signal is supplied to the second electrode is substantially the same as the manner in which the sustain signal is supplied to the first electrode.

As described in detail above, in one embodiment of the present invention, the voltage Vsc of the scan bias signal, the voltage Vy of the scan signal Sp, or the ramp down ramp using the voltage of the sustain signal or the data signal. The unit cost can be reduced by generating at least one of the voltages of the signal) and driving using the voltage.

In more detail, in the prior art, the voltage Vs of the sustain signal, the voltage Vsc of the scan bias signal, the voltage of the scan signal Sp or the voltage of the falling ramp signal, and the voltage Vd of the data signal are known. Each voltage generating circuit must be provided.

On the other hand, in one embodiment of the present invention, since the voltage generation circuit for generating the voltage of the scan signal Sp or the voltage of the falling ramp signal can be omitted, the manufacturing cost can be reduced.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the foregoing detailed description, and the meaning and scope of the claims are as follows. And all changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above in detail, the plasma display apparatus according to an embodiment of the present invention generates at least two of the voltages of the plurality of driving signals in common, thereby reducing the number of voltage generating circuits and thus reducing manufacturing costs. It works.

Claims (5)

A plasma display panel including a first electrode and a second electrode parallel to each other, and a third electrode crossing the first electrode and the second electrode; Supply a ramp ramp signal of which voltage gradually falls to the first electrode in the reset period for initialization, and scan signal that falls from the scan bias signal and the scan bias signal to the first electrode in the address period after the reset period. Supplies a data signal to the third electrode corresponding to the scan signal, supplies a sustain signal to at least one of the first electrode and the second electrode in the sustain period after the address period, and A driver for generating a voltage, a voltage of a falling ramp signal, and a voltage of a scan bias signal from a voltage of the sustain signal or a voltage of a data signal Plasma display device comprising a. The method of claim 1, And the voltage of the scan bias signal is generated from a part of the voltage of the scan signal or the voltage of the falling ramp signal. The method of claim 1, The driving unit A scan drive integrated circuit unit including a scan top switch unit and a scan bottom switch unit and connected to the first electrode between the scan top switch unit and the scan bottom switch unit; On in part of the reset period or the address period, the voltage of the falling ramp signal or the voltage of the scan signal is supplied to the first electrode through the scan bottom switch unit, and off in a part of the address period. Scan and reset common switch unit to supply a voltage of a scan bias signal to the first electrode through the scan top switch unit Plasma display device comprising a. The method of claim 3, wherein Between the scan and reset common switch unit and the scan top switch unit includes a portion having a first voltage between the two nodes (Node), between the scan and reset common switch unit and the scan bottom switch unit between the two nodes And a node having a second voltage between the two portions and the portion having the first voltage, wherein the second voltage is substantially equal to the voltage of the scan bias signal. The method of claim 4, wherein And the sum of the first voltage and the second voltage is substantially equal to the voltage of the scan signal or the voltage of the falling ramp signal.

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