KR100800918B1 - Method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor device Download PDF

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KR100800918B1
KR100800918B1 KR1020060135924A KR20060135924A KR100800918B1 KR 100800918 B1 KR100800918 B1 KR 100800918B1 KR 1020060135924 A KR1020060135924 A KR 1020060135924A KR 20060135924 A KR20060135924 A KR 20060135924A KR 100800918 B1 KR100800918 B1 KR 100800918B1
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South Korea
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semiconductor substrate
active region
isolation layer
layer
etching
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KR1020060135924A
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Korean (ko)
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박정호
최호영
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a semiconductor device is provided to improve thickness uniformity of a gate oxide layer by etching an upper edge having a pin shape of an active region in a semiconductor substrate through a CDE(Chemical Dry Etching) method to form a rounded upper edge. A trench(27) is formed on a semiconductor substrate(21) and defines a protrudent active region(A2) having a pin shape by etching an exposed portion of the semiconductor substrate using a patterned pad oxide layer(23) and a pad nitride layer(25) as a mask. An isolation layer(29) is formed in the trench. Using a mask as a portion of the isolation layer overlapped with a photoresist pattern on the pad nitride layer, the isolation layer is etched to form a protrusion portion. The pad nitride layer and the pad oxide layer are wet-etched and eliminated to etch the protrusion of the isolation layer. An upper edge of an active region having a pin shape on the semiconductor substrate is etched to have a rounded shape. A gate oxide is interposed on a surface of the active region on the semiconductor substrate to form a gate in a longitudinal direction as exposing the active region of the semiconductor substrate. Conductive impurity different from the semiconductor substrate is slantly implanted on the expose portion and a lateral side of the active region to an impurity region.

Description

반도체 장치의 제조방법{METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE}METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

도 1a 및 도 1b는 종래 기술에 따른 반도체 장치의 단면도.1A and 1B are cross-sectional views of a semiconductor device according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 반도체 장치의 제조방법을 도시하는 공정도.2A to 2D are process drawings showing a method of manufacturing a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 반도체 기판 23 : 패드 산화막21 semiconductor substrate 23 pad oxide film

25 : 패드 질화막 27 : 트렌치25: pad nitride film 27: trench

29 : 소자 분리막 31 : 돌기부29 device isolation layer 31 projection

33 : 게이트 산화막 35 : 게이트33: gate oxide film 35: gate

A2 : 활성영역 T : 상부 모서리A2: active area T: upper corner

본 발명은 반도체 장치의 제조방법에 관한 것으로서, 특히, 반도체 기판에 돌출되는 핀(fin) 활성영역 상에 트랜지스터를 형성하는 반도체 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which a transistor is formed on a fin active region protruding from a semiconductor substrate.

최근 정보 통신 분야의 급속한 발달과, 컴퓨터와 같은 정보 매체의 대중화에 따라 반도체 장치도 비약적으로 발전하고 있다. 또한, 그 기능적인 면에 있어서 반도체 장치의 소자 고집적화 경향에 따라 기판에 형성되는 개별 소자의 크기(feature size)를 줄이면서 한편으로 소자 성능을 극대화시키기 위해 여러 가지 방법이 연구 개발되고 있다. Recently, with the rapid development of the information and communication field and the popularization of information media such as computers, semiconductor devices are also rapidly developing. In addition, various methods have been researched and developed in order to reduce the feature size of individual devices formed on a substrate and maximize device performance in accordance with the tendency of high integration of semiconductor devices in terms of their functions.

이러한 방법 중에 실리콘 반도체 기술을 기반으로 하여 소자의 집적도를 향상시키고, 그 중에서 전계효과 트랜지스터(Field Effect Transistor : FET)의 디자인 또는 구성으로 이루어지는 CMOS 기술이 가장 경쟁력이 있다. 그러나, 고집적화에 따른 일반적인 전계효과 트랜지스터의 축소(scaling down)는 소자의 성능 또는 신뢰도가 저하되는 결과를 가져온다. Among these methods, CMOS technology, which is based on silicon semiconductor technology, improves the integration of devices, and has a design or configuration of a field effect transistor (FET) is the most competitive. However, scaling down of general field effect transistors due to high integration results in deterioration of device performance or reliability.

따라서, 이러한 전계효과 트랜지스터의 집적도 향상을 용이하도록 하기 위해 트랜지스터의 바디(body)가 수직 구조를 갖도록, 일반적으로 물고기의 등지느러미(dorsal)와 닮은 형상의 핀 전계효과 트랜지스터(fin Field Effect Transistor : 이하 핀 전계효과 트랜지스터의이라 함)가 제안되었다.Therefore, in order to facilitate the integration of such a field effect transistor, a fin field effect transistor having a shape similar to a dorsal of a fish generally has a vertical structure so that the body of the transistor has a vertical structure. A fin field effect transistor) has been proposed.

이러한 핀 전계효과 트랜지스터는 게이트 전극이 반도체 기판 상에 수직으로 돌출된 채널 부분을 감싸도록 형성되어 돌출된 부분의 높이가 채널을 이루어 채널의 폭이 증가되는 것이다.The fin field effect transistor is formed such that a gate electrode surrounds a channel portion protruding vertically on a semiconductor substrate, so that the height of the protruding portion forms a channel, thereby increasing the width of the channel.

도 1a 및 도 1b는 종래 기술에 따른 반도체 장치의 단면도로서, 도 1a는 게이트의 길이 방향으로 절단한 단면도이고, 도 1b는 게이트와 수직하는 방향으로 절단한 단면도이다.1A and 1B are cross-sectional views of a semiconductor device according to the prior art, and FIG. 1A is a cross-sectional view taken along a length direction of a gate, and FIG. 1B is a cross-sectional view taken along a direction perpendicular to the gate.

도시된 바와 같이, 반도체 기판(11)은 트렌치(12)에 의해 한정되는 활성영 역(A1)이 핀(fin) 형상으로 돌출되게 형성된다. 그리고, 트렌치(12) 내에 소자 분리막(13)이 중간 정도까지 채워져 형성된다. 상기 소자 분리막(13)이 채워지는 정도에 따라 채널 폭이 한정된다.As illustrated, the semiconductor substrate 11 is formed such that the active region A1 defined by the trench 12 protrudes into a fin shape. In addition, the isolation layer 13 is filled in the trench 12 to an intermediate level. The channel width is limited depending on the degree of filling the device isolation layer 13.

반도체 기판(11) 상에 게이트 산화막(15)을 개재시켜 게이트(17)가 수직 방향으로 좁은 폭을 가져 양측에 활성영역(A1)을 노출시키면서 길이 방향으로 길게 형성된다. 그리고, 반도체 기판(11) 활성영역(A1)의 노출된 부분에 반도체 기판(11)과 다른 도전형의 불순물이 도핑되어 소오스 및 드레인영역으로 사용되는 불순물영역(19)이 형성된다. 상기에서 불순물영역(19)은 도핑시 활성영역(A1)의 측면에도 도핑되어 수직 방향으로도 형성된다.The gate 17 has a narrow width in the vertical direction with the gate oxide film 15 interposed on the semiconductor substrate 11 and is formed long in the longitudinal direction while exposing the active regions A1 on both sides. An impurity region 19 which is used as a source and a drain region is formed by doping the semiconductor substrate 11 with the conductive type different from the semiconductor substrate 11 in the exposed portion of the active region A1. The impurity region 19 is also doped to the side of the active region A1 when doping, and is also formed in the vertical direction.

그러나, 상술한 종래의 반도체 장치는 핀 구조를 갖는 활성영역의 상부 모리리가 날카롭게 형성되고 소자 분리막을 식각하여 활성영역을 노출시킬 때 하부에서 모우트(moat)가 발생된다.However, in the above-described conventional semiconductor device, the upper part of the active region having a fin structure is sharply formed, and a moat is generated at the bottom when the device isolation layer is etched to expose the active region.

그러므로, 게이트 산화막이 균일한 두께로 형성되지 않고 활성영역의 상부 모서리와 하부에 얇은 두께로 형성되어 소자의 신뢰성이 저하되는 문제점이 있었다.Therefore, there is a problem in that the gate oxide film is not formed to have a uniform thickness but is formed to have a thin thickness at the upper edge and the bottom of the active region, thereby degrading the reliability of the device.

그러므로, 본 발명의 목적은 활성영역에 게이트 산화막을 균일한 두께로 형성하여 소자의 신뢰성을 향상시킬 수 있는 반도체 장치의 제조방법을 제공하는 것이다.Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor device which can improve the reliability of a device by forming a gate oxide film in a uniform thickness in an active region.

전술한 목적을 달성하기 위한 본 발명에 따른 반도체 장치 제조방법은 반도체 기판 상에 형성되고 패터닝된 패드 산화막 및 패드 질화막을 마스크로 사용하여 상기 반도체 기판의 노출된 부분을 식각하여 활성영역을 핀 형상으로 돌출되게 한정하는 트렌치를 형성하는 공정과, 상기 트렌치 내에 소자 분리막을 형성하는 공정과, 상기 패드 질화막 상에 상기 소자 분리막과 중첩되는 포토레지스트 패턴을 마스크로 사용하여 상기 소자 분리막을 상기 포토레지스트 패턴과 중첩된 부분이 잔류되어 돌기부가 되도록 식각하는 공정과, 상기 패드 질화막 및 패드 산화막을 습식 식각하여 제거하면서 상기 소자 분리막의 돌기부를 식각하는 공정과, 상기 반도체 기판의 핀 형상을 갖는 활성영역의 상부 모서리를 둥글게 식각하는 공정과, 상기 반도체 기판의 활성영역 표면 상에 게이트 산화막을 개재시켜 게이트를 수직 방향으로 좁은 폭을 가져 양측에 상기 반도체 기판의 활성영역을 노출시키면서 길이 방향으로 형성하는 공정과, 상기 반도체 기판의 활성영역의 노출된 부분 및 측면에 상기 반도체 기판과 다른 도전형의 불순물을 경사지게 도핑하여 불순물영역을 형성하는 공정을 포함한다.The semiconductor device manufacturing method according to the present invention for achieving the above object is to use a pad oxide film and a pad nitride film formed on the semiconductor substrate as a mask to etch the exposed portion of the semiconductor substrate to form an active region in a pin shape Forming a trench to protrude, forming a device isolation film in the trench, and using the photoresist pattern overlapping the device isolation film on the pad nitride film as a mask, Etching the overlapped portions to form a protrusion, etching the pad nitride layer and the pad oxide layer by wet etching to remove the protrusion of the device isolation layer, and forming an upper edge of the fin-shaped active region of the semiconductor substrate. Etching a round and the bow of the semiconductor substrate Forming a gate in a longitudinal direction by interposing a gate oxide film on the surface of the active region with a narrow width in the vertical direction, exposing the active region of the semiconductor substrate to both sides, and an exposed portion and a side surface of the active region of the semiconductor substrate And doping the semiconductor substrate with an impurity of a different conductivity type from the semiconductor substrate to form an impurity region.

상기 반도체 기판의 핀 형상을 갖는 활성영역의 상부 모서리를 화학적 건식 식각(Chemical Dry Etching : CDE) 방법으로 식각하여 둥글게 형성한다.The upper edge of the fin-shaped active region of the semiconductor substrate is etched by chemical dry etching (CDE) to form a round shape.

이하, 본 발명의 바람직한 실시예는 첨부한 도면을 참조하여 다음과 같이 상세히 설명된다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d를 참조하면, 본 발명에 따른 반도체 장치 제조 방법을 도시하는 공정도가 도시된다.2A to 2D, a process diagram showing a semiconductor device manufacturing method according to the present invention is shown.

먼저, 도 2a를 참조하면, 반도체 기판(21) 상에 패드 산화막(23) 및 패드 질화막(25)을 순차적으로 형성한다. 그리고, 패드 산화막(23) 및 패드 질화막(25)을 포토리쏘그래피 방법으로 패터닝한다.First, referring to FIG. 2A, the pad oxide film 23 and the pad nitride film 25 are sequentially formed on the semiconductor substrate 21. The pad oxide film 23 and the pad nitride film 25 are patterned by a photolithography method.

그 다음 패드 질화막(25)을 마스크로 사용하여 반도체 기판(21)의 노출된 부분을 반응성 이온 식각 등의 방법으로 이방성 식각한다. 그 결과 반도체 기판상에 활성영역(A2)을 한정하는 트렌치(27)가 형성된다. 이때 도시된 바와 같이 반도체 기판(21)의 활성영역(A2)은 핀 형상으로 돌출되게 형성된다.Then, using the pad nitride film 25 as a mask, the exposed portion of the semiconductor substrate 21 is anisotropically etched by a method such as reactive ion etching. As a result, a trench 27 defining an active region A2 is formed on the semiconductor substrate. At this time, as shown, the active region A2 of the semiconductor substrate 21 is formed to protrude in a fin shape.

그리고, 패드 질화막(25) 상에 BPSG 또는 TEOS 등의 산화물을 화학기상증착(CVD) 방법으로 트렌치(27)를 채우도록 증착하고 패드 질화막(25)이 노출되도록 CMP(Chemical Mechanical Polishing)하여 트렌치(27) 내에 소자 분리막(29)을 형성한다.Then, an oxide such as BPSG or TEOS is deposited on the pad nitride film 25 to fill the trench 27 by chemical vapor deposition (CVD), and chemical mechanical polishing (CMP) is performed to expose the pad nitride film 25. An element isolation film 29 is formed in 27.

그 다음 도 2b를 참조하면, 노출된 패드 질화막(25) 상에 소자 분리막(29)과 중첩되게 포토레지스트 패턴(도시되지 않음)을 형성한다. Next, referring to FIG. 2B, a photoresist pattern (not shown) is formed on the exposed pad nitride layer 25 to overlap the device isolation layer 29.

그리고 포토레지스트 패턴을 마스크로서 사용하여 소자 분리막(29)의 노출된 부분을 식각한다. 이 때, 소자 분리막(29)의 포토레지스트 패턴과 중첩된 부분은 식각되지 않고 남아있게 된다. 이렇게 식각되지 않고 남아있는 소자 분리막 부분은 도시된 바와 같이 돌기부(31)와 같은 형상을 갖는다. 그 다음, 포토레지스트 패턴을 제거한다.The exposed portion of the device isolation layer 29 is etched using the photoresist pattern as a mask. At this time, a portion overlapping the photoresist pattern of the device isolation layer 29 is left without being etched. The portion of the device isolation layer that is not etched as described above has the same shape as the protrusion 31 as shown. The photoresist pattern is then removed.

도 2c를 참조하면, 패드 질화막(25) 및 패드 산화막(23)을 습식 식각하여 제거한다. 이때, 소자 분리막(29)도 약간 식각되는데, 돌출부(27)에 의해 반도체 기 판(21)의 활성영역(A2)과 접촉되는 부분의 소자 분리막(29)은 모우트가 형성되지 않는다. Referring to FIG. 2C, the pad nitride layer 25 and the pad oxide layer 23 are removed by wet etching. At this time, the device isolation layer 29 is also slightly etched, and no portion of the device isolation layer 29 in contact with the active region A2 of the semiconductor substrate 21 is formed by the protrusions 27.

그리고, 화학적 건식 식각(Chemical Dry Etching : CDE) 방법으로 반도체 기판(21)의 핀 형상을 갖는 활성영역(A2)의 상부 모서리(T)를 식각하여 둥글게 형성한다.The upper edge T of the active region A2 having the fin shape of the semiconductor substrate 21 is etched and rounded by a chemical dry etching (CDE) method.

그 다음 도 2d를 참조하면, 반도체 기판(21)의 활성영역(A2) 표면 상에 게이트 산화막(33)을 형성한다. 이때, 반도체 기판(21)의 활성영역(A2) 상부 모서리가 완만하게 형성되고 하부의 소자 분리막(29)에 모우트가 형성되지 않으므로 게이트 산화막(33)이 균일한 두께로 형성된다. 그러므로, 게이트 산화막(33)이 균일한 두께로 형성되므로 소자 동작시 전계가 집중되는 것이 방지되므로 소자의 신뢰성이 향상된다.Next, referring to FIG. 2D, the gate oxide layer 33 is formed on the surface of the active region A2 of the semiconductor substrate 21. In this case, since the upper edge of the active region A2 of the semiconductor substrate 21 is formed smoothly and no moat is formed in the lower device isolation layer 29, the gate oxide layer 33 is formed to have a uniform thickness. Therefore, since the gate oxide film 33 is formed to have a uniform thickness, the electric field is prevented from being concentrated during the operation of the device, thereby improving the reliability of the device.

그리고, 소자 분리막(29) 및 게이트 산화막(33) 상에 다결정실리콘을 증착하고 게이트 산화막(33)과 함께 패터닝하여 게이트(35)를 형성한다. 이때, 게이트(35)를 수직 방향으로 좁은 폭을 가져 양측에 반도체 기판(21)의 활성영역(A2)을 노출시키면서 길이 방향으로 길게 형성한다.Then, polysilicon is deposited on the device isolation layer 29 and the gate oxide layer 33 and patterned together with the gate oxide layer 33 to form the gate 35. At this time, the gate 35 has a narrow width in the vertical direction and is formed long in the longitudinal direction while exposing the active region A2 of the semiconductor substrate 21 on both sides.

그리고, 반도체 기판(21)의 활성영역(A2)의 노출된 부분에 반도체 기판(21)과 다른 도전형의 불순물을 경사지게 이온주입하고 활성화하여 소오스 및 드레인영역으로 사용되는 불순물영역(도시되지 않음)을 형성한다. 이때, 불순물영역은 반도체 기판(21)의 활성영역(A2)의 노출된 부분뿐만 아니라 노출된 측면에도 형성되므로 채널의 폭이 증가된다.An impurity region (not shown) used as a source and a drain region by injecting and activating an ion of an impurity different from that of the semiconductor substrate 21 into the exposed portion of the active region A2 of the semiconductor substrate 21 in an inclined manner. To form. In this case, the impurity region is formed not only in the exposed portion of the active region A2 of the semiconductor substrate 21 but also on the exposed side surface, thereby increasing the width of the channel.

전술한 바와 같이 본 발명은 소자 분리막을 반도체 기판의 핀 형상의 활성영역의 상부 모서리와 접촉되는 부분에 돌출부를 형성하는 것에 의해 패드 산화막 및 패드 질화막을 제거할 때 반도체 기판의 활성영역과 접촉되는 부분의 소자 분리막에 모우트가 형성되지 않도록 하며, 또한, 반도체 기판의 핀 형상의 활성영역의 상부 모서리를 CDE 방법으로 식각하여 둥글게 형성한다.As described above, according to the present invention, when the pad oxide film and the pad nitride film are removed by forming a protrusion at a portion in which the device isolation layer is in contact with the upper edge of the fin-shaped active region of the semiconductor substrate, the contact portion is in contact with the active region of the semiconductor substrate. The moiety is not formed in the device isolation layer of the semiconductor substrate, and the upper edge of the fin-shaped active region of the semiconductor substrate is etched and rounded by the CDE method.

따라서, 본 발명은 게이트 산화막이 균일한 두께로 형성되어 소자의 신뢰성을 향상시킬 수 있는 장점이 있다.Therefore, the present invention has the advantage that the gate oxide film is formed to have a uniform thickness to improve the reliability of the device.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

Claims (2)

반도체 기판 상에 형성되고 패터닝된 패드 산화막 및 패드 질화막을 마스크로 사용하여 상기 반도체 기판의 노출된 부분을 식각하여 활성영역을 핀 형상으로 돌출되게 한정하는 트렌치를 형성하는 공정과,Using a pad oxide film and a pad nitride film formed on the semiconductor substrate as a mask to etch an exposed portion of the semiconductor substrate to form a trench defining an active region to protrude in a pin shape; 상기 트렌치 내에 소자 분리막을 형성하는 공정과,Forming an isolation layer in the trench; 상기 패드 질화막 상에 상기 소자 분리막과 중첩되는 포토레지스트 패턴을 마스크로 사용하여 상기 소자 분리막을 상기 포토레지스트 패턴과 중첩된 부분이 잔류되어 돌기부가 되도록 식각하는 공정과,Using the photoresist pattern overlapping the device isolation layer as a mask on the pad nitride layer to etch the device isolation layer such that a portion overlapping with the photoresist pattern remains to form a protrusion; 상기 패드 질화막 및 패드 산화막을 습식 식각하여 제거하면서 상기 소자 분리막의 돌기부를 식각하는 공정과,Etching the pad nitride layer and the pad oxide layer by wet etching to remove the protrusions of the device isolation layer; 상기 반도체 기판의 핀 형상을 갖는 활성영역의 상부 모서리를 둥글게 식각하는 공정과,Etching an upper edge of the active region having a fin shape of the semiconductor substrate roundly; 상기 반도체 기판의 활성영역 표면 상에 게이트 산화막을 개재시켜 게이트를 수직 방향으로 좁은 폭을 가져 양측에 상기 반도체 기판의 활성영역을 노출시키면서 길이 방향으로 형성하는 공정과,Forming a gate in a longitudinal direction by interposing a gate oxide film on a surface of an active region of the semiconductor substrate with a narrow width in a vertical direction and exposing the active region of the semiconductor substrate to both sides; 상기 반도체 기판의 활성영역의 노출된 부분 및 측면에 상기 반도체 기판과 다른 도전형의 불순물을 경사지게 도핑하여 불순물영역을 형성하는 공정을 포함하는 반도체 장치의 제조방법.And impurity doping the exposed portions and side surfaces of the active region of the semiconductor substrate with an impurity region different from that of the semiconductor substrate to form an impurity region. 청구항 1에 있어서,The method according to claim 1, 상기 반도체 기판의 핀 형상을 갖는 활성영역의 상부 모서리를 화학적 건식 식각(CDE) 방법으로 식각하여 둥글게 형성하는 반도체 장치의 제조방법.And forming a rounded upper edge of the fin-shaped active region of the semiconductor substrate by chemical dry etching (CDE).
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499954B1 (en) * 2003-08-30 2005-07-05 동부아남반도체 주식회사 Method for manufacturing Field-Effect-Transistor of semiconductor device
JP2006079329A (en) * 2004-09-09 2006-03-23 Nec Corp Charging method and charging system and program for charging
KR100613338B1 (en) * 2004-05-18 2006-08-22 동부일렉트로닉스 주식회사 MOS transistor and fabrication method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499954B1 (en) * 2003-08-30 2005-07-05 동부아남반도체 주식회사 Method for manufacturing Field-Effect-Transistor of semiconductor device
KR100613338B1 (en) * 2004-05-18 2006-08-22 동부일렉트로닉스 주식회사 MOS transistor and fabrication method thereof
JP2006079329A (en) * 2004-09-09 2006-03-23 Nec Corp Charging method and charging system and program for charging

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
공개공보 2006-79329
특허 10-0499954
특허 10-0613338

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