CN115775830B - Shielding grid power device and preparation method thereof - Google Patents
Shielding grid power device and preparation method thereof Download PDFInfo
- Publication number
- CN115775830B CN115775830B CN202211505585.3A CN202211505585A CN115775830B CN 115775830 B CN115775830 B CN 115775830B CN 202211505585 A CN202211505585 A CN 202211505585A CN 115775830 B CN115775830 B CN 115775830B
- Authority
- CN
- China
- Prior art keywords
- gate
- shielding
- layer
- material layer
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000003989 dielectric material Substances 0.000 claims abstract description 73
- 239000004065 semiconductor Substances 0.000 claims abstract description 62
- 239000000463 material Substances 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000007772 electrode material Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 50
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 238000001312 dry etching Methods 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000004891 communication Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 250
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 210000000746 body region Anatomy 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to a shielded gate power device and a preparation method thereof. The preparation method of the shielded gate power device comprises the following steps: providing a semiconductor layer; forming a trench in the semiconductor layer; forming a shielding gate dielectric material layer in the groove, wherein the upper surface of the shielding gate dielectric material layer is lower than the top surface of the groove; forming a gate dielectric layer at least on the exposed side wall of the groove; forming a gate material layer in the trench; etching the grid electrode material layer and the shielding grid dielectric material layer to form a grid electrode, a shielding grid dielectric layer and a shielding grid groove; forming a gate source dielectric layer on the exposed side wall of the gate; and forming a shielding grid in the shielding grid groove. According to the preparation method, the bottom angle of the grid electrode adjacent to the shielding grid electrode is not sharp, the thickness uniformity of the grid source dielectric layer between the grid electrode and the shielding grid electrode is good, the withstand voltage of the grid source dielectric layer can be improved, and the grid leakage is effectively improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate power device and a preparation method thereof.
Background
In a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device, since a shielded gate trench (Shielded Gate Transistor, SGT) MOSFET is used as a relatively advanced power device, the MOSFET has advantages of lower on-resistance and faster switching speed compared to a conventional trench MOSFET, and is widely used in many fields.
The structure of the shielded gate trench MOSFET is shown in FIG. 1, and may specifically include: semiconductor layer 10, trench 11, shield gate dielectric layer 12, shield gate 13, gate trench 14, gate 15, and gate dielectric layer 16. Because the gate trench 14 is formed by etching back the shield gate dielectric layer 12 after the shield gate 13 is formed, the bottom angle of the bottom of the gate trench 14 adjacent to the shield gate 13 is sharp, and when the gate dielectric layer 16 is formed, the thickness of the gate dielectric layer 16 at the sharp angle is thinner, which is generally about 20% thinner than the thickness of the gate dielectric layer 16 at other positions in the gate trench 14, so that the thickness of the gate dielectric layer 16 in the gate trench 14 is uneven; the sharp angle can generate a strong electric field due to the point discharge, and the thickness of the grid dielectric layer 16 at the sharp angle is thinner, so that the voltage withstand of the grid dielectric layer 16 at the sharp angle is insufficient, and grid leakage is caused easily.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a shielded gate power device and a method for manufacturing the same, which aims to solve the problem of gate leakage caused by the fact that the gate dielectric layer at the sharp corner is thinner due to the sharp corner of the bottom corner of the gate trench adjacent to the shielded gate in the existing shielded gate power device, and the voltage withstand of the gate dielectric layer at the sharp corner is insufficient.
In a first aspect, the present invention provides a method for manufacturing a shielded gate power device, including:
providing a semiconductor layer;
forming a groove in the semiconductor layer;
forming a shielding gate dielectric material layer in the groove, wherein the upper surface of the shielding gate dielectric material layer is lower than the top surface of the groove;
forming a gate dielectric layer on at least the exposed side wall of the groove;
forming a gate material layer in the trench;
etching the grid electrode material layer and the shielding grid dielectric material layer to form a grid electrode, a shielding grid dielectric layer and a shielding grid groove;
forming a gate source dielectric layer on the exposed side wall of the gate;
and forming a shielding grid in the shielding grid groove.
In the preparation method of the shielded gate power device, after a shielded gate dielectric material layer and a gate material layer are formed in a groove, the shielded gate dielectric material layer and the gate material layer are etched to form a gate, a shielded gate dielectric layer and a shielded gate groove, then a gate source dielectric layer is formed on the exposed side wall of the gate, and finally a shielded gate is formed in the shielded gate groove; by the preparation method, the bottom angle of the grid electrode adjacent to the shielding grid electrode is not sharp, the thickness uniformity of the grid source dielectric layer between the grid electrode and the shielding grid electrode is good, the withstand voltage of the grid source dielectric layer can be improved, and the grid leakage is effectively improved.
In one embodiment, forming a shielding gate dielectric material layer in the trench includes:
forming a first shielding gate dielectric material layer on the side wall of the groove, the bottom of the groove and the upper surface of the semiconductor layer;
forming a second shielding gate dielectric material layer on the surface of the first shielding gate dielectric material layer, wherein the second shielding gate dielectric material layer fills the groove and extends to the semiconductor layer;
and removing the first shielding grid dielectric material layer positioned on the semiconductor layer, the second shielding grid dielectric material layer positioned on the semiconductor layer, part of the first shielding grid dielectric material layer positioned in the groove and part of the second shielding grid dielectric material layer to obtain a first shielding grid dielectric layer and a third shielding grid dielectric material layer, wherein the first shielding grid dielectric layer and the third shielding grid dielectric material layer jointly form the shielding grid dielectric material layer.
In one embodiment, forming a gate dielectric layer on at least the exposed sidewall of the trench includes:
and forming the gate dielectric layer on the exposed side wall of the groove and the upper surface of the semiconductor layer by adopting a thermal oxidation process.
In one embodiment, forming a gate material layer in the trench includes:
forming a gate material layer in the trench and on the semiconductor layer;
the gate material layer on the semiconductor layer is removed.
In one embodiment, etching the gate material layer and the shielding gate dielectric material layer to form a gate, a shielding gate dielectric layer and a shielding gate trench includes:
etching the gate material layer to form the gate and the first shielding gate trench located within the gate;
etching the shielding gate dielectric material layer based on the first shielding gate trench to obtain the shielding gate dielectric layer and a second shielding gate trench in the shielding gate dielectric layer; the second shield gate trench is in communication with the first shield gate trench and forms the shield gate trench together with the first shield gate trench.
In one embodiment, the width of the second shield gate trench is greater than the width of the first shield gate trench.
In one embodiment, the gate material layer is etched by a dry etching process to form the gate and the first shielding gate trench located within the gate; and sequentially performing dry etching and wet etching on the shielding gate dielectric material layer based on the first shielding gate trench to obtain the shielding gate dielectric layer and a second shielding gate trench in the shielding gate dielectric layer.
In one embodiment, the gate source dielectric layer is formed on the exposed sidewall of the gate by a thermal oxidation process.
In one embodiment, forming a shield gate in the shield gate trench includes:
forming a shield gate material layer in the shield gate trench and on the semiconductor layer;
and removing the shielding grid electrode material layer positioned on the semiconductor layer, wherein the shielding grid electrode material layer reserved in the shielding grid electrode groove is the shielding grid electrode.
In a second aspect, the present invention also provides a shielded gate power device, which is prepared by using the preparation method of the shielded gate power device in the first aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present invention, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic cross-sectional structure of a prior art shielded gate trench MOSFET;
fig. 2 is a flowchart of a method for manufacturing a shielded gate power device according to an embodiment;
fig. 3 is a schematic cross-sectional structure of the structure obtained in step S10 in the method for manufacturing a shielded gate power device according to an embodiment;
fig. 4 to fig. 5 are schematic cross-sectional structural diagrams of the structure obtained in step S20 in the method for manufacturing a shielded gate power device according to an embodiment;
fig. 6 to 7 are schematic cross-sectional structural diagrams of the structure obtained in step S30 in the method for manufacturing a shielded gate power device according to an embodiment;
fig. 8 is a schematic cross-sectional structure of the structure obtained in step S40 in the method for manufacturing a shielded gate power device according to an embodiment;
fig. 9 is a schematic cross-sectional structure of the structure obtained in step S50 in the method for manufacturing a shielded gate power device according to an embodiment;
fig. 10 is a schematic cross-sectional structure of the structure obtained in step S60 in the method for manufacturing a shielded gate power device according to an embodiment;
fig. 11 is a schematic cross-sectional structure of the structure obtained in step S70 in the method for manufacturing a shielded gate power device according to an embodiment;
fig. 12 is a schematic cross-sectional structure of the structure obtained in step S80 in the method for manufacturing a shielded gate power device according to an embodiment.
Reference numerals illustrate:
10. a semiconductor layer; 11. a groove; 12. a shielding gate dielectric layer; 13. a shield gate; 14. a gate trench; 15. a gate; 16. a gate dielectric layer; 20. a semiconductor layer; 21. a groove; 211. a mask layer; 212. patterning the mask layer; 22. a shielding gate dielectric layer; 221. a shield gate dielectric material layer; 2211. a first shield gate dielectric material layer; 2212. a second shield gate dielectric material layer; 2213. a third shield gate dielectric material layer; 222. a first shielding gate dielectric layer; 223. a second shielding gate dielectric layer; 23. a gate dielectric layer; 24. a gate; 241. a gate material layer; 25. a shield gate trench; 251. a first shield gate trench; 252. a second shield gate trench; 26. a gate source dielectric layer; 27. the gate is shielded.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
In one embodiment, referring to fig. 2, the present invention provides a method for manufacturing a shielded gate power device, where the method for manufacturing a shielded gate power device may include the following steps:
s10: providing a semiconductor layer;
s20: forming a groove in the semiconductor layer;
s30: forming a shielding gate dielectric material layer in the groove, wherein the upper surface of the shielding gate dielectric material layer is lower than the top surface of the groove;
s40: forming a gate dielectric layer on at least the exposed side wall of the groove;
s50: forming a gate material layer in the trench;
s60: etching the grid electrode material layer and the shielding grid dielectric material layer to form a grid electrode, a shielding grid dielectric layer and a shielding grid groove;
s70: forming a gate source dielectric layer on the exposed side wall of the gate;
s80: and forming a shielding grid in the shielding grid groove.
In the preparation method of the shielded gate power device, after the shielded gate dielectric material layer and the gate material layer are formed in the groove, the grid electrode, the shielded gate dielectric layer and the shielded gate groove are formed by etching the shielded gate dielectric material layer and the gate material layer, then the gate source dielectric layer is formed on the exposed side wall of the grid electrode, and finally the shielded gate is formed in the shielded gate groove; by the preparation method, the bottom angle formed by the grid electrode and the shielding grid electrode is not sharp, the thickness uniformity of the grid source dielectric layer between the grid electrode and the shielding grid electrode is good, the voltage withstand of the grid source dielectric layer can be improved, and the grid leakage is effectively improved.
In step S10, referring to step S10 in fig. 2 and fig. 3, a semiconductor layer 20 is provided.
By way of example, the semiconductor layer 20 may be at least one doped layer, such as to be at least one epitaxially doped layer; at this time, the semiconductor layer 20 may be formed on a substrate (not shown). Of course, in other examples, the semiconductor layer 20 may also be a doped substrate. Note that, the doping concentration range in the semiconductor layer 20 may be set according to the actual situation, which is not limited herein.
By way of example, the material of the semiconductor layer 20 may include, but is not limited to, silicon germanium, silicon carbide, gallium nitride, or other suitable semiconductor materials, and the like.
In step S20, referring to step S20 in fig. 2 and fig. 4 to 5, a trench 21 is formed in the semiconductor layer 20.
As an example, step S20 may include the steps of:
s201: forming a mask layer 211 on the upper surface of the semiconductor layer 20, as shown in fig. 4;
s202: patterning the mask layer 211 to obtain a patterned mask layer 212, wherein the patterned mask layer 212 has an opening pattern (not shown) therein, and the opening pattern defines the shape and the position of the trench 21;
s202: etching the semiconductor layer 20 based on the patterned mask layer 212 to form the trench 21 in the semiconductor layer 20, as shown in fig. 5;
s203: the patterned mask layer 212 is removed.
In an alternative example, step S202 may include the steps of:
s2021: forming a photoresist layer (not shown) on the upper surface of the mask layer 211;
s2022: exposing and developing the photoresist layer to form a patterned photoresist layer;
s2023: etching the mask layer 211 based on the patterned photoresist layer to obtain the patterned mask layer 212;
s2024: and removing the patterned photoresist layer.
As an example, in step S201, the mask layer 211 may be formed in a single layer structure, and in this case, the mask layer 211 may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer; in step S201, the mask layer 211 may be formed in a multi-layer structure, and in this case, the mask layer 211 may include at least two layers of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In this embodiment, the mask layer 211 may be an oxide layer.
As an example step S201, the mask layer 211 may be formed using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
As an example, the depth of the trench 21 is smaller than the thickness of the semiconductor layer 20.
As an example, the longitudinal cross-sectional shape of the groove 21 may be, but not limited to, U-shaped as shown in fig. 5, and the longitudinal cross-sectional shape of the groove 21 may also be inverted trapezoid, rectangle, or the like.
As an example, the number of the grooves 21 formed in step S20 may be set according to actual needs, and only two grooves 21 are taken as an example in fig. 5, and in other examples, the number of the grooves 21 is not limited to the number in fig. 5, but may be one, three, four, five, six or more, or the like.
In step S30, referring to step S30 in fig. 2 and fig. 6 to 7, a shielding gate dielectric material layer 221 is formed in the trench 21, and an upper surface of the shielding gate dielectric material layer 221 is lower than a top surface of the trench 21.
As an example, step S30 may include the steps of:
s301: forming a first shielding gate dielectric material layer 2211 on the side wall of the trench 21, the bottom of the trench 21 and the upper surface of the semiconductor layer 20;
s302: forming a second shielding gate dielectric material layer 2212 on the surface of the first shielding gate dielectric material layer 2211, where the second shielding gate dielectric material layer 2212 fills the trench 21 and extends onto the semiconductor layer 20, as shown in fig. 6;
s303: the first shielding gate dielectric material layer 2211 located on the semiconductor layer 20, the second shielding gate dielectric material layer 2212 located on the semiconductor layer 20, a part of the first shielding gate dielectric material layer 2211 and a part of the second shielding gate dielectric material layer 2212 located in the trench 21 are removed to obtain a first shielding gate dielectric layer 222 and a third shielding gate dielectric material layer 2213, and the first shielding gate dielectric layer 222 and the third shielding gate dielectric material layer 2213 together form the shielding gate dielectric material layer 221.
As an example, in step S301, an oxide layer may be formed as the first shielding gate dielectric material layer 2211 on the sidewall of the trench 21, the bottom of the trench 21 and the upper surface of the semiconductor layer 20 by using a thermal oxidation process.
As an example, in step S302, an oxide layer may be deposited as the second shield gate dielectric material layer 2212 using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
As an example, in step S303, the first shielding gate dielectric material layer 2211 located on the semiconductor layer 20 and the second shielding gate dielectric material layer 2212 located on the semiconductor layer 20 may be removed by using, but not limited to, a chemical mechanical polishing process or an etching process, and then a part of the first shielding gate dielectric material layer 2211 and a part of the second shielding gate dielectric material layer 2212 located in the trench 21 may be removed by using, but not limited to, a dry etching process, so as to obtain the first shielding gate dielectric layer 222 and the third shielding gate dielectric material layer 2213.
In step S40, referring to step S40 in fig. 2 and fig. 8, at least the exposed sidewall of the trench 21 forms the gate dielectric layer 23.
As an example, but not limited to, a thermal oxidation process may be used to form an oxide layer on the exposed sidewalls of the trench 21 and the upper surface of the semiconductor layer 20 as the gate dielectric layer 23. The thickness of the gate dielectric layer 23 may be set according to actual needs, and is not limited herein.
In step S50, referring to step S50 in fig. 2 and fig. 9, a gate material layer 241 is formed in the trench 21.
As an example, step S50 may include the steps of:
s501: forming the gate material layer 241 in the trench 21 and on the semiconductor layer 20; specifically, the gate material layer 241 may be formed in the trench 21 and on the semiconductor layer 20 by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like;
s502: removing the gate material layer 241 on the semiconductor layer 20; specifically, the gate material layer 241 on the semiconductor layer 20 may be removed using, but not limited to, a chemical mechanical polishing process or an etching process.
As an example, the gate material layer 241 may include, but is not limited to, a polysilicon layer.
In step S60, referring to step S60 in fig. 2 and fig. 10, the gate material layer 241 and the shield gate dielectric material layer 221 are etched to form the gate 24, the shield gate dielectric layer 22 and the shield gate trench 25.
As an example, step S60 may include the steps of:
s601: etching the gate material layer 241 to form the gate 24 and the first shield gate trench 251 within the gate 24;
s602: etching the shielding gate dielectric material layer 221 based on the first shielding gate trench 251 to obtain the shielding gate dielectric layer 22 and a second shielding gate trench 252 located in the shielding gate dielectric layer 22; the second shield gate trench 252 communicates with the first shield gate trench 251 and constitutes the shield gate trench 25 together with the first shield gate trench 251.
As an example, in step S601, the gate material layer 241 may be etched using a dry etching process to form the gate electrode 24 and the first shield gate trench 251 located within the gate electrode 24. Specifically, in the dry etching process, the dry etching gas used should have a larger removal rate for the gate material layer 241, but a smaller etching removal rate for the gate dielectric layer 23 and the second shielding gate dielectric layer 223, so as to ensure that the gate dielectric layer 23 may be used as an etching barrier layer and the second shielding gate dielectric layer 223 may be used as an etching stop layer in the process of etching the gate material layer 241.
As an example, in step S602, dry etching and wet etching may be sequentially performed on the shielding gate dielectric material layer 221 based on the first shielding gate trench 251, so as to obtain the shielding gate dielectric layer 22 and the second shielding gate trench 252 located in the shielding gate dielectric layer 22. It should be noted that the wet etching solution used in the wet etching process should have a larger etching removal rate for the second shield gate dielectric layer 223 and a smaller etching removal rate for the gate 24, so as to ensure that the gate 24 is hardly etched during the process of etching the second shield gate dielectric layer 223 to form the second shield gate trench 252.
As an example, the width of the second shielding gate trench 252 may be greater than the width of the first shielding gate trench 251. Of course, in other examples, the width of the second shielding gate trench 252 may be smaller than or equal to the width of the first shielding gate trench 251.
In step S70, referring to step S70 in fig. 2 and fig. 11, a gate source dielectric layer 26 is formed on the exposed sidewall of the gate electrode 25.
As an example, but not limited to, a thermal oxidation process may be used to form an oxide layer on the exposed sidewall of the gate electrode 25 as the gate source dielectric layer 26. The thickness of the gate-source dielectric layer 26 may be set according to practical needs, and is not limited herein. Because the gate-source dielectric layer 26 is formed by a thermal oxidation process after the shielding gate trench 25 is formed, sharp corners do not exist in the formed gate-source dielectric layer 26, and the forming rate of the gate-source dielectric layer 26 is approximately the same all over the exposed side wall of the gate 25, so that the formed gate-source dielectric layer 25 can be ensured to have better thickness uniformity.
In step S80, referring to step S80 in fig. 2 and fig. 12, a shield gate 27 is formed in the shield gate trench 25.
As an example step S80 may include the steps of:
s801: forming a shield gate material layer (not shown) within the shield gate trench 25 and on the semiconductor layer 20; specifically, the shield gate material layer may be formed in the shield gate trench 25 and on the semiconductor layer 20 using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;
s802: removing the shielding gate material layer on the semiconductor layer 20, wherein the shielding gate material layer remaining in the shielding gate trench 20 is the shielding gate 27; specifically, the shielding gate material layer on the semiconductor layer 20 may be removed using, but not limited to, a chemical mechanical polishing process or an etching process.
As an example, the shield gate 27 may include, but is not limited to, a polysilicon shield gate.
As an example, step S80 may further include the following steps:
forming body regions (not shown) in the semiconductor layer 20, the body regions being located on opposite sides of the trench 21;
forming a source (not shown) in the body region;
forming a gate electrode (not shown), a source electrode (not shown), and a drain electrode (not shown), the gate electrode being electrically connected to the gate 24; the source electrode penetrates through the source electrode and extends into the body region; the drain electrode is electrically connected to the lower surface of the semiconductor layer 10. Specifically, the drain electrode may be located on the lower surface of the semiconductor layer 10.
In another embodiment, please continue to refer to fig. 2 to 12, the present invention further provides a shielded gate power device, which may be manufactured by using the manufacturing method of the shielded gate power device described in the previous embodiment. The specific structure of the shielded gate power device may be referred to fig. 2 to 12 and the related text descriptions, which will not be further described herein.
It should be understood that, although the steps in the flowcharts related to the above embodiments are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (9)
1. The preparation method of the shielded gate power device is characterized by comprising the following steps:
providing a semiconductor layer;
forming a groove in the semiconductor layer;
forming a shielding gate dielectric material layer in the groove, wherein the upper surface of the shielding gate dielectric material layer is lower than the top surface of the groove;
forming a gate dielectric layer on at least the exposed side wall of the groove;
forming a gate material layer in the trench;
etching the grid electrode material layer and the shielding grid dielectric material layer to form a grid electrode, a shielding grid dielectric layer and a shielding grid groove;
forming a gate source dielectric layer on the exposed side wall of the gate;
forming a shield gate in the shield gate trench, comprising: forming a shield gate material layer in the shield gate trench and on the semiconductor layer; and removing the shielding grid electrode material layer positioned on the semiconductor layer, wherein the shielding grid electrode material layer reserved in the shielding grid electrode groove is the shielding grid electrode.
2. The method for manufacturing the shielded gate power device according to claim 1, wherein forming the shielded gate dielectric material layer in the trench comprises:
forming a first shielding gate dielectric material layer on the side wall of the groove, the bottom of the groove and the upper surface of the semiconductor layer;
forming a second shielding gate dielectric material layer on the surface of the first shielding gate dielectric material layer, wherein the second shielding gate dielectric material layer fills the groove and extends to the semiconductor layer;
and removing the first shielding grid dielectric material layer positioned on the semiconductor layer, the second shielding grid dielectric material layer positioned on the semiconductor layer, part of the first shielding grid dielectric material layer positioned in the groove and part of the second shielding grid dielectric material layer to obtain a first shielding grid dielectric layer and a third shielding grid dielectric material layer, wherein the first shielding grid dielectric layer and the third shielding grid dielectric material layer jointly form the shielding grid dielectric material layer.
3. The method for manufacturing the shielded gate power device according to claim 1, wherein forming a gate dielectric layer on at least the exposed sidewalls of the trench comprises:
and forming the gate dielectric layer on the exposed side wall of the groove and the upper surface of the semiconductor layer by adopting a thermal oxidation process.
4. The method of claim 1, wherein forming a gate material layer in the trench comprises:
forming a gate material layer in the trench and on the semiconductor layer;
the gate material layer on the semiconductor layer is removed.
5. The method of claim 1, wherein etching the gate material layer and the shield gate dielectric material layer to form a gate, a shield gate dielectric layer, and a shield gate trench comprises:
etching the gate material layer to form the gate and a first shielding gate trench in the gate;
etching the shielding gate dielectric material layer based on the first shielding gate trench to obtain the shielding gate dielectric layer and a second shielding gate trench in the shielding gate dielectric layer; the second shield gate trench is in communication with the first shield gate trench and forms the shield gate trench together with the first shield gate trench.
6. The method of claim 5, wherein the second shield gate trench has a width greater than a width of the first shield gate trench.
7. The method of manufacturing a shielded gate power device of claim 6, wherein the gate material layer is etched using a dry etching process to form the gate and the first shielded gate trench within the gate;
and sequentially performing dry etching and wet etching on the shielding gate dielectric material layer based on the first shielding gate trench to obtain the shielding gate dielectric layer and a second shielding gate trench in the shielding gate dielectric layer.
8. The method for manufacturing the shielded gate power device according to claim 1, wherein the gate source dielectric layer is formed on the exposed side wall of the gate electrode by a thermal oxidation process.
9. A shielded gate power device, characterized in that the shielded gate power device is manufactured by the manufacturing method of the shielded gate power device according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211505585.3A CN115775830B (en) | 2022-11-29 | 2022-11-29 | Shielding grid power device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211505585.3A CN115775830B (en) | 2022-11-29 | 2022-11-29 | Shielding grid power device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115775830A CN115775830A (en) | 2023-03-10 |
| CN115775830B true CN115775830B (en) | 2023-07-21 |
Family
ID=85390427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211505585.3A Active CN115775830B (en) | 2022-11-29 | 2022-11-29 | Shielding grid power device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115775830B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105551964A (en) * | 2015-12-25 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for MOSFET adopting separated trench side gate structure with shield gate |
| CN105870022A (en) * | 2016-05-31 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of shielding gate groove MOSFET |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7129536B2 (en) * | 2004-09-02 | 2006-10-31 | Silicon Storage Technology, Inc. | Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same |
| US8252647B2 (en) * | 2009-08-31 | 2012-08-28 | Alpha & Omega Semiconductor Incorporated | Fabrication of trench DMOS device having thick bottom shielding oxide |
| US7977193B1 (en) * | 2010-08-20 | 2011-07-12 | Monolithic Power Systems, Inc. | Trench-gate MOSFET with capacitively depleted drift region |
| DE102015103072B4 (en) * | 2015-03-03 | 2021-08-12 | Infineon Technologies Ag | SEMI-CONDUCTOR DEVICE WITH A DITCH STRUCTURE INCLUDING A GATE ELECTRODE AND A CONTACT STRUCTURE FOR A DIODE AREA |
| CN106057674B (en) * | 2016-05-31 | 2019-04-09 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of shield grid groove MOSFET |
| CN109216174B (en) * | 2017-07-03 | 2021-04-13 | 无锡华润上华科技有限公司 | Split gate structure of semiconductor device and manufacturing method thereof |
| CN112271134B (en) * | 2020-10-20 | 2021-10-22 | 苏州东微半导体股份有限公司 | Method for manufacturing semiconductor power device |
| CN112838000A (en) * | 2021-01-07 | 2021-05-25 | 深圳市谷峰电子有限公司 | Process method for manufacturing upper and lower structure SGT |
| CN113035945A (en) * | 2021-03-15 | 2021-06-25 | 海速芯(无锡)科技有限公司 | Novel field effect device structure for improving figure of merit and manufacturing method thereof |
| CN114005756A (en) * | 2021-10-29 | 2022-02-01 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of shielded gate trench power device |
| CN115148670B (en) * | 2022-07-05 | 2023-06-13 | 上海功成半导体科技有限公司 | Shielded gate trench MOSFET structure and preparation method thereof |
-
2022
- 2022-11-29 CN CN202211505585.3A patent/CN115775830B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105551964A (en) * | 2015-12-25 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for MOSFET adopting separated trench side gate structure with shield gate |
| CN105870022A (en) * | 2016-05-31 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of shielding gate groove MOSFET |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115775830A (en) | 2023-03-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR950024326A (en) | Semiconductor device having trench structure and manufacturing method thereof | |
| CN108155237B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| TWI686903B (en) | Gate structure of split-gate mosfet and manufacturing method thereof | |
| CN118173606B (en) | High-voltage MOS transistor and preparation method thereof | |
| JPH09213951A (en) | Semiconductor device | |
| CN113990917B (en) | Transistor with embedded isolation layer in bulk substrate | |
| CN115799307B (en) | Shielding grid power device and preparation method thereof | |
| CN115775830B (en) | Shielding grid power device and preparation method thereof | |
| US11682725B2 (en) | Semiconductor device with isolation layer | |
| CN107527857B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| CN113903808B (en) | Semiconductor structure and forming method thereof | |
| US7507630B2 (en) | Method of fabricating a semiconductor device | |
| CN110957349B (en) | Semiconductor device and method for manufacturing the same | |
| CN115763552B (en) | Shielding grid power device and preparation method thereof | |
| US20200243657A1 (en) | Multi-trench MOSFET and method for fabricating the same | |
| CN115938945B (en) | Shielding grid power device and preparation method thereof | |
| CN115775823B (en) | Shielding grid power device and preparation method thereof | |
| KR101128915B1 (en) | Method for forming semiconductor device | |
| WO2024012430A1 (en) | Trench-type double-diffused metal oxide semiconductor device and manufacturing method therefor | |
| CN116435336B (en) | Groove type MOSFET electric field protection structure and preparation method | |
| CN112117190B (en) | Semiconductor structure and forming method thereof | |
| US20230317815A1 (en) | Laterally diffused metal-oxide semiconductor with gate contact | |
| Park et al. | Novel process techniques for fabricating high density trench MOSFETs with self-aligned N/sup+//P/sup+/source formed on the trench side wall | |
| KR20080069427A (en) | Transistor of semiconductor device and method for manufacturing the same | |
| CN117476463A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |