CN112838000A - Process method for manufacturing upper and lower structure SGT - Google Patents
Process method for manufacturing upper and lower structure SGT Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 104
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 60
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 75
- 238000005530 etching Methods 0.000 claims abstract description 65
- 229920005591 polysilicon Polymers 0.000 claims abstract description 43
- 238000000151 deposition Methods 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 230000000873 masking effect Effects 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 37
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 4
- 230000001376 precipitating effect Effects 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 13
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 241001528553 Malus asiatica Species 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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Abstract
The invention relates to a process method for manufacturing an upper structure SGT and a lower structure SGT, which comprises the following manufacturing steps: firstly, etching a first groove on a semiconductor substrate, firstly etching an upper half-depth groove on the semiconductor substrate, growing a gate oxide layer, accumulating and depositing a hard masking layer, then etching a lower half-depth groove, depositing and etching back to form a lower gate oxide layer and a bottom gate oxide layer, filling polysilicon and etching back to form bottom gate polysilicon which is back to the hard masking layer; and secondly, etching a second groove, depositing a gate oxide layer on the hard masking layer on the side wall of the upper half-depth groove formed in the first step and the bottom grid polycrystalline silicon, filling the polycrystalline silicon and etching back to form upper source polycrystalline silicon. The method has the advantages that the lengths of the channels of the gate oxide layers are the same, the gate-level polycrystalline silicon is effectively prevented from being oxidized, and the electric field at the bottom of the groove is easy to be exhausted.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductors, in particular to a process method for manufacturing an upper structure SGT and a lower structure SGT.
[ background of the invention ]
A Shielded Gate MOSFET (abbreviated SGT-MOSFET) power device is an improved Trench power MOSFET based on a conventional Trench MOSFET (U-MOSFET). Compared with the traditional U-MOSFET power device, the switching speed is higher, the switching loss is lower, and the device performance is better; for the SGTMOSFET power device, the shape of the bottom of the groove has very important influence on the performance of the device.
In the field of medium and low voltage devices with the withstand voltage of over 60V, a Shielded Gate Trench (SGT) device has a charge coupling effect, horizontal depletion is introduced on the basis of the traditional Trench mosfet vertical depletion (p-body/n-epi junction), the electric field of the device is changed from triangular distribution to approximately rectangular distribution, and the device is widely applied due to low specific on-resistance and low Gate-drain coupling capacitance. The gate structure of the SGT device includes a shield polysilicon and a polysilicon gate, the shield polysilicon is also commonly referred to as source polysilicon and is formed in the trench, and the gate structure is generally divided into an upper structure, a lower structure and a left structure and a right structure according to the arrangement of the shield polysilicon and the polysilicon gate in the trench. The shielding polysilicon is positioned at the bottom of the groove in the upper and lower structures, the polysilicon gate is positioned at the top of the groove, and the polysilicon gate and the shielding polysilicon are in an upper-lower or left-right structural relationship.
The trench structure of a conventional SGT-MOSFET consists of two polysilicon portions: the upper half part is a control grid, the lower half part is a shielding grid, and the shielding grid is positioned below the control grid. When the device is conducted, the drain current forms an inversion layer channel on the surface of the body region along the longitudinal side wall of the groove. When the source is forward biased, electrons travel from the source region to the drain region along the inversion layer channel. Electrons pass through the channel from the source region, enter the drift region at the bottom of the trench gate, and then the current spreads out over the entire cell cross-sectional width. Application No.: 202010025423.4, Applicant: the invention name of Jinan' an Hai semiconductor Limited company, a novel SGT-MOSFET device gate structure, is that the left side and the right side of a shielding gate are respectively provided with a control gate, in the switching process of the device, an insulating medium between the control gate and the shielding gate is coupled, a gate-drain capacitor is added, meanwhile, the transverse overlapping area is reduced by two separate control gates, the gate source capacitance and the total gate charge are further reduced, so that the device has lower specific on-resistance and gate-drain charge, and the driving loss and the switching loss are reduced.
Application No.: 201911291567.8, Applicant: the invention relates to a process method of an SGT (SGT device) of Shanghai Huahong powerful semiconductor manufacturing company, which comprises the following process steps: the method comprises the steps that firstly, a groove type grid electrode is formed on a heavily doped semiconductor substrate, a groove is formed on the substrate through the groove type grid electrode, then a dielectric layer and a liner oxide layer are deposited, and then polycrystalline silicon is deposited and etched back to form source polycrystalline silicon; secondly, forming a thermal oxidation layer again; thirdly, depositing an oxide layer by adopting an HDPCVD method; fourthly, removing the liner oxide layer on the upper part of the trench; fifthly, depositing polycrystalline silicon and etching back to finish the manufacture of the polycrystalline silicon grid at the upper part of the groove; after a conventional thermal oxidation layer deposition process, a one-step HDPCVD process is added, so that the upper surface of a thermal oxidation layer is smoother, the transition of a corner region of a groove is smoother, the defects of depression at two sides, sharp corners and the like cannot occur, and the condition of electric leakage between a polycrystalline silicon grid and a shielding electrode is not easy to cause.
The invention improves the manufacturing process of the upper and lower SGT structure.
[ summary of the invention ]
The invention aims to provide a manufacturing process method of an upper and lower structure SGT, which has the same length of a gate oxide layer channel, effectively prevents gate-level polysilicon from being oxidized and easily exhausts an electric field at the bottom of a groove.
In order to achieve the above purpose, the technical scheme adopted by the invention is a process method for manufacturing an upper structure SGT and a lower structure SGT, which comprises the following manufacturing steps:
firstly, etching a first groove on a semiconductor substrate, firstly etching an upper half-depth groove on the semiconductor substrate, growing a gate oxide layer, accumulating and depositing a hard masking layer, then etching a lower half-depth groove, depositing and etching back to form a lower gate oxide layer and a bottom gate oxide layer, filling polysilicon and etching back to form bottom gate polysilicon which is back to the hard masking layer;
and secondly, etching a second groove, depositing a gate oxide layer on the hard masking layer on the side wall of the upper half-depth groove formed in the first step and the bottom grid polycrystalline silicon, filling the polycrystalline silicon and etching back to form upper source polycrystalline silicon.
Preferably, in the above process method for manufacturing the upper and lower structures SGT, the first trench etching in the first step specifically includes the following process steps:
s1, etching an upper half-depth groove on the semiconductor substrate;
s2, depositing and depositing silicon oxide on the upper half-depth groove in the step S1;
s3, stacking and precipitating silicon nitride on the silicon oxide in the step S2;
s4, back etching the silicon oxide and the silicon nitride on the top semiconductor substrate;
s5, etching back the silicon oxide and the silicon nitride at the bottom of the upper half-depth groove in the step S1, and then etching the silicon oxide and the silicon nitride at the bottom of the upper half-depth groove in half
Etching a lower half-depth groove on the conductor substrate to form a full-depth groove;
s6, depositing and precipitating silicon oxide on the full-depth groove in the step S5;
s7, etching back the silicon oxide in the step S6, so that the bottom of the full-depth groove and the side wall of the lower half-depth groove are gate oxide layers formed by the silicon oxide, the side wall of the upper half-depth groove is sequentially provided with the gate oxide layer formed by the silicon oxide and the silicon nitride and a hard masking layer, and the top of the semiconductor substrate is provided with the gate oxide layer formed by the silicon oxide;
s8, filling polysilicon in the full-depth groove formed by back etching in the step S7;
s9, etch back step S8 the polysilicon forms bottom gate polysilicon, and a new upper half depth trench.
Preferably, in the above process method for manufacturing the upper and lower structures SGT, the second trench etching in the second step specifically includes the following process steps:
s10, accumulating and depositing silicon oxide on the new upper half-depth groove side wall hard masking layer and the bottom grid polycrystalline silicon formed in the step S9 through etching back to form a grid oxide layer;
s11, filling polysilicon in the groove formed by deposition in the step S10;
s12, etching back the polysilicon in the step S11 to form upper source polysilicon.
Preferably, in the above process method for manufacturing the upper and lower SGT structures, the first trench etching is performed, and gate oxide layers with the same length are grown on the sidewalls of the trenches to form the same channel length.
Preferably, in the above-mentioned process method for manufacturing the upper and lower structures SGT, the gate polysilicon formed by etching back in step S9 is backed by the hard mask layer formed by etching back in step S7.
Preferably, in the above-mentioned process method for manufacturing the upper and lower structures SGT, the lower half-depth trench etched in step S5 has a wider width than the upper half-depth trench etched in step S1.
Preferably, in the above-mentioned process method for manufacturing the upper and lower structures SGT, the step S10 is to deposit silicon oxide by using a chemical vapor deposition method, so as to form gate oxide layers with different thicknesses according to actual needs.
The process method for manufacturing the upper and lower structure SGT has the following beneficial effects: 1. etching a first groove, wherein gate oxide layers with the same length can grow on the side walls of two sides of the groove, and the length of the groove can be the same; 2. the oxide layer between the source electrode polycrystalline silicon and the grid electrode polycrystalline silicon is controllable, and different silicon oxide thicknesses are deposited by a Chemical Vapor Deposition (CVD) method according to actual requirements without the limitation of the thickness of the grid oxide layer; 3. the hard masking layer on the back surface of the gate polycrystalline silicon can prevent the gate polycrystalline silicon from being oxidized and enable the interval between the gate polycrystalline silicon and the source polycrystalline silicon to be better; 4. the bottom of the trench is widened to facilitate the depletion of the electric field.
[ description of the drawings ]
Fig. 1 is a schematic diagram of a process step S1 of manufacturing the upper and lower structures SGT.
Fig. 2 is a schematic diagram of a process step S2 of manufacturing the upper and lower structures SGT.
Fig. 3 is a schematic diagram of a process step S3 of manufacturing the upper and lower structures SGT.
Fig. 4 is a schematic diagram of a process step S4 of manufacturing the upper and lower structures SGT.
Fig. 5 is a schematic diagram of a process step S5 of manufacturing the upper and lower structures SGT.
Fig. 6 is a schematic diagram of a process step S6 of manufacturing the upper and lower structures SGT.
Fig. 7 is a schematic diagram of a process step S7 of manufacturing the upper and lower structures SGT.
Fig. 8 is a schematic diagram of a process step S8 of manufacturing the upper and lower structures SGT.
Fig. 9 is a schematic diagram of a process step S9 of manufacturing the upper and lower structures SGT.
Fig. 10 is a schematic diagram of a process step S10 of manufacturing the upper and lower structures SGT.
Fig. 11 is a schematic diagram of a process step S11 of manufacturing the upper and lower structures SGT.
Fig. 12 is a schematic diagram of a process step S12 of manufacturing the upper and lower structures SGT.
The reference numerals and components referred to in the drawings are as follows: 1. semiconductor substrate, 2, silicon oxide, 3, silicon nitride, 4, polysilicon.
[ detailed description ] embodiments
The invention is further described with reference to the following examples and with reference to the accompanying drawings.
Example 1
This embodiment realizes a process method for manufacturing the upper and lower SGT structures.
Fig. 12 is a schematic view of a process step S12 of manufacturing the upper and lower structures SGT, and as shown in fig. 12, the process of manufacturing the upper and lower structures SGT of the present embodiment includes the following manufacturing steps:
firstly, etching a first groove on a semiconductor substrate, firstly etching an upper half-depth groove on the semiconductor substrate, growing a gate oxide layer, accumulating and depositing a hard masking layer, then etching a lower half-depth groove, depositing and etching back to form a lower gate oxide layer and a bottom gate oxide layer, filling polysilicon and etching back to form bottom gate polysilicon which is back to the hard masking layer;
and secondly, etching a second groove, depositing a gate oxide layer on the hard masking layer on the side wall of the upper half-depth groove formed in the first step and the bottom grid polycrystalline silicon, filling the polycrystalline silicon and etching back to form upper source polycrystalline silicon.
Preferably, in the above process method for manufacturing the upper and lower structures SGT, the first trench etching in the first step specifically includes the following process steps:
s1, FIG. 1 is a schematic view of a process step S1 of manufacturing an upper and lower structure SGT, as shown in FIG. 1, etching an upper half-depth trench on a semiconductor substrate;
s2, fig. 2 is a schematic view of a process step S2 of fabricating an upper and lower structure SGT, as shown in fig. 2, silicon oxide is deposited and precipitated on the upper half-depth trench of step S1;
s3, FIG. 3 is a schematic view of step S3 of a process for manufacturing upper and lower SGT structures, as shown in FIG. 3, silicon nitride is deposited and precipitated on the silicon oxide in step S2;
s4, FIG. 4 is a schematic view of a process step S4 of fabricating an upper and lower structure SGT, shown in FIG. 4, by etching back silicon oxide and silicon nitride on a top semiconductor substrate;
s5, fig. 5 is a schematic view of a process of manufacturing an upper and lower SGT, step S5, as shown in fig. 5, the silicon oxide and the silicon nitride at the bottom of the upper half-depth trench in step S1 are etched back, and then the lower half-depth trench is etched on the semiconductor substrate to form a full-depth trench;
s6, FIG. 6 shows a process step S6 of fabricating upper and lower structures SGT, as shown in FIG. 6, silicon oxide is deposited and precipitated on the full depth trenches in step S5;
s7 and fig. 7 are schematic diagrams of a process method step S1 of manufacturing an SGT with an upper and lower structure, as shown in fig. 7, the silicon oxide described in step S7 is etched back, so that the bottom of the full-depth trench and the sidewall of the lower half-depth trench are gate oxide layers formed by the silicon oxide, the sidewall of the upper half-depth trench is sequentially a gate oxide layer formed by the silicon oxide and silicon nitride, and a hard masking layer, and the top of the semiconductor substrate is a gate oxide layer formed by the silicon oxide;
s8, fig. 8 is a schematic view of a process of manufacturing an upper and lower structure SGT in step S8, as shown in fig. 8, polysilicon is filled in the full depth trench formed by etching back in step S7;
s9, fig. 9 is a schematic view of a process step S9 of fabricating the upper and lower structures SGT, as shown in fig. 9, the polysilicon is etched back to form bottom gate polysilicon and a new upper half-depth trench in step S8.
Preferably, in the above process method for manufacturing the upper and lower structures SGT, the second trench etching in the second step specifically includes the following process steps:
s10, fig. 10 is a schematic view of a process of manufacturing an upper and lower structure SGT, step S10, as shown in fig. 10, the new upper half-depth trench sidewall hard masking layer formed in step S9 is etched back, and silicon oxide is deposited and deposited on the bottom gate polysilicon to form a gate oxide layer;
s11, FIG. 10 is a schematic view of a process of fabricating an upper and lower structure SGT, step S10, as shown in FIG. 10, filling polysilicon in the trench formed by the deposition of step S10;
s12, FIG. 12 is a process step S12 of fabricating an upper and lower structure SGT, as shown in FIG. 12, the polysilicon is etched back to form upper source polysilicon in step S11.
Preferably, in the above process method for manufacturing the upper and lower SGT structures, the first trench etching is performed, and gate oxide layers with the same length are grown on the sidewalls of the trenches to form the same channel length.
Preferably, in the above-mentioned process method for manufacturing the upper and lower structures SGT, the gate polysilicon formed by etching back in step S9 is backed by the hard mask layer formed by etching back in step S7.
Preferably, in the above-mentioned process method for manufacturing the upper and lower structures SGT, the lower half-depth trench etched in step S5 has a wider width than the upper half-depth trench etched in step S1.
Preferably, in the above-mentioned process method for manufacturing the upper and lower structures SGT, the step S10 is to deposit silicon oxide by using a chemical vapor deposition method, so as to form gate oxide layers with different thicknesses according to actual needs.
The process method for manufacturing the upper and lower structure SGT has the following beneficial effects: 1. etching a first groove, wherein gate oxide layers with the same length can grow on the side walls of two sides of the groove, and the length of the groove can be the same; 2. the oxide layer between the source electrode polycrystalline silicon and the grid electrode polycrystalline silicon is controllable, and different silicon oxide thicknesses are deposited by a Chemical Vapor Deposition (CVD) method according to actual requirements without the limitation of the thickness of the grid oxide layer; 3. the hard masking layer on the back surface of the gate polycrystalline silicon can prevent the gate polycrystalline silicon from being oxidized and enable the interval between the gate polycrystalline silicon and the source polycrystalline silicon to be better; 4. the bottom of the trench is widened to facilitate the depletion of the electric field.
Example 2
This embodiment realizes a process method for manufacturing the upper and lower SGT structures. Related art terms are as follows, Trench, etch Trench etch, Trench etch, gox (gate oxide) gate oxide, oxide, oxide film, Channel, Channel length, Poly, SIN hard mask, SIN silicon nitride, gdo, gate Poly, Source Poly, linear oxide, etch back, Chemical Vapor Deposition (CVD).
The main purpose of the process for manufacturing the upper and lower SGT of this embodiment is: 1. two times of trench etch to complete SGT of an upper structure and a lower structure, and the fixed 1st trench, GOX with the same length can grow on two sides, and the GOX with the same channel length can grow on two sides; SIN on the back of Poly will prevent Gpoly from being oxidized and make the space between Gpoly and source Poly better; 3. the bottom is widened, so that the electric field is depleted.
The process method for manufacturing the upper and lower SGT structures in this embodiment includes the following process steps:
1. as shown in FIGS. 1 to 9, 1st trench is made, and growing GOX, deposit (deposition vi. precipitation) GOX and SIN, trench bottom SIN/POLY/GOX;
2. as shown in FIG. 10, then 2nd inch trench, remove the grow or position oxide as required by the linear oxide thickness and the distance between two poly layers;
3. as shown in fig. 11, 12, then filled with poly, followed by etch back.
The process method for manufacturing the upper and lower structure SGT has the following beneficial effects: 1. fixed 1st trench, GOX with the same length will grow on both sides, and channel length will be the same; 2. the oxide layer between Source poly and Gpoly is controllable, and the different thicknesses of CVD deposint are not limited by the thickness of GOX according to the actual requirements; 3. the SIN on the back of the Poly prevents Gpoly from being oxidized, and enables the interval between the Gpoly and the source Poly to be better; 4. the bottom is widened, so that the electric field is depleted.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and additions can be made without departing from the principle of the present invention, and these should also be considered as the protection scope of the present invention.
Claims (7)
1. A process method for manufacturing an upper structure SGT and a lower structure SGT is characterized by comprising the following manufacturing steps:
firstly, etching a first groove on a semiconductor substrate, firstly etching an upper half-depth groove on the semiconductor substrate, growing a gate oxide layer, accumulating and depositing a hard masking layer, then etching a lower half-depth groove, depositing and etching back to form a lower gate oxide layer and a bottom gate oxide layer, filling polysilicon and etching back,
forming a bottom gate polysilicon back to the hard masking layer;
and secondly, etching a second groove, depositing a gate oxide layer on the hard masking layer on the side wall of the upper half-depth groove formed in the first step by back etching and the bottom gate polycrystalline silicon, filling the polycrystalline silicon and back etching to form upper source polycrystalline silicon.
2. The process method for manufacturing an upper and lower structure SGT according to claim 1, wherein the first trench etching step specifically comprises the following process steps:
s1, etching an upper half-depth groove on the semiconductor substrate;
s2, depositing and depositing silicon oxide on the upper half-depth groove in the step S1;
s3, stacking and precipitating silicon nitride on the silicon oxide in the step S2;
s4, back etching the silicon oxide and the silicon nitride on the top semiconductor substrate;
s5, etching back the silicon oxide and the silicon nitride at the bottom of the upper half-depth groove in the step S1, and further etching the lower half-depth groove on the semiconductor substrate to form a full-depth groove;
s6, depositing and precipitating silicon oxide on the full-depth groove in the step S5;
s7, etching back the silicon oxide in the step S6, so that the bottom of the full-depth groove and the side wall of the lower half-depth groove are gate oxide layers formed by the silicon oxide, the side wall of the upper half-depth groove is sequentially provided with the gate oxide layer formed by the silicon oxide and the silicon nitride and a hard masking layer, and the top of the semiconductor substrate is provided with the gate oxide layer formed by the silicon oxide;
s8, filling polysilicon in the full-depth groove formed by back etching in the step S7;
s9, etch back step S8 the polysilicon forms bottom gate polysilicon, and a new upper half depth trench.
3. The process for manufacturing an upper and lower structure SGT according to claim 3, wherein the second trench etching step specifically comprises the following process steps:
s10, accumulating and depositing silicon oxide on the new upper half-depth groove side wall hard masking layer and the bottom grid polycrystalline silicon formed in the step S9 through etching back to form a grid oxide layer;
s11, filling polysilicon in the groove formed by deposition in the step S10;
s12, etching back the polysilicon in the step S11 to form upper source polysilicon.
4. The process for manufacturing upper and lower structured SGTs according to claim 3, wherein: and in the first step, etching the first groove, and growing gate oxide layers with the same length on the side wall of the groove to form the same channel length.
5. The process for manufacturing upper and lower structured SGTs according to claim 3, wherein: the gate polysilicon formed in the step S9 is etched back to the hard mask layer formed in the step S7.
6. The process for manufacturing upper and lower structured SGTs according to claim 3, wherein: the width of the lower half-depth trench etched and formed in the step S5 is wider than that of the upper half-depth trench etched and formed in the step S1.
7. The process for manufacturing upper and lower structured SGTs according to claim 3, wherein: and step S10, depositing silicon oxide by using a chemical vapor deposition method, and forming gate oxide layers with different thicknesses according to actual needs.
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