CN115799307B - Shielding grid power device and preparation method thereof - Google Patents
Shielding grid power device and preparation method thereof Download PDFInfo
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- CN115799307B CN115799307B CN202211505650.2A CN202211505650A CN115799307B CN 115799307 B CN115799307 B CN 115799307B CN 202211505650 A CN202211505650 A CN 202211505650A CN 115799307 B CN115799307 B CN 115799307B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention relates to a shielded gate power device and a preparation method thereof. The shielded gate power device includes: a semiconductor layer; a trench in the semiconductor layer; the shielding grid is positioned in the groove, and the upper surface of the shielding grid is lower than the top surface of the groove; the grid electrode is positioned in the groove and above the shielding grid electrode, and has a distance with the shielding grid electrode; an air cavity is located within the trench and between the gate and the shield gate to isolate the gate from the shield gate. According to the shielded gate power device, the air cavity is arranged between the gate electrode and the shielded gate electrode as the isolation layer, and because the air has a good isolation voltage-resistant effect and a very low dielectric constant, the voltage resistance between the gate electrode and the source electrode of the device can be obviously improved on the basis of ensuring the voltage resistance between the source electrode and the drain electrode of the device, and the parasitic capacitance Cgs of the gate electrode can be greatly reduced, so that the switching speed of the device is improved, and the switching loss is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate power device and a preparation method thereof.
Background
In a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device, a shielded gate trench (Shielded Gate Transistor, SGT) MOSFET has been widely used in many fields because of its advantages such as lower on-resistance and faster switching speed compared to conventional trench MOSFETs.
The structure of the shielded gate trench MOSFET is shown in FIG. 1, and may specifically include: semiconductor layer 10, trench 11, shield gate 12, field oxide 13, isolation dielectric 14, gate 15, and gate oxide 16. As can be seen from fig. 1, the isolation dielectric layer 14 is required between the gate electrode 15 and the shield gate electrode 12 to perform isolation, and the isolation dielectric layer 14 needs to have a good withstand voltage to suppress gate-source leakage. Since the isolation dielectric layer 14 is typically an oxide layer, a nitride layer or an oxynitride layer, the dielectric constant is relatively high, so that parasitic capacitance Cgs is generated between the gate and the source, that is, the input capacitance is increased, thereby greatly affecting the switching performance of the device.
The conventional technology generally increases the isolation dielectric layer 14, which can increase the gate-source voltage resistance and reduce the gate-source parasitic capacitance, but the increase in the thickness of the isolation dielectric layer 14 shortens the length of the shield gate 12, thereby affecting the source-drain voltage resistance.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a shielded gate power device and a method for manufacturing the same, which aims to solve the problems that parasitic capacitance Cgs is generated between gate sources due to the arrangement of an isolation medium layer between a gate and a shielded gate for isolation in the shielded gate trench MOSFET in the prior art, thereby greatly influencing the switching performance of the device, and the length of the shielded gate is shortened due to the increase of the thickness of the isolation medium layer, thereby influencing the withstand voltage between source and drain.
In a first aspect, the present invention provides a shielded gate power device comprising:
a semiconductor layer;
a trench within the semiconductor layer;
the shielding grid is positioned in the groove, and the upper surface of the shielding grid is lower than the top surface of the groove;
the grid electrode is positioned in the groove and above the shielding grid electrode, and has a distance with the shielding grid electrode;
an air cavity is located within the trench and between the gate and the shield gate to isolate the gate from the shield gate.
According to the shielded gate power device, the air cavity is arranged between the gate and the shielded gate to serve as the isolation layer, and because air has a good isolation voltage-resistant effect and a very low dielectric constant, the inter-gate-source voltage resistance of the device can be obviously improved on the basis of ensuring the inter-source voltage resistance of the device, and the parasitic capacitance Cgs of the gate source can be greatly reduced, so that the switching speed of the device is improved, and the switching loss is reduced.
In one embodiment, the shielded gate power device further includes:
the field oxide layer is positioned below the air cavity, is positioned between the shielding grid electrode and the semiconductor layer, and covers the bottom and part of the side wall of the shielding grid electrode;
and the gate oxide layer is positioned above the air cavity, is positioned between the gate and the semiconductor layer and covers the side wall of the gate.
In one embodiment, the upper surface of the shield gate is higher than the upper surface of the field oxide layer.
In one embodiment, the grid is further provided with a through hole, and the through hole penetrates through the grid from top to bottom and is communicated with the air cavity; the shielded gate power device further includes:
a filling medium layer for filling the through hole;
and the medium layer is covered to cover the inner wall of the air cavity.
In one embodiment, the number of the through holes is a plurality, and the plurality of through holes are arranged in an array; and the filling medium layer fills all the through holes.
In a second aspect, the present invention further provides a method for preparing a shielded gate power device, including:
providing a semiconductor layer;
forming a groove in the semiconductor layer;
forming a shielding grid in the groove, wherein the upper surface of the shielding grid is lower than the top surface of the groove;
forming a grid electrode and an air cavity in the groove; the grid electrode is positioned above the shielding grid electrode and is spaced from the shielding grid electrode; the air cavity is located between the grid and the shielded grid to isolate the grid from the shielded grid.
According to the preparation method of the shielded gate power device, the air cavity is prepared between the gate and the shielded gate as the isolation layer, and because air has a good isolation voltage-resistant effect and a very low dielectric constant, the inter-gate-source voltage resistance of the device can be obviously improved on the basis of ensuring the inter-source voltage resistance of the device, and the parasitic capacitance Cgs of the gate source can be greatly reduced, so that the switching speed of the device is improved, and the switching loss is reduced.
In one embodiment, before forming the shielding gate in the trench, the method further includes: forming a field oxide material layer on the upper surface of the semiconductor layer, the side wall and the bottom of the groove; the shielding grid electrode is formed on the surface, far away from the semiconductor layer, of the field oxide material layer;
after forming the shielding grid electrode in the groove, the method further comprises the following steps: and removing the field oxide material layer on the upper surface of the semiconductor layer and on the upper side wall of the groove to obtain a field oxide layer, wherein the field oxide layer coats the bottom and part of the side wall of the shielding grid electrode.
In one embodiment, forming the gate and the air cavity within the trench includes:
forming a sacrificial layer in the groove, wherein the sacrificial layer is positioned above the shielding grid electrode; the upper surface of the sacrificial layer is lower than the top surface of the groove;
forming a grid electrode on the upper surface of the sacrificial layer;
forming a through hole in the grid electrode, wherein the through hole exposes the sacrificial layer;
and removing the sacrificial layer based on the through hole to form the air cavity.
In one embodiment, after forming the sacrificial layer in the trench and before forming the gate with the upper surface of the sacrificial layer, the method further comprises: forming a gate oxide layer on at least the exposed side wall of the groove; the grid electrode is formed on the surface of the grid oxide layer far away from the semiconductor layer.
In one embodiment, after removing the sacrificial layer based on the through hole to form the air cavity, the method further includes: and forming a filling medium layer in the through hole, and forming a covering medium layer covering the inner wall of the air cavity on the inner wall of the air cavity.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present invention, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic cross-sectional structure of a prior art shielded gate trench MOSFET;
fig. 2 is a flowchart of a method for manufacturing a shielded gate power device according to an embodiment;
fig. 3 is a schematic cross-sectional structure of the structure obtained in step S10 in the method for manufacturing a shielded gate power device according to an embodiment;
fig. 4 is a schematic cross-sectional structure of the structure obtained in step S20 in the method for manufacturing a shielded gate power device according to an embodiment;
fig. 5 is a schematic cross-sectional structure of a structure obtained after forming a field oxide material layer in a method for manufacturing a shielded gate power device according to an embodiment;
fig. 6 is a schematic cross-sectional structure of the structure obtained in step S30 in the method for manufacturing a shielded gate power device according to an embodiment;
fig. 7 is a schematic cross-sectional structure of a structure obtained after a field oxide layer is formed in a method for manufacturing a shielded gate power device according to an embodiment;
fig. 8 to 12 are schematic cross-sectional structural diagrams of the structure obtained in step S40 in the method for manufacturing a shielded gate power device according to an embodiment;
FIG. 13 is a schematic top view of the gate of FIG. 8;
fig. 14 is a schematic cross-sectional structure of the structure obtained in step S50 in the method for manufacturing a shielded gate power device according to an embodiment.
Reference numerals illustrate:
10. a semiconductor layer; 11. a groove; 12. a shield gate; 13. a field oxide layer; 14. an isolation dielectric layer; 15. a gate; 16. a gate oxide layer; 20. a semiconductor layer; 21. a groove; 22. a field oxide layer; 221. a field oxide material layer; 23. a shield gate; 24. a sacrificial layer; 25. a gate; 251. a through hole; 26. an air chamber; 27. a gate oxide layer; 28. filling a dielectric layer; 29. covering the dielectric layer.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
In one embodiment, referring to fig. 2, the present invention provides a method for manufacturing a shielded gate power device, where the method for manufacturing a shielded gate power device may include the following steps:
s10: providing a semiconductor layer;
s20: forming a groove in the semiconductor layer;
s30: forming a shielding grid in the groove, wherein the upper surface of the shielding grid is lower than the top surface of the groove;
s40: forming a grid electrode and an air cavity in the groove; the grid electrode is positioned above the shielding grid electrode and is spaced from the shielding grid electrode; the air cavity is located between the grid and the shielded grid to isolate the grid from the shielded grid.
According to the preparation method of the shielded gate power device, the air cavity is prepared between the gate and the shielded gate as the isolation layer, and because air has a good isolation voltage-resistant effect and a very low dielectric constant, the inter-gate-source voltage resistance of the device can be obviously improved on the basis of ensuring the inter-source voltage resistance of the device, and the parasitic capacitance Cgs of the gate source can be greatly reduced, so that the switching speed of the device is improved, and the switching loss is reduced.
In step S10, referring to step S10 in fig. 2 and fig. 3, a semiconductor layer 20 is provided.
By way of example, the semiconductor layer 20 may be at least one doped layer, such as to be at least one epitaxially doped layer; at this time, the semiconductor layer 20 may be formed on a substrate (not shown). Of course, in other examples, the semiconductor layer 20 may also be a doped substrate. Note that, the doping concentration range in the semiconductor layer 20 may be set according to the actual situation, which is not limited herein.
By way of example, the material of the semiconductor layer 20 may include, but is not limited to, silicon germanium, silicon carbide, gallium nitride, or other suitable semiconductor materials, and the like.
In step S20, referring to step S20 in fig. 2 and fig. 3, a trench 21 is formed in the semiconductor layer 20.
As an example, step S20 may include the steps of:
s201: forming a patterned mask layer (not shown) on the upper surface of the semiconductor layer 20, wherein the patterned mask layer is provided with an opening pattern, and the opening pattern defines the shape and the position of the groove 21;
s202: etching the semiconductor layer 20 based on the patterned mask layer to form the trench 21 in the semiconductor layer 20;
s203: and removing the patterned mask layer to obtain a structure shown in figure 4.
In an alternative example, step S201 may include the steps of:
s2011: forming a mask layer on the upper surface of the semiconductor layer 20;
s2012: forming a photoresist layer on the upper surface of the mask layer;
s2013: exposing and developing the photoresist layer to form a patterned photoresist layer;
s2014: etching the mask layer based on the patterned photoresist layer to obtain the patterned mask layer;
s2015: and removing the patterned photoresist layer.
As an example, in step S2011, the formed mask layer may have a single layer structure, and in this case, the mask layer may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer; in step S2011, the mask layer may be formed in a multi-layer structure, and in this case, the mask layer may include at least two layers of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
As an example step S2011, the mask layer may be formed using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
In another alternative example, step S201 may include the steps of:
s2011: forming a photoresist layer on the upper surface of the semiconductor layer 20;
s2012: and exposing and developing the photoresist layer to form a patterned photoresist layer serving as the patterned mask layer.
As an example, the depth of the trench 21 is smaller than the thickness of the semiconductor layer 20.
As an example, the longitudinal cross-sectional shape of the groove 21 may be, but is not limited to, a U-shape as shown in fig. 4, or the like.
As an example, the number of the grooves 21 formed in step S20 may be set according to actual needs, and only two grooves 21 are taken as an example in fig. 4, and in other examples, the number of the grooves 21 is not limited to the number in fig. 4, but may be one, three, four, five, six or more, or the like.
As an example, as shown in fig. 5, after step S20, the following steps may be further included:
a field oxide material layer 221 is formed on the upper surface of the semiconductor layer 20, the sidewall and the bottom of the trench 21.
As an example, an oxide layer may be formed on the upper surface of the semiconductor layer 20, the sidewall and the bottom of the trench 21 by a thermal oxidation process, but is not limited to, as the field oxide material layer 221.
In step S30, referring to step S3 in fig. 2 and fig. 6, a shielding gate 23 is formed in the trench 21, and an upper surface of the shielding gate 23 is lower than a top surface of the trench 21.
As an example, step S30 may include the steps of:
s301: forming a shield gate material layer (not shown) in the trench 21 and on the upper surface of the field oxide material layer 221;
s302: removing the shielding gate material layer located on the upper surface of the field oxide material layer 221 outside the trench 21;
s303: and etching back to remove part of the shielding gate material layer in the trench 21, wherein the shielding gate material layer remained in the trench 21 is the shielding gate 23.
As an example, in step S301, the shielding gate material layer may be formed using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
As an example, the shield gate material layer may include, but is not limited to, a polysilicon layer.
As an example, in step S302, the shielding gate material layer on the upper surface of the field oxide material layer 221 outside the trench 21 may be removed by using, but not limited to, a chemical mechanical polishing process or an etching process.
As an example, in step S303, a portion of the shielding gate material layer located in the trench 21 may be etched back using, but not limited to, a dry etching process.
As an example, following step S30, the following steps may be further included:
the field oxide material layer on the upper surface of the semiconductor layer 20 and on the upper side wall of the trench 21 is removed to obtain a field oxide layer 22, and the field oxide layer 22 covers the bottom and part of the side wall of the shielding gate 23, as shown in fig. 7.
Specifically, the field oxide layer on the upper surface of the semiconductor layer 20 may be removed using, but not limited to, a chemical mechanical polishing process; and then a dry etching process is used to remove a portion of the field oxide material layer located in the trench 21.
More specifically, the upper surface of the shield gate 23 is higher than the upper surface of the field oxide layer 22. The height of the shield gate 23 above the shield gate oxide layer 22 may be set according to actual needs, and is not limited herein.
In step S40, referring to step S40 in fig. 2 and fig. 8 to 13, a gate 25 and an air cavity 26 are formed in the trench 21; the grid electrode 25 is positioned above the shielding grid electrode 23 and is spaced from the shielding grid electrode 23; the air chamber 26 is located between the grid 25 and the shielded grid 23 to isolate the grid 25 from the shielded grid 23.
As an example, step S40 may include the steps of:
s401: forming a sacrificial layer 24 in the trench 21, wherein the sacrificial layer 24 is positioned above the shielding gate 23; the upper surface of the sacrificial layer 24 is lower than the top surface of the trench 21 as shown in fig. 8;
s403: forming a gate electrode 25 on the upper surface of the sacrificial layer 24, as shown in fig. 10;
s404: forming a via 251 in the gate 25, wherein the via 251 exposes the sacrificial layer 24, as shown in fig. 11;
s405: the sacrificial layer 24 is removed based on the through holes 251 to form the air chamber 26.
As an example step S401 may include the steps of:
s4011: forming a sacrificial material layer (not shown) in the trench 21 and on the upper surface of the semiconductor layer 20;
s4012: removing the sacrificial material layer on the upper surface of the semiconductor layer 20; specifically, the sacrificial material layer on the upper surface of the semiconductor layer 20 may be removed by, but not limited to, a chemical mechanical polishing process or an etching process;
s4013: etching back to remove part of the sacrificial material layer in the groove 21, wherein the sacrificial material layer remained in the groove 21 is the sacrificial layer; specifically, a dry etching process may be used, but is not limited to, etching back a portion of the sacrificial material layer located within the trench 21.
As an example, the material of the sacrificial layer 24 is different from the material of the gate electrode 25, the material of the field oxide layer 22 and the material of the shielding gate electrode 23; specifically, the sacrificial layer 24 may include, but is not limited to, a nitride layer.
As an example, between step S401 and step S403, the following steps may be further included:
s402: forming a gate oxide layer 27 on at least the exposed side wall of the trench 21, as shown in fig. 9; the gate electrode 25 is formed on the surface of the gate oxide layer 27 away from the semiconductor layer 21, as shown in fig. 10.
As an example, the gate oxide layer 27 may be formed on the exposed sidewall of the trench 21 and the upper surface of the semiconductor layer 20 using, but not limited to, a thermal oxidation process, as shown in fig. 9.
As an example, step S403 may include the steps of:
s4031: forming a gate material layer (not shown) on the upper surface of the sacrificial layer 24 and the upper surface of the gate oxide layer 27 outside the trench 21;
s4032: removing the gate material layer on the upper surface of the gate oxide layer 27 outside the trench 21, wherein the gate material layer remaining in the trench 21 is the gate electrode 25; specifically, the gate material layer on the upper surface of the gate oxide layer 27 outside the trench 21 may be removed by, but not limited to, a chemical mechanical polishing process or an etching process.
As an example, the gate 25 may include, but is not limited to, a polysilicon gate.
As an example, in step S404, the gate electrode 25 may be etched using, but not limited to, a dry etching process to form the via 251 in the gate electrode 25.
As an example, the shape of the through hole 251 may be circular, rectangular, elliptical, or the like. Here, fig. 13 exemplifies a shape of the through hole 251 as a circle.
As an example, the plurality of through holes 251 in the gate electrode 25 may be uniformly spaced.
As an example, the specific number and distribution of the through holes 251 may be set according to actual needs, which is not limited herein.
As an example, the sacrificial layer 24 may be removed based on the through hole 251 using a wet etching solution. Specifically, the wet etching solution may be any wet etching solution having a removal rate of the sacrificial layer 24 significantly greater than the removal rate of the gate electrode 25, the removal rate of the field oxide layer 22, the removal rate of the shielding gate electrode 23, and the removal rate of the semiconductor layer 20.
As an example, following step S40, the following steps may be further included:
a filling dielectric layer 28 is formed in the through hole 251, and a covering dielectric layer 29 is formed on the inner wall of the air chamber 26 to cover the inner wall of the air chamber 26, as shown in fig. 14.
As an example, the structure obtained in step S40 may be subjected to a thermal oxidation process, so that a part of the gate electrode 25 is oxidized to form the filling dielectric layer 28 to fill the via 251, and a part of the semiconductor layer 20, a part of the gate electrode 25, and a part of the shield gate electrode 23 are oxidized to form the capping dielectric layer 29. I.e. the filling dielectric layer 28 and the covering dielectric layer 29 are both oxide layers obtained by a thermal oxidation process.
It should be noted that, if the aperture of the through hole 251 is too large, it will be difficult to seal the through hole 251 during the process of forming the filling medium layer 28. The pitch of the adjacent through holes 251 cannot be too small, and if the pitch of the adjacent through holes 251 is too small, the gate electrode between the adjacent through holes 251 will be completely oxidized during the process of forming the filling medium layer 28, thereby losing the effect of the gate electrode.
Specifically, the aperture of the through hole 251 may be between 0.1um and 0.5um, and specifically, the aperture of the through hole 251 may be 0.1um, 0.2um, 0.3um, 0.4 um or 0.5um. The pitch of the adjacent through holes 251 may be greater than or equal to 2um, for example, the pitch of the adjacent through holes 251 may be 2um, 5um, 10um, 15um, or the like.
As an example, after forming the filling dielectric layer 28 in the through hole 251 and forming the covering dielectric layer 29 covering the inner wall of the air cavity 26 on the inner wall of the air cavity 26, the method further includes the following steps:
forming body regions (not shown) in the semiconductor layer 20, the body regions being located on opposite sides of the trench 21;
forming a source (not shown) in the body region;
forming a gate electrode (not shown), a source electrode (not shown), and a drain electrode (not shown), the gate electrode being electrically connected to the gate electrode 25; the source electrode penetrates through the source electrode and extends into the body region; the drain electrode is electrically connected to the lower surface of the semiconductor layer 10. Specifically, the drain electrode may be located on the lower surface of the semiconductor layer 10.
In another embodiment, please continue to refer to fig. 14, the present invention further provides a shielded gate power device, which includes: a semiconductor layer 20; a trench 21, the trench 2 being located within the semiconductor layer 20; a shield gate 23, the shield gate 23 being located in the trench 21, an upper surface of the shield gate 23 being lower than a top surface of the trench 21; a gate 25, wherein the gate 25 is located in the trench 21 and above the shielding gate 23, and has a distance from the shielding gate 23; an air cavity 26, the air cavity 26 being located within the trench 21 and between the gate 25 and the shield gate 23 to isolate the gate 25 from the shield gate 23.
According to the shielded gate power device, the air cavity 26 is arranged between the gate electrode 25 and the shielded gate electrode 23 to serve as an isolation layer, and because air has a good isolation voltage-resistant effect and a very low dielectric constant, the inter-gate-source voltage resistance of the device can be remarkably improved on the basis of ensuring the inter-source voltage resistance of the device, and the parasitic capacitance Cgs of the gate source can be greatly reduced, so that the switching speed of the device is improved, and the switching loss is reduced.
By way of example, the semiconductor layer 20 may be at least one doped layer, such as to be at least one epitaxially doped layer; at this time, the semiconductor layer 20 may be formed on a substrate (not shown). Of course, in other examples, the semiconductor layer 20 may also be a doped substrate. Note that, the doping concentration range in the semiconductor layer 20 may be set according to the actual situation, which is not limited herein.
By way of example, the material of the semiconductor layer 20 may include, but is not limited to, silicon germanium, silicon carbide, gallium nitride, or other suitable semiconductor materials, and the like.
As an example, the depth of the trench 21 is smaller than the thickness of the semiconductor layer 20.
As an example, the longitudinal cross-sectional shape of the groove 21 may be, but is not limited to, a U-shape as shown in fig. 14, or the like.
As an example, the number of the grooves 21 may be set according to actual needs, and in fig. 14, only the number of the grooves 21 is taken as two as an example, and in other examples, the number of the grooves 21 is not limited to the number in fig. 14, but may be one, three, four, five, six or more, or the like.
As an example, the shield gate 23 may include, but is not limited to, a polysilicon gate.
As an example, the gate 25 may include, but is not limited to, a polysilicon gate.
As an example, the shielded gate power device further includes: a field oxide layer 22, wherein the field oxide layer 22 is located below the air cavity 26 and between the shielding gate 23 and the semiconductor layer 20, and covers the bottom and part of the side wall of the shielding gate 23; and a gate oxide layer 27, wherein the gate oxide layer 27 is positioned above the air cavity 26, between the gate electrode 25 and the semiconductor layer 20, and covers the side wall of the gate electrode 25.
As an example, the gate oxide layer 27 is also located on the upper surface of the semiconductor layer 20 outside the trench 21.
As an example, the field oxide layer 22 may include, but is not limited to, a silicon oxide layer. The gate oxide layer 27 may include, but is not limited to, a silicon oxide layer.
As an example, the upper surface of the shield gate 23 may be higher than the upper surface of the field oxide layer 22.
As an example, the gate 25 further has a through hole 251 therein, and the through hole 251 penetrates the gate 25 from top to bottom and communicates with the air chamber 26.
As an example, the shape of the through hole 251 may be circular, rectangular, elliptical, or the like. Here, fig. 13 exemplifies a shape of the through hole 251 as a circle.
As an example, the plurality of through holes 251 in the gate electrode 25 may be uniformly spaced.
As an example, the specific number and distribution of the through holes 251 may be set according to actual needs, which is not limited herein. Specifically, the plurality of through holes 251 may be arranged in an array.
As an example, the shielded gate power device may further include: a filling dielectric layer 28, wherein the filling dielectric layer 28 fills the through hole 251; a cover dielectric layer 29, the cover dielectric layer 29 covering the inner wall of the air chamber 26.
As an example, when the number of the through holes 251 is plural, the filling medium layer 28 fills all the through holes 251.
As an example, the filling dielectric layer 28 and the covering dielectric layer 29 may be oxide layers obtained by a thermal oxidation process.
It should be noted that, if the aperture of the through hole 251 is too large, it will be difficult to seal the through hole 251 during the process of forming the filling medium layer 28. The pitch of the adjacent through holes 251 cannot be too small, and if the pitch of the adjacent through holes 251 is too small, the gate electrode between the adjacent through holes 251 will be completely oxidized during the process of forming the filling medium layer 28, thereby losing the effect of the gate electrode.
Specifically, the aperture of the through hole 251 may be between 0.1um and 0.5um, and specifically, the aperture of the through hole 251 may be 0.1um, 0.2um, 0.3um, 0.4 um or 0.5um. The pitch of the adjacent through holes 251 may be greater than or equal to 2um, for example, the pitch of the adjacent through holes 251 may be 2um, 5um, 10um, 15um, or the like.
As an example, the shielded gate power device may further include: body regions (not shown) on opposite sides of the trench 21; a source (not shown) located within the body region; a gate electrode (not shown) electrically connected to the gate electrode 25; a drain electrode (not shown) extending through the source and into the body region; a drain electrode (not shown) electrically connected to the lower surface of the semiconductor layer 10. Specifically, the drain electrode may be located on the lower surface of the semiconductor layer 10.
It should be understood that, although the steps in the flowcharts related to the above embodiments are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (6)
1. A shielded gate power device, comprising:
a semiconductor layer;
a trench within the semiconductor layer;
the shielding grid is positioned in the groove, and the upper surface of the shielding grid is lower than the top surface of the groove;
the grid electrode is positioned in the groove and above the shielding grid electrode, and has a distance with the shielding grid electrode; the grid is internally provided with a through hole which penetrates through the grid from top to bottom and is communicated with the air cavity; the number of the through holes is multiple, and the through holes are arranged in an array;
an air cavity located within the trench and between the gate and the shield gate to isolate the gate from the shield gate;
filling a dielectric layer to fill all the through holes;
and the medium layer is covered to cover the inner wall of the air cavity.
2. The shielded gate power device of claim 1, further comprising:
the field oxide layer is positioned below the air cavity, is positioned between the shielding grid electrode and the semiconductor layer, and covers the bottom and part of the side wall of the shielding grid electrode;
and the gate oxide layer is positioned above the air cavity, is positioned between the gate and the semiconductor layer and covers the side wall of the gate.
3. The shielded gate power device of claim 2 wherein an upper surface of the shielded gate is higher than an upper surface of the field oxide layer.
4. The preparation method of the shielded gate power device is characterized by comprising the following steps:
providing a semiconductor layer;
forming a groove in the semiconductor layer;
forming a shielding grid in the groove, wherein the upper surface of the shielding grid is lower than the top surface of the groove;
forming a grid electrode and an air cavity in the groove, wherein the method comprises the following steps of: forming a sacrificial layer in the groove, wherein the sacrificial layer is positioned above the shielding grid electrode; the upper surface of the sacrificial layer is lower than the top surface of the groove; forming a grid electrode on the upper surface of the sacrificial layer; forming a through hole in the grid electrode, wherein the through hole exposes the sacrificial layer; the number of the through holes is multiple, and the through holes are arranged in an array; removing the sacrificial layer based on the through hole to form the air cavity;
forming a filling medium layer in the through hole, and forming a covering medium layer covering the inner wall of the air cavity on the inner wall of the air cavity;
the grid electrode is positioned above the shielding grid electrode and is spaced from the shielding grid electrode; the air cavity is located between the grid and the shielded grid to isolate the grid from the shielded grid.
5. The method of manufacturing a shielded gate power device of claim 4, further comprising, prior to forming a shielded gate in the trench: forming a field oxide material layer on the upper surface of the semiconductor layer, the side wall and the bottom of the groove; the shielding grid electrode is formed on the surface, far away from the semiconductor layer, of the field oxide material layer;
after forming the shielding grid electrode in the groove, the method further comprises the following steps: and removing the field oxide material layer on the upper surface of the semiconductor layer and on the upper side wall of the groove to obtain a field oxide layer, wherein the field oxide layer coats the bottom and part of the side wall of the shielding grid electrode.
6. The method of claim 4, further comprising, after forming a sacrificial layer in the trench and before forming a gate with an upper surface of the sacrificial layer: forming a gate oxide layer on at least the exposed side wall of the groove; the grid electrode is formed on the surface of the grid oxide layer far away from the semiconductor layer.
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