CN116864383A - Preparation method of shielded gate power device and shielded gate power device - Google Patents

Preparation method of shielded gate power device and shielded gate power device Download PDF

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Publication number
CN116864383A
CN116864383A CN202310877606.2A CN202310877606A CN116864383A CN 116864383 A CN116864383 A CN 116864383A CN 202310877606 A CN202310877606 A CN 202310877606A CN 116864383 A CN116864383 A CN 116864383A
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CN
China
Prior art keywords
gate
groove
layer
grid electrode
power device
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Pending
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CN202310877606.2A
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Chinese (zh)
Inventor
高学
柴展
罗杰馨
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Shanghai Gongcheng Semiconductor Technology Co Ltd
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Shanghai Gongcheng Semiconductor Technology Co Ltd
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Priority to CN202310877606.2A priority Critical patent/CN116864383A/en
Publication of CN116864383A publication Critical patent/CN116864383A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Abstract

The invention provides a shielded gate power device and a preparation method thereof, wherein the preparation method of the shielded gate power device comprises the following steps: providing a semiconductor layer; forming a groove in the semiconductor layer; forming a shielding grid in the groove, wherein the upper surface of the shielding grid is lower than the top surface of the groove, and a part of material of one side, close to the grid, of the shielding grid is removed to form at least one groove; and forming a grid electrode in the groove, wherein the grid electrode is positioned above the shielding grid electrode. According to the preparation method of the shielded gate power device, the at least one groove is formed in the shielded gate structure, so that the relative area between the gate and the shielded gate is reduced, the capacitance Cgs between polar plates is reduced, the input capacitance is reduced, the switching speed is increased, and the loss is reduced.

Description

Preparation method of shielded gate power device and shielded gate power device
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a preparation method of a shielded gate trench power device and the shielded gate power device.
Background
In power MOSFET devices, shield gate trench MOSFETs are receiving increasing attention because of their lower on-resistance and faster switching speed than conventional trench MOSFETs. In order to improve the voltage endurance capability of the device and reduce the internal resistance of the device, shielded gate trench MOSFETs with various structures sequentially appear, as shown in fig. 1, a schematic cross-sectional structure of a trench structure of the shielded gate trench MOSFET with an up-down structure includes a semiconductor layer 01, a trench 011, a field oxide 012, a shielded gate 013, a gate 014, and a gate oxide 015.
In the patent with publication number CN115799307a, a developer proposes that an air cavity can be prepared between a gate conductive layer and a shielding gate layer as an isolation layer, and because air has a good isolation voltage-resistant effect due to air, and the dielectric constant is very low, on the basis of ensuring the inter-source voltage resistance of the device, the inter-gate voltage resistance of the device can be obviously improved, and the parasitic capacitance Cgs of the gate source can be greatly reduced, so that the switching speed of the device is improved, and the switching loss is reduced.
However, in some special application scenarios or in order to reduce cost, this problem cannot be solved by providing an air cavity in the shielded gate trench MOSFET structure, but the whole dielectric layer entirely surrounds the gate shielding layer, so that the developer is forced to reduce the gate-source parasitic capacitance Cgs from other angles.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a shielded gate power device and a method for manufacturing the same, which aims to solve the problem that parasitic capacitance Cgs is generated between gate sources due to the fact that an isolation medium layer is arranged between a gate and a shielded gate for isolation in the shielded gate trench MOSFET in the prior art, so that the switching performance of the device is greatly affected.
In a first aspect, the present invention provides a method for manufacturing a shielded gate power device, including:
providing a semiconductor layer;
forming a groove in the semiconductor layer;
forming a shielding grid in the groove, wherein the upper surface of the shielding grid is lower than the top surface of the groove, and a part of material of one side, close to the grid, of the shielding grid is removed to form at least one groove;
and forming a grid electrode in the groove, wherein the grid electrode is positioned above the shielding grid electrode.
According to the preparation method of the shielded gate power device, the at least one groove is formed in the shielded gate structure, so that the relative area between the gate and the shielded gate is reduced, the capacitance Cgs between polar plates is reduced, the input capacitance is reduced, the switching speed is increased, and the loss is reduced.
In one embodiment, before forming the shielding gate in the trench, the method further includes:
forming a field oxide material layer on the side wall and the bottom of the groove on the upper surface of the semiconductor layer;
the shielding grid electrode is formed on the surface, away from the semiconductor layer, of the field oxide material layer.
In one embodiment, forming a shield gate within the trench includes:
filling a shielding grid electrode material on the field oxide material layer to form a shielding grid electrode material layer;
depositing a silicon nitride material on the shielding grid electrode material layer and etching back to form a silicon nitride side wall;
and etching the shielding grid electrode material layer, forming a groove by removing material in the area which is not covered and protected by the silicon nitride side wall, and etching the shielding grid electrode material layer into a shielding grid electrode with the groove.
In one embodiment, after forming the shielding gate in the trench, the method further includes:
removing the silicon nitride side wall;
removing part of the material of the field oxide material layer far away from the bottom of the groove so that the height of the field oxide material layer is lower than the upper surface of the shielding grid electrode;
and depositing materials on the field oxide material layer and the shielding grid electrode and etching back to form an inter-grid oxide layer.
In one embodiment, the inter-gate oxide layer and the field oxide material layer encapsulate the shield gate.
In one embodiment, forming the gate in the trench specifically includes:
forming a gate oxide layer on the upper side wall, far away from the inter-gate oxide layer, of the trench in a surface growth manner;
and depositing a material on the inter-gate oxide layer and etching back to form a gate.
In another aspect, the present invention further provides a shielded gate power device, including:
a semiconductor layer;
a trench in the semiconductor layer;
the shielding grid is positioned in the groove, and the upper surface of the shielding grid is lower than the top surface of the groove;
the grid electrode is positioned in the groove and above the shielding grid electrode, and has a distance with the shielding grid electrode;
wherein, shielding grid is close to the grid one side is equipped with at least one recess.
According to the shielded gate power device, the at least one groove is formed in the shielded gate structure, so that the relative area between the gate and the shielded gate is reduced, the capacitance Cgs between polar plates is reduced, the input capacitance is reduced, the switching speed is increased, and the loss is reduced.
In one embodiment, a recess is formed in a side of the shield gate adjacent to the gate, and the recess has a depth of 2000 angstroms.
In one embodiment, the width of the groove opening is larger than 1000 angstroms, and the single side at the top of the shielding grid is larger than 500 angstroms.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the prior art, a brief description of the drawings is provided below, wherein it is apparent that the drawings in the following description are some, but not all, embodiments of the present invention. Other figures may be derived from these figures without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic cross-sectional structure of a prior art shielded gate trench MOSFET;
fig. 2 is a flowchart of a method for manufacturing a shielded gate power device according to an embodiment of the present invention;
fig. 3 to fig. 9 are schematic structural diagrams of an intermediate state of a shielded gate power device in a method for manufacturing the shielded gate power device according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a shielded gate power device according to an embodiment of the present invention.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
In power MOSFET devices, shield gate trench MOSFETs are receiving increasing attention because of their lower on-resistance and faster switching speed than conventional trench MOSFETs. In order to improve the voltage endurance capability of the device and reduce the internal resistance of the device, shielded gate trench MOSFETs with various structures sequentially appear, as shown in fig. 1, a schematic cross-sectional structure of a trench structure of the shielded gate trench MOSFET with an up-down structure includes a semiconductor layer 01, a trench 011, a field oxide 012, a shielded gate 013, a gate 014, and a gate oxide 015.
In the patent with publication number CN115799307a, a developer proposes that an air cavity can be prepared between a gate conductive layer and a shielding gate layer as an isolation layer, and because air has a good isolation voltage-resistant effect due to air, and the dielectric constant is very low, on the basis of ensuring the inter-source voltage resistance of the device, the inter-gate voltage resistance of the device can be obviously improved, and the parasitic capacitance Cgs of the gate source can be greatly reduced, so that the switching speed of the device is improved, and the switching loss is reduced.
However, in some special application scenarios or in order to reduce cost, no isolation layer is provided in the shielded gate trench MOSFET structure, but the whole dielectric layer entirely surrounds the gate shielding layer, so that the developer is forced to reduce the gate-source parasitic capacitance Cgs from other angles.
Based on the problems existing in the prior art, the embodiment of the invention provides a preparation method of a shielded gate trench power device and the shielded gate trench power device.
In one embodiment, referring to fig. 2, the present invention provides a method for manufacturing a shielded gate power device, including:
s10: providing a semiconductor layer;
s20: forming a groove in the semiconductor layer;
s30: forming a shielding grid in the groove, wherein a part of material of the shielding grid close to one side of the grid is removed to form at least one groove, and the upper surface of the shielding grid is lower than the top surface of the groove;
s40: forming a gate in the trench, wherein the gate is located above the shielding gate
According to the preparation method of the shielded gate power device, the at least one groove is formed in the shielded gate structure, so that the relative area between the gate and the shielded gate is reduced, the capacitance Cgs between polar plates is reduced, the input capacitance is reduced, the switching speed is increased, and the loss is reduced.
Referring to fig. 3, in one alternative embodiment, S10 specifically includes,
s101: providing a semiconductor layer 20;
s102: oxide is deposited on semiconductor layer 20 as masking layer 30 in preparation for the next trench formation.
Referring to fig. 4, in an alternative embodiment, S20 specifically includes performing photolithography and etching operations on the semiconductor layer 20 covered by the mask layer 30, so as to form the trench 21.
Referring to fig. 5, in one embodiment, S30 further includes, before forming the shielding gate in the trench:
forming a field oxide material layer 40 on the upper surface of the semiconductor layer 20 and on the side walls and the bottom of the trench 21; before this, it is also necessary to remove the mask layer 30 originally formed for forming the trench 21.
The shield gate is formed on the surface of the field oxide material layer 40 away from the semiconductor layer 20.
Referring to fig. 6, in one alternative embodiment, step S30 specifically includes,
s301: filling a shielding gate material on the field oxide material layer 40 to form a shielding gate material layer 23;
s302: referring to fig. 7, a silicon nitride material is deposited on the shielding gate material 23 and etched back to form the silicon nitride sidewall 24, and it should be noted that the sidewall 24 may be made of other nitride materials, and silicon nitride is only one of them, and is not limited thereto.
S303: with continued reference to fig. 7, the shielding gate material layer 23 is etched, and the recess 25 is formed by removing material from the region not covered and protected by the silicon nitride sidewall 24, and the shielding gate material layer 23 is etched to form a shielding gate with the recess 25.
As an example, the grooves 25 may be provided in one, two, or other numbers, and when a plurality of grooves 25 are provided, the grooves 25 may be uniformly or unevenly arranged as needed.
By way of example, the semiconductor layer 20 may be at least one doped layer, such as to be at least one epitaxially doped layer; at this time, the semiconductor layer 20 may be formed on a substrate (not shown). Of course, in other examples, the semiconductor layer 20 may also be a doped substrate. Note that, the doping concentration range in the semiconductor layer 20 may be set according to the actual situation, which is not limited herein.
By way of example, the material of the semiconductor layer 20 may include, but is not limited to, silicon germanium, silicon carbide, gallium nitride, or other suitable semiconductor materials, and the like.
Referring to fig. 8, in one alternative embodiment, step 30 further includes, after forming a shield gate in the trench:
s31: removing the silicon nitride side wall 24;
s32: a portion of the field oxide material layer 40 away from the bottom of the trench 21 is removed so that the height of the field oxide material layer 40 is lower than the upper surface of the shield gate, and alternatively, the process of removing the field oxide layer may be a wet etching process.
S33: referring to fig. 9, material is deposited and etched back over the field oxide material layer 40 and the shield gate to form an inter-gate oxide layer 26.
With continued reference to fig. 9, in one embodiment, the inter-gate oxide 26 and the field oxide material layer 40 encapsulate the shield gate.
Referring to fig. 10, in one alternative embodiment, step 40 of forming a gate in the trench specifically includes:
s401: forming a gate oxide layer 27 in the trench 21 and away from the upper sidewall of the inter-gate oxide layer 26 and the surface of the semiconductor layer 20;
s402: a material is deposited and etched back on the inter-gate oxide layer 26 to form a gate 28.
The subsequent processes also include P body implant, N plus implant, ILD deposition, CT lithography, aluminum layer deposition, aluminum layer lithography, passivation layer deposition, passivation layer lithography, and the like, which are different from the conventional processes, and will not be described in detail.
In another embodiment, referring still to fig. 10, the present invention provides a shielded gate power device, comprising: a semiconductor layer 20; a trench 21 located in the semiconductor layer 20; a shielding gate (not labeled in the figure, corresponding to the shielding gate material layer going groove 25) located in the trench 21, wherein the upper surface of the shielding gate 23 is lower than the top surface of the trench 21; a gate 28 located within the trench 21 and above the shield gate with a spacing from the shield gate 23; the shielding grid is provided with at least one recess 25 near one side of the grid.
According to the shielded gate power device, the at least one groove is formed in the shielded gate structure, so that the relative area between the gate and the shielded gate is reduced, the capacitance Cgs between polar plates is reduced, the input capacitance is reduced, the switching speed is increased, and the loss is reduced.
By way of example, the semiconductor layer 20 may be at least one doped layer, such as to be at least one epitaxially doped layer; at this time, the semiconductor layer 20 may be formed on a substrate (not shown). Of course, in other examples, the semiconductor layer 20 may also be a doped substrate. Note that, the doping concentration range in the semiconductor layer 20 may be set according to the actual situation, which is not limited herein.
By way of example, the material of the semiconductor layer 20 may include, but is not limited to, silicon germanium, silicon carbide, gallium nitride, or other suitable semiconductor materials, and the like.
As an example, the depth of the trench 21 is smaller than the thickness of the semiconductor layer 20.
In an alternative embodiment, a groove 25 is formed on one side, close to the grid, of the shielding grid, and a part of area is lost after the shielding grid is slotted on one side, close to the grid;
in one alternative embodiment, a recess 25 is provided on a side of the shield gate 23 adjacent to the gate 28, the recess 25 having a depth of 2000 angstroms.
In one alternative embodiment, the opening width of the recess 25 is greater than 1000 angstroms, and the single side at the top of the shielding gate 23 is greater than 500 angstroms.
As can be seen from the inter-plate capacitance formula c=εrs/4πkd, the inter-plate capacitance is proportional to the relative area between the plates and inversely proportional to the distance between the plates. Providing the shield grid with grooves can be seen as reducing the relative area between the plates and thus the capacitance between the plates. The input capacitance of the device comprises Cgs and Cgd, and the size of the input capacitance influences the charge and discharge time of the gate capacitance, namely influences the gate switching speed. The smaller Cgs, the smaller the input capacitance, the faster the switching speed and the lower the losses.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (9)

1. The preparation method of the shielded gate power device is characterized by comprising the following steps:
providing a semiconductor layer;
forming a groove in the semiconductor layer;
forming a shielding grid in the groove, wherein the upper surface of the shielding grid is lower than the top surface of the groove, and a part of material of one side, close to the grid, of the shielding grid is removed to form at least one groove;
and forming a grid electrode in the groove, wherein the grid electrode is positioned above the shielding grid electrode.
2. The method for manufacturing a shielded gate power device of claim 1, further comprising, prior to forming a shielded gate in the trench:
forming a field oxide material layer on the side wall and the bottom of the groove on the upper surface of the semiconductor layer;
the shielding grid electrode is formed on the surface, away from the semiconductor layer, of the field oxide material layer.
3. The method of claim 2, wherein forming a shield gate in the trench comprises:
filling a shielding grid electrode material on the field oxide material layer to form a shielding grid electrode material layer;
depositing a silicon nitride material on the shielding grid electrode material layer and etching back to form a silicon nitride side wall;
and etching the shielding grid electrode material layer, forming a groove by removing material in the area which is not covered and protected by the silicon nitride side wall, and etching the shielding grid electrode material layer into a shielding grid electrode with the groove.
4. The method for manufacturing a shielded gate power device according to claim 3, further comprising, after forming a shielded gate in the trench:
removing the silicon nitride side wall;
removing part of the material of the field oxide material layer far away from the bottom of the groove so that the height of the field oxide material layer is lower than the upper surface of the shielding grid electrode;
and depositing materials on the field oxide material layer and the shielding grid electrode and etching back to form an inter-grid oxide layer.
5. The method for manufacturing a shielded gate power device according to claim 4, wherein,
the inter-gate oxide layer and the field oxide material layer cover the shielding gate.
6. The method for manufacturing a shielded gate power device according to claim 1, wherein forming a gate in the trench specifically comprises:
forming a gate oxide layer on the upper side wall, far away from the inter-gate oxide layer, of the trench and on the upper surface of the semiconductor layer;
and depositing a material on the inter-gate oxide layer and etching back to form a gate.
7. A shielded gate power device, comprising:
a semiconductor layer;
a trench in the semiconductor layer;
the shielding grid is positioned in the groove, and the upper surface of the shielding grid is lower than the top surface of the groove;
the grid electrode is positioned in the groove and above the shielding grid electrode, and has a distance with the shielding grid electrode;
wherein, shielding grid is close to the grid one side is equipped with at least one recess.
8. The shielded gate power device of claim 7 wherein a recess is provided in a side of the shielded gate adjacent the gate, the recess having a depth of 2000 angstroms.
9. The shielded gate power device of claim 8 wherein the recess opening width is greater than 1000 angstroms and the shield gate top single side is greater than 500 angstroms.
CN202310877606.2A 2023-07-17 2023-07-17 Preparation method of shielded gate power device and shielded gate power device Pending CN116864383A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310877606.2A CN116864383A (en) 2023-07-17 2023-07-17 Preparation method of shielded gate power device and shielded gate power device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310877606.2A CN116864383A (en) 2023-07-17 2023-07-17 Preparation method of shielded gate power device and shielded gate power device

Publications (1)

Publication Number Publication Date
CN116864383A true CN116864383A (en) 2023-10-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
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