CN116666433A - Shielding grid power device and manufacturing method thereof - Google Patents

Shielding grid power device and manufacturing method thereof Download PDF

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Publication number
CN116666433A
CN116666433A CN202310808751.5A CN202310808751A CN116666433A CN 116666433 A CN116666433 A CN 116666433A CN 202310808751 A CN202310808751 A CN 202310808751A CN 116666433 A CN116666433 A CN 116666433A
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China
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layer
polysilicon layer
gate polysilicon
shielding
top surface
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高学
柴展
罗杰馨
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Shanghai Gongcheng Semiconductor Technology Co Ltd
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Shanghai Gongcheng Semiconductor Technology Co Ltd
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Priority to CN202310808751.5A priority Critical patent/CN116666433A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application provides a shielding grid power device and a manufacturing method thereof, wherein the power device comprises a semiconductor layer, at least one unit cell unit and a metal layer, wherein the unit cell unit is positioned in the semiconductor layer and comprises an effective unit cell and a virtual unit cell, the effective unit cell is internally provided with a grid polycrystalline silicon layer and a first shielding grid polycrystalline silicon layer, the virtual unit cell is internally provided with a second shielding grid polycrystalline silicon layer, and the top surface of the second shielding grid polycrystalline silicon layer is flush with the top surface of the semiconductor layer; the metal layer is positioned above the semiconductor layer and comprises a source metal and a gate metal, the source metal is electrically connected with the first shielding gate polysilicon layer and the second shielding gate polysilicon layer, and the gate metal is electrically connected with the gate polysilicon layer. Compared with a common shielded gate power device, the shielded gate power device has the advantages that the FOM value is effectively reduced, the leakage channel and parasitic capacitance between the source and the drain are not increased, the problem of Idss leakage can be effectively avoided, the whole structure is simple and easy to realize, and the structural consistency and the performance stability of the device can be ensured.

Description

Shielding grid power device and manufacturing method thereof
Technical Field
The application belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to a shielded gate power device and a manufacturing method thereof.
Background
A shielded gate MOSFET (Shield Gate Transistor MOSFET, SGT-MOSFET for short) is an improvement on a deep trench MOSFET, and by adding a polysilicon electrode (called a shielding electrode) below a gate electrode and connecting the shielding electrode with a source electrode, most of gate-drain capacitance Cgd or Crss in the bottom of a traditional trench MOSFET is converted into gate-source capacitance Cgs, thereby realizing the functions of a shielded gate and a drift region and improving the switching speed of a device. Meanwhile, the shielding grid technology realizes charge coupling, reduces the critical electric field intensity of a drift region, reduces Rds (on) of the device, and reduces the switching loss. Compared with the common power device, the shielded gate trench MOSFET has the advantages of high integration level, on-resistance, high switching speed, small switching loss and the like, and is widely applied to various fields.
Currently, a Figure of Merit (FOM) is generally used as an index for measuring the performance of a power device, where the FOM is an on-resistance Rd (son) and a gate charge Q g Since higher FOM values affect the operating efficiency of the device, lower FOM values are better when selecting switching power MOSFETs. The on-resistance of the MOSFET includes a channel resistance, an accumulation layer resistance, a parasitic JFET resistance, a diffusion resistance, an epitaxial layer resistance, a substrate resistance, and a metal line contact resistance, wherein the main parts are the channel resistance and the epitaxial layer resistance, the channel resistance is dominant in the low-voltage MOS, and the epitaxial layer internal resistance is dominant in the high-voltage MOS. Currently, to produce low FOM devices, half of the cells are typically sacrificed, i.e., by a reduction of Q by a factor of two g At this time, the on-resistance only increases the channel resistance due to the channel reduction, that is, a half of the cell is sacrificed when the chip area is unchanged, Q g The Rdson is reduced by one time, and the FOM value is reduced by one time, referring to FIG. 1, a partial cross-sectional structure of a typical low FOM device is shown by shorting gate 1 and source metal 2 of half of the cells in the active region to change the gate of the cell to source, e.g. in the case of SGT 100V, after sacrificing half of the cells, Q g Reduce by one timeWhile Rdson increased only 1.3-fold, FOM decreased by 35%. However, the above method can reduce FOM, but brings other technical problems, such as increasing the leakage channel between source and drain, causing I dss An increase in leakage current and an increase in parasitic capacitance C ds 。
Therefore, how to provide a shielded gate power device and a manufacturing method thereof, so as to reduce the FOM value without increasing the leakage channel between the source and the drain, and effectively avoid the problem of increasing the Idss leakage current, is an important technical problem to be solved by those skilled in the art.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a shielded gate power device and a method for manufacturing the same, which are used for solving the problem that the leakage channel between source and drain increases when the FOM value of the power device is reduced in the prior art, resulting in I dss An increase in leakage current and an increase in parasitic capacitance C ds Is a problem of (a).
To achieve the above and other related objects, the present application provides a shielded gate power device including:
a semiconductor layer;
the device comprises a semiconductor layer, at least one unit cell unit, a first shielding grid and a second shielding grid, wherein the unit cell unit is positioned in the semiconductor layer and comprises effective unit cells and virtual unit cells which are arranged at intervals in the horizontal direction, the effective unit cells are provided with first grooves, grid polycrystalline silicon layers and first shielding grid polycrystalline silicon layers which are arranged at intervals in the first grooves, the virtual unit cells are provided with second grooves, second shielding grid polycrystalline silicon layers are arranged in the second grooves, and the top surfaces of the second shielding grid polycrystalline silicon layers are flush with the top surfaces of the semiconductor layer;
the metal layer is positioned above the semiconductor layer, the metal layer comprises source electrode metal and grid electrode metal which are arranged at intervals in the horizontal direction, the source electrode metal is electrically connected with the first shielding grid polycrystalline silicon layer and the second shielding grid polycrystalline silicon layer, and the grid electrode metal is electrically connected with the grid polycrystalline silicon layer.
Optionally, the top surface of the first shielding gate polysilicon layer is flush with the top surface of the second shielding gate polysilicon layer, and the gate polysilicon layer is disposed around the first shielding gate polysilicon layer.
Optionally, the top surface of the first shielding gate polysilicon layer is lower than the top surface of the second shielding gate polysilicon layer, and the gate polysilicon layer is located above the first shielding gate polysilicon layer.
Alternatively, the number of the cell units is plural, the plural cell units are arranged at intervals in the horizontal direction, and the effective cells are alternately arranged with the virtual cells.
The application also provides a manufacturing method of the shielded gate power device, which comprises the following steps:
providing a semiconductor layer and forming a first groove and a second groove in the semiconductor layer, wherein the first groove and the second groove are arranged at intervals in the horizontal direction, and the first groove and the second groove are opened from the top surface of the semiconductor layer and extend downwards;
forming a first shielding gate polysilicon layer in the first groove and a second shielding gate polysilicon layer in the second groove, wherein the top surface of the second shielding gate polysilicon layer is flush with the top surface of the semiconductor layer;
forming a gate polysilicon layer in the second trench, wherein the gate polysilicon layer is arranged at intervals with the first shielding gate polysilicon layer;
and forming a metal layer above the semiconductor layer, wherein the metal layer comprises source metal and gate metal which are arranged at intervals in the horizontal direction, the source metal is electrically connected with the first shielding gate polysilicon layer and the second shielding gate polysilicon layer, and the gate metal is electrically connected with the gate polysilicon layer.
Optionally, the top surface of the first shielding gate polysilicon layer is flush with the top surface of the second shielding gate polysilicon layer, and the gate polysilicon layer is disposed around the first shielding gate polysilicon layer.
Optionally, the top surface of the first shielding gate polysilicon layer is lower than the top surface of the second shielding gate polysilicon layer, and the gate polysilicon layer is located above the first shielding gate polysilicon layer.
Optionally, forming a first shielding gate polysilicon layer in the first trench and forming a second shielding gate polysilicon layer in the second trench includes the steps of:
forming a first oxide layer, wherein the first oxide layer is positioned on the top surface of the semiconductor layer, the inner wall of the first groove and the inner wall of the second groove;
forming a first polysilicon layer which is positioned above the first oxide layer and is also filled into the first groove and the second groove;
performing first etching to enable the top surface of the first polysilicon layer to be flush with the top surface of the semiconductor layer, wherein the part of the first polysilicon located in the second groove forms the second shielding gate polysilicon layer;
forming a first photoresist layer on the semiconductor layer and patterning the first photoresist layer to form a first etching window, wherein the first etching window is positioned above the first groove and exposes at least a part of a first polysilicon layer positioned in the first groove;
and performing second etching on the first polysilicon layer in the first groove based on the first etching window to obtain the first shielding gate polysilicon layer, wherein the top surface of the first shielding gate polysilicon layer is lower than the top surface of the second shielding gate polysilicon layer.
Optionally, forming a gate polysilicon layer in the second trench includes the steps of:
forming a second oxide layer on the top surface of the semiconductor layer, wherein the second oxide layer is also filled in the first groove;
planarizing to remove a first oxide layer portion over the semiconductor layer and a second oxide layer portion over the semiconductor layer;
forming a second photoresist layer on the semiconductor layer and patterning the second photoresist layer to form a second etching window, wherein the second etching window is positioned above the first groove, and the second etching window exposes a second oxide layer positioned in the first groove and a first oxide layer positioned on the side wall of the first groove;
performing third etching on the basis of the second etching window so that the top surface of the second oxide layer in the first groove is lower than the top surface of the semiconductor layer and at least one part of side wall of the first groove is exposed, and removing the second photoresist layer;
forming a third oxide layer, wherein the third oxide layer covers the exposed side wall of the first groove and the top surface of the semiconductor layer;
forming a second polysilicon layer over the semiconductor layer, the second polysilicon layer also filling into the first trench;
and performing a fourth etching to enable the top surface of the second polysilicon layer to be flush with the top surface of the semiconductor layer, wherein the part of the second polysilicon layer located in the first groove forms the gate polysilicon layer.
Alternatively, the method of forming the first oxide layer includes a thermal oxidation method, the method of forming the second oxide layer includes a high density plasma chemical vapor deposition method, and the method of forming the third oxide layer includes a thermal oxidation method.
As described above, compared with the common shielded gate power device, the shielded gate power device provided by the application has the advantages that the FOM value is effectively reduced, the leakage channel and parasitic capacitance between the source and the drain are not increased, the problem of Idss leakage can be effectively avoided, the whole structure is simple and easy to realize, and the structural consistency and the performance stability of the device can be ensured. The manufacturing method of the shielded gate power device has the advantages that the manufacturing process is simple and easy to realize, the extra manufacturing cost is not increased, and the low FOM value power device can be manufactured.
Drawings
FIG. 1 is a schematic diagram showing a partial cross-sectional structure of a typical low FOM device.
Fig. 2 is a schematic flow chart of steps of a method for manufacturing a shielded gate power device according to the present application.
Fig. 3 is a schematic cross-sectional view of a structure obtained after forming a mask layer in the method for manufacturing a shielded gate power device according to the present application.
Fig. 4 is a schematic cross-sectional view of a structure obtained after forming a first trench and a second trench in the method for manufacturing a shielded gate power device according to the present application.
Fig. 5 is a schematic cross-sectional view of a structure obtained after forming a first oxide layer in the method for manufacturing a shielded gate power device according to the present application.
Fig. 6 is a schematic cross-sectional view of a structure obtained after forming a first polysilicon layer in the method for manufacturing a shielded gate power device according to the present application.
Fig. 7 is a schematic cross-sectional view of a structure obtained after forming a first etching window in the method for manufacturing a shielded gate power device according to the present application.
Fig. 8 is a schematic cross-sectional view of a structure obtained after obtaining a second shielding gate polysilicon layer in the method for manufacturing a shielding gate power device of the present application.
Fig. 9 is a schematic cross-sectional view of a structure obtained after forming a second oxide layer in the method for manufacturing a shielded gate power device according to the present application.
Fig. 10 is a schematic cross-sectional view of a structure obtained by planarizing the second oxide layer and the first oxide layer in the method for manufacturing a shielded gate power device according to the present application.
Fig. 11 is a schematic cross-sectional view of a structure obtained after forming a second etching window in the method for manufacturing a shielded gate power device according to the present application.
Fig. 12 is a schematic cross-sectional structure of a structure obtained after etching based on a second etching window in the method for manufacturing a shielded gate power device according to the present application.
Fig. 13 is a schematic cross-sectional view of a structure obtained after forming a third oxide layer in the method for manufacturing a shielded gate power device according to the present application.
Fig. 14 is a schematic cross-sectional view of a structure obtained after forming a second polysilicon layer in the method for manufacturing a shielded gate power device according to the present application.
Fig. 15 is a schematic cross-sectional view showing a structure obtained after a gate polysilicon layer is obtained in the method for manufacturing a shielded gate power device according to the present application.
Fig. 16 is a schematic diagram showing a partial cross-sectional structure of a shielded gate power device according to the second embodiment of the application.
Fig. 17 is a schematic diagram showing a partial cross-sectional structure of a shielded gate power device according to the third embodiment of the application.
Description of element reference numerals
1. Grid electrode
2. Source metal
10. Semiconductor layer
101. Mask layer
102. A first oxide layer
103. First polysilicon layer
104. First photoresist layer
105. First etching window
106. A second oxide layer
107. Second photoresist layer
108. Second etching window
109. Third oxide layer
110. Second polysilicon layer
20. Cell unit
21. Effective cell
211. First groove
212. First shielding gate polysilicon layer
213. Gate polysilicon layer
22. Virtual cell
221. Second groove
222. Second shielding gate polysilicon layer
S1 to S4 steps
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
Please refer to fig. 2 to 17. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The embodiment provides a method for manufacturing a shielded gate power device, please refer to fig. 2, which shows a step flow chart of the manufacturing method, comprising the following steps:
s1: providing a semiconductor layer and forming a first groove and a second groove in the semiconductor layer, wherein the first groove and the second groove are arranged at intervals in the horizontal direction, and the first groove and the second groove are opened from the top surface of the semiconductor layer and extend downwards;
s2: forming a first shielding gate polysilicon layer in the first groove and a second shielding gate polysilicon layer in the second groove, wherein the top surface of the second shielding gate polysilicon layer is flush with the top surface of the semiconductor layer;
s3: forming a gate polysilicon layer in the second trench, wherein the gate polysilicon layer is arranged at intervals with the first shielding gate polysilicon layer;
s4: and forming a metal layer above the semiconductor layer, wherein the metal layer comprises source metal and gate metal which are arranged at intervals in the horizontal direction, the source metal is electrically connected with the first shielding gate polysilicon layer and the second shielding gate polysilicon layer, and the gate metal is electrically connected with the gate polysilicon layer.
As an example, the top surface of the first shielding gate polysilicon layer is lower than the top surface of the second shielding gate polysilicon layer, and the gate polysilicon layer is located above the first shielding gate polysilicon layer, and further, the top surface of the gate polysilicon layer is flush with the top surface of the first shielding gate polysilicon layer.
In yet another embodiment, the top surface of the first shielding gate polysilicon layer is flush with the top surface of the second shielding gate polysilicon layer, the gate polysilicon layer is disposed around the first shielding gate polysilicon layer, and further, the top surface of the gate polysilicon layer is flush with the top surface of the first shielding gate polysilicon layer.
Specific manufacturing steps of the shielded gate power device will now be described by taking a structure in which the top surface of the first shielded gate polysilicon layer is lower than the top surface of the second shielded gate polysilicon layer as an example, and specific manufacturing steps in which the top surface of the first shielded gate polysilicon layer is flush with the top surface of the second shielded gate polysilicon layer may be performed with reference to corresponding steps in this example, but some steps need to be adjusted.
Referring to fig. 3 to 4, step S1 is performed to provide a semiconductor layer 10 and form a first trench 211 and a second trench 221 in the semiconductor layer 10, wherein the first trench 211 and the second trench 221 are horizontally arranged at intervals, and the first trench 211 and the second trench 221 are opened from the top surface of the semiconductor layer 10 and extend downward.
As an example, providing a semiconductor layer 10 and forming the first trench 211 and the second trench 221 in the semiconductor layer 10 includes the steps of:
as shown in fig. 3, a semiconductor layer 10 is provided, and a mask layer 101 is formed on the top surface of the semiconductor layer 10;
as an example, the material of the semiconductor layer 10 includes silicon, silicon germanium, silicon carbide or other suitable semiconductor materials, and in addition, the semiconductor layer 10 may be a single substrate, or a single substrate and an epitaxial layer structure on the surface of the single substrate, where the doping type of the substrate and whether the epitaxial layer is formed are reasonably designed based on the conductivity type of the power device, and in this embodiment, the semiconductor layer 10 is a silicon wafer.
As an example, the mask layer 101 includes an oxide layer, a silicon nitride layer or other suitable film layers, and in this embodiment, the mask layer 101 is an oxide layer and the oxide layer is manufactured by a chemical vapor deposition method.
As shown in fig. 4, a photoresist layer (not shown in fig. 4) is formed and patterned, and the semiconductor layer 101 is etched based on the patterned photoresist layer to obtain a deep trench structure, where the deep trench structure includes the first trench 211 and the second trench 221, and the opening sizes and depths of the first trench 211 and the second trench 221 are reasonably designed based on actual needs, which is not limited herein. The step of removing the mask layer 101 is further included after the etching to obtain the first trench 211 and the second hook trench.
As an example, the number of the first grooves 211 and the second grooves 221 is plural, and the plurality of the first grooves 211 and the plurality of the second grooves 221 are alternately arranged at intervals in the horizontal direction, and the dimensions of the first grooves 211 and the second grooves 221 are preferably kept consistent.
Referring to fig. 5 to 8, step S2 is performed to form a first shielding gate polysilicon layer 212 in the first trench 211 and a second shielding gate polysilicon layer 222 in the second trench 221, wherein a top surface of the second shielding gate polysilicon layer 222 is level with a top surface of the semiconductor layer 10.
As an example, forming the first shielding gate polysilicon layer 212 in the first trench 211 and forming the second shielding gate polysilicon layer 222 in the second trench 221 includes the steps of:
as shown in fig. 5, a first oxide layer 102 is formed, and the first oxide layer 102 is located on the top surface of the semiconductor layer 10, the inner wall (including the side wall and the bottom wall) of the first trench 211, and the inner wall of the second trench 221.
As an example, the first oxide layer 102 is manufactured by a thermal oxidation method, and in other embodiments, the first oxide layer 102 may be manufactured by other methods, and serves as an oxygen layer for electrically isolating the first and second shielding gate polysilicon layers 212 and 222 formed later from the semiconductor layer around the corresponding trench (i.e., the semiconductor layer 10).
As shown in fig. 6, a first polysilicon layer 103 is formed, the first polysilicon layer 103 is located above the first oxide layer 102, and the first polysilicon layer 103 is further filled into the first trench 211 and the second trench 221, and a method for forming the first polysilicon layer 103 includes a chemical vapor deposition method, preferably a low pressure chemical vapor deposition method (LPCVD).
As shown in fig. 7, a first etching is performed so that the top surface of the first polysilicon layer 103 is flush with the top surface of the semiconductor layer 10, and the portion of the first polysilicon layer 103 located in the second trench 221 constitutes the second shield gate polysilicon layer 222; it should be noted that, in the practical production process, the top surface of the second shielding gate polysilicon layer 222 is not in a standard plane shape (for example, the middle portion of the top surface is recessed with respect to the edge portion), but the top surface of the second shielding gate polysilicon layer 222 may be approximately considered to be a plane and is flush with the top surface of the semiconductor layer 10.
A first photoresist layer 104 is formed on the semiconductor layer 10 and the first photoresist layer 104 is patterned to form a first etch window 105, the first etch window 105 being located above the first trench 211 and exposing at least a portion of the first polysilicon layer 103 located in the first trench 211.
As shown in fig. 8, the first polysilicon layer 103 in the first trench 211 is etched based on the first etching window 105 to obtain the first shielding gate polysilicon layer 212, and the top surface of the first shielding gate polysilicon layer 212 is lower than the top surface of the second shielding gate polysilicon layer 222. In addition, the step of removing the first photoresist layer 104 is further included after the etching to obtain the first shielding gate polysilicon layer 212.
Referring to fig. 9 to 15, step S3 is performed to form a gate polysilicon layer 213 in the second trench 221, where the gate polysilicon layer 213 is spaced apart from the first shielding gate polysilicon layer 212.
As an example, forming the gate polysilicon layer 213 in the second trench 221 includes the following steps:
as shown in fig. 9, a second oxide layer 106 is formed on the top surface of the semiconductor layer 101, and the second oxide layer 106 is further filled into the first trench 211;
as an example, the method for forming the second oxide layer 106 includes a high-density plasma chemical vapor deposition method, where the second oxide layer 106 is used to realize electrical isolation between the gate polysilicon layer 213 and the first shielding gate polysilicon layer 212 (equivalent to a field oxide layer in the conventional sense), and since the film quality of the second oxide layer 106 directly affects the device performance, the conventional method is to complete the intermediate oxide layer (the second oxide layer 106) and the gate oxide layer (the third oxide layer 109 formed subsequently) at one time by adopting a thermal oxidation method, however, in the process of growing the oxide layer by using the thermal oxygen method, if the furnace tube process parameter control capability is insufficient, it is easy to cause the thickness of the intermediate oxide layer to be insufficient, and the device Igss performance is affected, and then the oxide layer is etched back to a preset depth by using the high-density plasma chemical vapor deposition method (HDP-CVD), so that the problem that the thickness of the intermediate oxide layer is insufficient or the void exists in the middle of the film layer is avoided, and in other embodiments, the gap layer 106 is also formed by selecting the method to cover the second oxide layer 106 by a sufficient gap thickness, so that the gap can be fully ensured.
As shown in fig. 10, the portion of the first oxide layer 102 located above the semiconductor layer 10 and the portion of the second oxide layer 106 located above the semiconductor layer 10 are planarized to leave only the second oxide layer 106 located in the first trench 211 and the first oxide layer 102 located on the inner walls of the first trench 211 and the second trench 212, and the top surface of the second oxide layer 106 located in the first trench 211 is flush with the top surface of the semiconductor layer 10.
As shown in fig. 11, a second photoresist layer 107 is formed on the semiconductor layer 101 and the second photoresist layer 107 is patterned to form a second etching window 108, wherein the second etching window 108 is located above the first trench 211 and the second etching window 108 exposes the second oxide layer 106 located in the first trench 211 and the first oxide layer 102 located on the sidewall of the first trench 211;
as shown in fig. 12, a third etching is performed based on the second etching window 108 so that the top surface of the second oxide layer 106 located in the first trench 211 is lower than the top surface of the semiconductor layer 10 and at least a portion of the sidewall of the first trench 211 is exposed, and then the second photoresist layer 107 is removed;
as shown in fig. 13, a third oxide layer 109 is formed, and the third oxide layer 109 covers the exposed sidewalls of the first trench 211 and the top surface of the semiconductor layer 10;
as an example, the method for forming the third oxide layer 109 includes a thermal oxidation method, the third oxide layer 109 corresponds to a gate oxide layer, and is used for realizing a current path between the source and the drain, and the thickness of the third oxide layer 109 is controlled based on the process parameters of the thermal oxidation method.
As shown in fig. 14, a second polysilicon layer 110 is formed on the semiconductor layer 10, the second polysilicon layer 110 is further filled into the second trench 221, and the forming method of the second polysilicon layer 110 is preferably consistent with the forming method of the first polysilicon layer 103.
As shown in fig. 15, a fourth etching is performed so that the top surface of the second polysilicon layer 110 is flush with the top surface of the semiconductor layer 10, and the portion of the second polysilicon layer 110 located in the second trench 221 constitutes the gate polysilicon layer 213.
As an example, according to the different conductivity types of the power device to be formed, the method for manufacturing the shielded gate power device further includes a plurality of steps of forming a first conductivity type body region, a second conductivity type source region, a second conductivity type drain region, an interlayer dielectric layer, and forming a contact hole in the interlayer dielectric layer after forming the gate polysilicon layer 213, where the first conductivity type is P-type or N-type, and the second conductivity type is opposite to the first conductivity type, and in this embodiment, the first conductivity type is P-type, and the second conductivity type is N-type, that is, ion implantation is performed on an upper surface layer of the P-body region to form a source region of n+ after forming the P-body region in the semiconductor layer 10 by ion implantation.
Step S4 is performed, where a metal layer is formed above the semiconductor layer 10, the metal layer includes source metal and gate metal that are arranged at intervals in a horizontal direction, the source metal is electrically connected to the first shielding gate polysilicon and the second shielding gate polysilicon, and the gate metal is electrically connected to the gate polysilicon layer 213.
As an example, the metal layer may further include a step of forming a passivation layer and patterning the passivation layer after forming the metal layer, and the step may be performed by a conventional semiconductor film preparation method, which is not particularly limited herein.
The manufacturing method of the shielded gate power device is simple and easy to realize, does not increase extra manufacturing cost, and can manufacture the low FOM value power device.
Example two
The present embodiment provides a shielded gate power device, please refer to fig. 16, which is a schematic diagram of a partial cross-sectional structure of the shielded gate power device, and the power device may be manufactured by the manufacturing method described in the first embodiment or other suitable methods, and specifically includes a semiconductor layer 10, at least one unit cell 20 and a metal layer (not shown in fig. 16).
Specifically, the cell unit 20 is located in the semiconductor layer 10, the cell unit 20 includes an effective cell 21 and a dummy cell 22 that are arranged at intervals in a horizontal direction, the effective cell 21 has a first trench 211, the first trench 211 has a gate polysilicon layer 213 and a first shielding gate polysilicon layer 212 that are arranged at intervals, the dummy cell 22 has a second trench 221, the second trench 221 has a second shielding gate polysilicon layer 222, and a top surface of the second shielding gate polysilicon layer 222 is flush with a top surface of the semiconductor layer 10; the metal layer is located above the semiconductor layer 10, and the metal layer includes source metal and gate metal that are disposed at intervals in a horizontal direction, the source metal is electrically connected to the first shielding gate polysilicon layer 212 and the second shielding gate polysilicon layer 222, and the gate metal is electrically connected to the gate polysilicon layer 213.
As an example, the top surface of the first shielding gate polysilicon layer 212 is lower than the top surface of the second shielding gate polysilicon layer 222, the gate polysilicon layer 213 is located above the first shielding gate polysilicon layer 212, and further, the top surface of the gate polysilicon layer 213 is flush with the top surface of the first shielding gate polysilicon layer 212.
As an example, the number of the cell units 20 is plural, the plurality of cell units 20 are arranged at intervals in the horizontal direction, and the effective cells 21 are alternately arranged with the virtual cells 22. That is, the number of effective cells 21 and virtual cells 22 is the same in all cells in the active region, and the effective cells 21 and virtual cells 22 are arranged at intervals in the same cell unit 20, and the effective cells 21 and virtual cells 22 in adjacent two cells are also arranged at intervals, exhibiting a tendency that the effective cells 21 and virtual cells 22 are alternately arranged in the entire active region overall structure. It should be noted that, in other embodiments, in order to meet the performance requirements of the device in different applications, the cellular unit 20 may include more than one effective cellular unit 21 or more than one virtual cellular unit 22, and the effective cellular units 21 and the virtual cellular units 22 are not necessarily arranged alternately, and the specific arrangement manner is reasonably set according to the actual needs. In this embodiment, the effective cells 21 and the virtual cells 22 are alternately arranged, so that the manufacturing difficulty and process can be reduced, and the structural consistency and performance stability of the device can be ensured.
Compared with a common shielded gate power device, the shielded gate power device of the embodiment has the advantages that the FOM value is effectively reduced, the leakage channel and parasitic capacitance between the source and the drain are not increased, the problem of Idss leakage can be effectively avoided, the whole structure is simple and easy to realize, and the structural consistency and the performance stability of the device can be ensured.
Example III
Referring to fig. 17, a schematic cross-sectional structure of the shielded gate power device is shown, in which the height of the first shielded gate polysilicon layer and the positional relationship between the first shielded gate polysilicon layer and the gate polysilicon layer are different from each other in the corresponding structure in the second embodiment, and the shielded gate power device of the present embodiment specifically includes a semiconductor layer 10, at least one unit cell 20, and a metal layer (not shown in fig. 17).
Specifically, the cell unit 20 is located in the semiconductor layer 10, the cell unit 20 includes an effective cell 21 and a dummy cell 22 that are arranged at intervals in a horizontal direction, the effective cell 21 has a first trench 211, the first trench 211 has a gate polysilicon layer 213 and a first shielding gate polysilicon layer 212 that are arranged at intervals, the dummy cell 22 has a second trench 221, the second trench 221 has a second shielding gate polysilicon layer 222, and a top surface of the second shielding gate polysilicon layer 222 is flush with a top surface of the semiconductor layer 10; the metal layer is located above the semiconductor layer 10, and the metal layer includes source metal and gate metal that are disposed at intervals in a horizontal direction, the source metal is electrically connected to the first shielding gate polysilicon layer 212 and the second shielding gate polysilicon layer 222, and the gate metal is electrically connected to the gate polysilicon layer 213.
As an example, the top surface of the first shielding gate polysilicon layer 212 is flush with the top surface of the second shielding gate polysilicon layer 222, and the gate polysilicon layer 213 is disposed around the first shielding gate polysilicon layer 212, and further, the top surface of the gate polysilicon layer 213 is flush with the top surface of the first shielding gate polysilicon layer 212.
In summary, compared with the common shielded gate power device, the shielded gate power device provided by the application has the advantages that the FOM value is effectively reduced, the leakage channel and parasitic capacitance between the source and the drain are not increased, the problem of Idss leakage can be effectively avoided, the whole structure is simple and easy to realize, and the structural consistency and the performance stability of the device can be ensured. The manufacturing method of the shielded gate power device has the advantages that the manufacturing process is simple and easy to realize, the extra manufacturing cost is not increased, and the low FOM value power device can be manufactured. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A shielded gate power device, comprising:
a semiconductor layer;
the device comprises a semiconductor layer, at least one unit cell unit, a first shielding grid and a second shielding grid, wherein the unit cell unit is positioned in the semiconductor layer and comprises effective unit cells and virtual unit cells which are arranged at intervals in the horizontal direction, the effective unit cells are provided with first grooves, grid polycrystalline silicon layers and first shielding grid polycrystalline silicon layers which are arranged at intervals in the first grooves, the virtual unit cells are provided with second grooves, second shielding grid polycrystalline silicon layers are arranged in the second grooves, and the top surfaces of the second shielding grid polycrystalline silicon layers are flush with the top surfaces of the semiconductor layer;
the metal layer is positioned above the semiconductor layer, the metal layer comprises source electrode metal and grid electrode metal which are arranged at intervals in the horizontal direction, the source electrode metal is electrically connected with the first shielding grid polycrystalline silicon layer and the second shielding grid polycrystalline silicon layer, and the grid electrode metal is electrically connected with the grid polycrystalline silicon layer.
2. The shielded gate power device of claim 1, wherein: the top surface of the first shielding gate polysilicon layer is flush with the top surface of the second shielding gate polysilicon layer, and the gate polysilicon layer is arranged around the first shielding gate polysilicon layer.
3. The shielded gate power device of claim 1, wherein: the top surface of the first shielding gate polysilicon layer is lower than the top surface of the second shielding gate polysilicon layer, and the gate polysilicon layer is positioned above the first shielding gate polysilicon layer.
4. The shielded gate power device of claim 1, wherein: the number of the cell units is a plurality, the cell units are arranged at intervals in the horizontal direction, and the effective cells and the virtual cells are alternately arranged.
5. The manufacturing method of the shielded gate power device is characterized by comprising the following steps of:
providing a semiconductor layer and forming a first groove and a second groove in the semiconductor layer, wherein the first groove and the second groove are arranged at intervals in the horizontal direction, and the first groove and the second groove are opened from the top surface of the semiconductor layer and extend downwards;
forming a first shielding gate polysilicon layer in the first groove and a second shielding gate polysilicon layer in the second groove, wherein the top surface of the second shielding gate polysilicon layer is flush with the top surface of the semiconductor layer;
forming a gate polysilicon layer in the second trench, wherein the gate polysilicon layer is arranged at intervals with the first shielding gate polysilicon layer;
and forming a metal layer above the semiconductor layer, wherein the metal layer comprises source metal and gate metal which are arranged at intervals in the horizontal direction, the source metal is electrically connected with the first shielding gate polysilicon layer and the second shielding gate polysilicon layer, and the gate metal is electrically connected with the gate polysilicon layer.
6. The method for manufacturing the shielded gate power device according to claim 5, wherein: the top surface of the first shielding gate polysilicon layer is flush with the top surface of the second shielding gate polysilicon layer, and the gate polysilicon layer is arranged around the first shielding gate polysilicon layer.
7. The method for manufacturing the shielded gate power device according to claim 5, wherein: the top surface of the first shielding gate polysilicon layer is lower than the top surface of the second shielding gate polysilicon layer, and the gate polysilicon layer is positioned above the first shielding gate polysilicon layer.
8. The method of claim 7, wherein forming a first shield gate polysilicon layer in the first trench and forming a second shield gate polysilicon layer in the second trench comprises:
forming a first oxide layer, wherein the first oxide layer is positioned on the top surface of the semiconductor layer, the inner wall of the first groove and the inner wall of the second groove;
forming a first polysilicon layer which is positioned above the first oxide layer and is also filled into the first groove and the second groove;
performing first etching to enable the top surface of the first polysilicon layer to be flush with the top surface of the semiconductor layer, wherein the part of the first polysilicon located in the second groove forms the second shielding gate polysilicon layer;
forming a first photoresist layer on the semiconductor layer and patterning the first photoresist layer to form a first etching window, wherein the first etching window is positioned above the first groove and exposes at least a part of a first polysilicon layer positioned in the first groove;
and performing second etching on the first polysilicon layer in the first groove based on the first etching window to obtain the first shielding gate polysilicon layer, wherein the top surface of the first shielding gate polysilicon layer is lower than the top surface of the second shielding gate polysilicon layer.
9. The method of claim 8, wherein forming a gate polysilicon layer in the second trench comprises:
forming a second oxide layer on the top surface of the semiconductor layer, wherein the second oxide layer is also filled in the first groove;
planarizing to remove a first oxide layer portion over the semiconductor layer and a second oxide layer portion over the semiconductor layer;
forming a second photoresist layer on the semiconductor layer and patterning the second photoresist layer to form a second etching window, wherein the second etching window is positioned above the first groove, and the second etching window exposes a second oxide layer positioned in the first groove and a first oxide layer positioned on the side wall of the first groove;
performing third etching on the basis of the second etching window so that the top surface of the second oxide layer in the first groove is lower than the top surface of the semiconductor layer and at least one part of side wall of the first groove is exposed, and removing the second photoresist layer;
forming a third oxide layer, wherein the third oxide layer covers the exposed side wall of the first groove and the top surface of the semiconductor layer;
forming a second polysilicon layer over the semiconductor layer, the second polysilicon layer also filling into the first trench;
and performing a fourth etching to enable the top surface of the second polysilicon layer to be flush with the top surface of the semiconductor layer, wherein the part of the second polysilicon layer located in the first groove forms the gate polysilicon layer.
10. The method for manufacturing the shielded gate power device according to claim 9, wherein: the method for forming the first oxide layer comprises a thermal oxidation method, the method for forming the second oxide layer comprises a high-density plasma chemical vapor deposition method, and the method for forming the third oxide layer comprises a thermal oxidation method.
CN202310808751.5A 2023-07-03 2023-07-03 Shielding grid power device and manufacturing method thereof Pending CN116666433A (en)

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Application Number Priority Date Filing Date Title
CN202310808751.5A CN116666433A (en) 2023-07-03 2023-07-03 Shielding grid power device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310808751.5A CN116666433A (en) 2023-07-03 2023-07-03 Shielding grid power device and manufacturing method thereof

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CN116666433A true CN116666433A (en) 2023-08-29

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