KR100787814B1 - A X-ray detector and a method for fabricating thereof - Google Patents

Abstract

The present invention relates to an x-ray image sensing device, and more particularly, to an array substrate of the x-ray image sensing device (DXD) and a method of manufacturing the same.

The first array substrate of the image sensing device according to the present invention is configured to omit the organic passivation layer and to form a separate gate pad terminal electrode on the gate pad electrode, and the second array substrate omits the organic passivation layer and to the gate pad electrode and the data. A separate gate pad terminal electrode and a data pad terminal electrode are formed on the pad electrode.

The array substrate configuration of the image sensing device according to the present invention as described above can simplify the manufacturing process, and external signal wiring can be connected to the respective pad electrodes by using a wire bonding method and a tap bonding method.

Description

X-ray detector and a method for manufacturing the same             

1 is a cross-sectional view for explaining the operation of the X-ray image sensing device,

2 is a plan view showing one pixel area of a conventional image sensing device;

3A to 3J are cross-sectional views of the process of FIG. 2 taken along line I-I, II-II, III-III, IV-IV, and shown in a conventional process sequence;

4 is a plan view illustrating one pixel area of an image sensing device according to a first embodiment of the present invention;

5A through 5J are cross-sectional views illustrating a process sequence according to a first embodiment of the present invention, cut along VV, VI-VI, VIII-VIII, VIII-VIII of FIG. 4,

6 is a plan view illustrating one pixel area of an image sensing device according to a second embodiment of the present invention;

7A to 7H are cross-sectional views illustrating a process sequence according to a second embodiment of the present invention, cut along the lines VIII-VIII, VIII-XI, XI-XI, and XII-XII of FIG. 6.

<Explanation of symbols for main parts of drawing>

232: gate electrode 234: gate pad electrode

248: source electrode 250: drain electrode

251: gate wiring 252: data wiring

253: data pad electrode 254: ground wiring

255: ground pad electrode 260a, b: ground wiring contact hole

268: capacitor electrode 270: first gate pad terminal electrode

272: first data pad terminal electrode 274: first ground pad terminal electrode

292: second gate pad terminal electrode 294: second data pad terminal electrode

296: second ground pad terminal electrode

The present invention relates to an X-ray image sensing device using a TFT array process and a method of manufacturing the same.

The diagnostic method of a diagnostic X-ray (X-ray) device, which is widely used for medical purposes today, was photographed using an X-ray detection film, and it was necessary to pass a predetermined film print time in order to know the result.

However, in recent years, with the development of semiconductor technology, digital X-ray detectors (hereinafter referred to as "X-ray image sensing devices") using thin film transistors have been researched and developed. The X-ray image sensing device has an advantage of using a thin film transistor as a switching device, and diagnosing a result by displaying an X-ray image on a screen in real time immediately after the X-ray is photographed.

Hereinafter, the configuration and operation of the X-ray image sensing device will be described.

FIG. 1 is a schematic view illustrating the structure and operation of an X-ray image sensing device, in which a substrate 1 is formed below, a thin film transistor 3, a storage capacitor 10, a pixel electrode 12, and a photoconductive film 2. ), The protective film 20, the high voltage electrode 24, the high voltage DC power supply 26, and the like.

The photoconductive film 2 forms an electrical signal, ie, electron and hole pair 6, internally in proportion to an external signal intensity such as incident electric waves or magnetic waves. The photoconductive film 2 serves as a converter for converting an external signal, in particular, an X-ray into an electrical signal. The electron-hole pair 6 formed by the X-ray light is provided under the photoconductive film 2 by the voltage Ev applied from the high voltage DC power supply 26 to the high voltage electrode 24 positioned on the photoconductive film 2. The pixel electrodes 12 positioned are collected in the form of electric charges and stored in the storage capacitor 10 formed together with the capacitor electrodes grounded from the outside. At this time, the charge stored in the storage capacitor 10 is turned on by the gate signal applied to the gate of the thin film transistor 3 and turned on through the data line connected to the source of the thin film transistor 3. It is sent to an image processing circuit to produce an x-ray image.                         

In order to detect and convert even weak X-ray light into charge in the X-ray image sensing device, the number of trap state densities trapping charge in the photoconductive film 2 is reduced, and the thin film transistor 3 is turned off. The leakage current when there is to be reduced.

FIG. 2 is a plan view showing a pixel area of a conventional X-ray image sensing device, in which a gate line 51 constituting a gate pad electrode 34b is arranged in a row direction at one end thereof, and data at one end thereof. The data lines 52 constituting the pad electrodes 36b are arranged in the column direction crossing the gate lines 51.

The gate pad electrode 34b is connected to the gate line 51 through the gate connection line 34a, and the data pad electrode 36b is connected to the data line 52 through the data connection line 36a.

Further, the thin film transistor T is formed as a switching element at a portion where the gate wiring 51 and the data wiring 52 cross each other.

An area defined by the intersection of the data line 52 and the gate line 51 is called a pixel area P through which X-ray light is incident. In the pixel area P, a capacitor electrode 68 and a pixel electrode 74 are disposed. This is made up.

A ground wiring 54 is formed to be spaced apart from the gate wiring 51 by a predetermined distance, and the ground wiring 54 is formed under the capacitor electrode 68.

The ground wiring 54 and the capacitor electrode 68 are electrically connected to each other through the ground wiring contact holes 60a and 60b.                         

One end of the ground line 54 is configured with a ground pad electrode 37b for applying a ground signal from the outside, and the ground line 54 and the ground pad electrode 37b are connected through a ground connection line 37a. Connected.

In the above-described configuration, the drain auxiliary electrode 66 in contact with the drain electrode 50 is further formed.

The silicon nitride film SiN _X is interposed between the capacitor electrode 68 and the pixel electrode 74 to form a storage capacitor C as a charge storage means.

In addition, the gate pad electrode 34b, the data pad electrode 36b, and the ground pad electrode 37b are exposed through the contact holes 76, 78, and 80.

Here, the pixel electrode 74 extends to the upper portion of the thin film transistor T, and although not shown, holes generated in the photoconductive film 2 of FIG. 1 may be accumulated in the storage capacitor C. It serves as a collecting electrode to collect electric charges.

In addition, holes stored in the storage capacitor C move to the source electrode 48 through the drain electrode 50 and are processed in an external circuit (not shown) via the data wiring 52 to be represented as an image. . The detailed operation thereof is the same as described with reference to FIG.

3A to 3J are cross-sectional views taken along the cutting lines I-II, II-II, III-III, and IV-IV of FIG. 2 and shown in the process sequence of the present invention.

3A illustrates a process of forming a gate buffer 12, a data buffer 14, and a ground pad buffer 15 on a region where a gate pad electrode, a data pad electrode, and a ground pad electrode are to be formed.

The buffer layers 12, 14, and 15 are means for increasing the height of the gate pad electrode, the data pad electrode, and the ground pad electrode to be formed later.

The reason for raising the pad electrodes is to expose the pad electrodes without forming an auxiliary electrode on each pad electrode separately in the last step, so that the buffer layer is used so that external wirings can easily contact the pad electrodes. To increase the height of each pad electrode.

Since the buffer layers 12, 14, and 15 do not have an electrical function, they may be formed of an insulating material or a metal material.

FIG. 3B shows a double deposition and patterning of a conductive metal to form a gate electrode 32, a gate wiring (not shown), a gate pad electrode 34b, a data pad electrode 36b, and a ground pad electrode 37b having a dual structure. The forming step is shown.

The first metal layer of the double metal layer is a low-resistance aluminum (Al), aluminum alloy (mainly AlNd) and the like, the second metal layer is selected from molybdenum (Mo), chromium (Cr), tungsten (W). Use

The reason why each of the components is formed of a double metal layer is that as the gate electrode 32 material, aluminum having a low resistance is mainly used to reduce the RC delay, but pure aluminum has a low chemical corrosion resistance. Since it causes a wiring defect problem due to the formation of hillocks at a high temperature process, the laminated structure is applied as described above.

The metal of the two-layer structure is etched to form the gate electrode 32 and the gate wiring (not shown), the gate connection wiring 34a extending from the gate wiring (not shown), and the gate connection wiring. Data forming a gate pad electrode 34b covering the gate buffer 12 at an end of 34a, and covering the data buffer 14 at an end of the data connection line 36a and the data connection line 36a. A ground pad electrode 37b covering the ground pad buffer 15 is formed at the end of the pad electrode 36b, the ground connection line 37a, and the ground connection line 37a.

In this case, the gate pad electrode 34b, the data pad electrode 36b, and the ground pad electrode 37b may be a single layer in which a lower aluminum metal layer is exposed.

The reason for this is that the pad electrodes 34b, 36b, 37b on the buffer layers 12, 14, and 15 are bonded to the external wiring and receive a signal, and thus require low resistance. . Therefore, the lower aluminum layer having lower resistance than the upper layer having high resistance is used as the contact electrode.

Next, as shown in FIG. 3C, the substrate on which the gate electrode 32, the data pad electrode 36b, the ground pad electrode 37b, the gate pad electrode 34b, and the gate wiring (not shown) are formed 10) an inorganic insulating material group including a silicon nitride film (SiN _X ) and a silicon oxide film (SiO ₂ ) on the front surface, and in some cases, a benzocyclobutene (BCB) and an acrylic resin (resin) A gate insulating film 38 is formed to a thickness of 100 kV to 3000 kV by depositing or applying one selected from the group of organic insulating materials.

FIG. 3D illustrates a step of forming the active layer 40 and the ohmic contact layer 42.

First, pure amorphous silicon (A-Si: H) and impurity amorphous silicon (n + a-Si :) are continuously formed on the gate insulating film 38 while the gate insulating film 38 is not exposed to external air. H) is stacked in order and patterned to form an active layer 40 and an ohmic contact layer 42.

Next, the data insulating contact hole 46 and the ground wiring contact hole 47 are formed by etching the upper portion of the data connection line 36a and the gate insulating layer 38 above the ground connection line 37a.

3E illustrates a source metal 48 in contact with the ohmic contact layer 42 by forming and patterning a second metal layer on the gate insulating layer 38 on which the active layer 40 and the ohmic contact layer 42 are formed. And a data line 52 connected to the drain electrode 50 and the source electrode 48.

At the same time, the ground line 54 is formed in parallel with the data line 52.

In this structure, one end of the data line 52 contacts the data connection line 36a through the data line contact hole 46, and one end of the ground line 54 contacts the ground line contact hole. In contact with the ground connection wiring (37a) through (47).

Next, the ohmic contact layer 42 exposed between the source and drain electrodes is etched using the patterned source and drain electrodes 48 and 50 as a mask to expose a portion of the active layer 40.

Alternatively, the ohmic contact layer 42 may be etched away while the source and drain electrodes 48 and 50 are patterned using a photoresist (not shown) photomask, and the photoresist is not removed.

The exposed surface of the active layer 40 functions as a channel through which electrons flow.

FIG. 3F illustrates a step of forming a first passivation layer 56 on the entire surface of the substrate 10 on which the source and drain electrodes 48 and 50, the ground wiring 54, the data wiring 52, and the like are formed. .

The first passivation layer 56 is formed to have a thickness of 500 kV to 1300 kV by depositing a silicon insulating film (silicon nitride (SiN _x ) or silicon oxide (SiO ₂ )) by a predetermined method.

As such, when the first passivation layer, which is a layer in direct contact with the exposed active layer 40, is formed of a silicon insulating layer, the electrons are attracted because the interface property between the exposed active layer 40 and the first passivation layer 56 is excellent. The area to be trapped becomes smaller, and therefore, the result is that the mobility of electrons becomes faster. In addition, it is possible to prevent an increase in leakage current due to direct contact between the second protective film made of the organic insulating film to be formed later and the channel.

The first passivation layer 56 may be patterned to expose a portion of the drain electrode 50 and a portion of the ground line 54 to expose the first drain contact hole 58a and the first contact control line contact hole, respectively. 60a).

3G is a step of forming a second passivation layer 64, which is a transparent organic layer, on the patterned first passivation layer 56.

That is, the second passivation layer may be coated on the first passivation layer 56 by applying one selected from the group of transparent organic insulating materials including benzocyclobutene (BCB), acryl resin, etc. to 1 μm to 1.5 μm. Form 64.

Before the organic insulating material is applied, the thin film transistor region in which the thin film transistor T is formed is higher than the pixel region in which the pixel electrode is to be formed, as shown in FIG. 3F. However, by coating the organic insulating material to form the second passivation layer 64, the surfaces of these two regions may be flattened from the substrate 10 at the same height.

Subsequently, a second protective film 64 in a portion corresponding to the first drain contact hole (58a of FIG. 3F) and the first ground wiring contact hole (60a of FIG. 3F) is etched to form the drain electrode 50. The second drain contact hole 58b and the second ground contact hole 60b are formed to expose the over-ground wiring 54 again.

In this case, each of the first and second drain contact holes (58a and 58b of FIG. 3F) and the first and second ground contact holes (60a and 60b of FIG. 3F) are exposed to the same mask, and then dry etching is used. The first passivation layer 56 and the second passivation layer 64 may be simultaneously etched and formed.

Next, FIG. 3H illustrates a drain as an etch stop layer on the drain electrode 50 and the ground line 54 respectively exposed through the second drain contact hole 58b and the second ground contact hole 60b as transparent electrodes. In this step, the auxiliary electrode 66 and the capacitor electrode 68 are formed.

That is, a drain auxiliary electrode 66 contacting the exposed drain electrode 50 by depositing and patterning a transparent conductive material such as indium tin oxide (ITO) on the patterned second passivation layer 64, and A capacitor electrode 68 is formed in contact with the exposed ground line 54.

The ground line 54 is formed to pass a part of the pixel (FIG. 3), but the capacitor electrode 68 is wider than the ground line 54 so as not to overlap with the data line 52, so that the entire pixel electrode. It overlaps with more than half of the area.

In this case, the drain auxiliary electrode 66 is formed to be wider than the third drain contact hole on the third passivation layer to be formed later.

Next, as shown in FIG. 3I, one of the above-described organic insulating material groups is deposited on the entire surface of the substrate 10 on which the drain auxiliary electrode 66 and the capacitor electrode 68 are formed to form a third passivation layer 72. ).

The third passivation layer 72 is patterned to form a third drain contact hole 58c exposing the drain auxiliary electrode 66.

As described above, the third drain contact hole 58c is formed to have a smaller area than the drain auxiliary electrode already formed. Since the drain auxiliary electrode 66 is formed on the drain electrode 50, damage to the drain electrode 50 can be prevented when the third drain contact hole 58c is formed.

Next, FIG. 3J illustrates a method of depositing and patterning a transparent conductive metal on the entire surface of the third passivation layer 72 to contact the exposed drain auxiliary electrode 66 and the upper portions of the source and drain electrodes 48 and 50. The pixel electrode 74 is formed on the pixel region P.                         

The pixel electrode 74 is formed to overlap the capacitor electrode 68 in a planar manner with the third passivation layer 72 interposed therebetween.

A storage layer C may be formed between the pixel electrode 74 and the capacitor electrode 68, and a storage capacitor C may be formed in the pixel region P, and the pixel electrode 74 may be a capacitor second. It also functions as an electrode.

Subsequently, the gate insulating layer 38, the first passivation layer 56, the second passivation layer 64, and the third passivation layer on the data pad electrode 36b, on the gate pad electrode 34b, and on the ground pad electrode 37b. The passivation layer 72 is etched to expose the lower gate pad electrode 34b, the data pad electrode 36b, and the ground wiring pad electrode 37b, respectively, and the gate pad contact hole 76 and the data pad contact hole 78. And the ground wiring contact hole 80 is formed.

Although the following process is not shown, the photosensitive material is applied, and the photosensitive material is used as a transducer which receives an external signal and converts the signal into an electrical signal. The compound of amorphous selenium is converted to 100 by using an evaporator. Deposit at -500 μm thickness. In addition, an X-ray photosensitive material having a low dark conductivity and sensitive to an external signal, particularly X-ray photoconductivity, may be used, such as HgI ₂ , PbO, CdTe, CdSe, thallium bromide, cadmium sulfide, and the like. When the X-ray light is exposed to the photosensitive material, electrons and hole pairs are generated in the photosensitive material according to the intensity of the exposed light.

After application of the X-ray photosensitive material, the metal layer is formed thin enough to transmit transparent conductive electrodes or X-ray light as high voltage electrodes.                         

When the X-ray light is applied while applying a voltage to the conductive electrode, electrons and hole pairs formed in the photosensitive material are separated from each other, and holes separated by the conductive electrode are collected in the pixel electrode 74 and stored in the storage capacitor C.

The thin film transistor array substrate for the X-ray image sensing device may be manufactured by the process as described above.

However, in the above-described configuration, since the process of forming the organic insulating film and the inorganic insulating film on the thin film transistor is continuously performed, the gate pad electrode and the gate pad electrode, There is a problem in that the data pad electrode and the auxiliary pad electrode and the external signal wiring should be connected only by a wire bonding method.

The present invention has been proposed to solve the above-described additional process problem and to diversify the method of connecting the external signal wiring to the pad electrode, and omit the organic protective layer on the thin film transistor, and at the same time, pad to the gate pad electrode. A first array substrate structure further comprising a terminal electrode, a second array substrate structure including a gate pad terminal electrode and a data pad terminal electrode formed on both the gate pad electrode and the data pad electrode while omitting the organic passivation layer, and a method of manufacturing the same. Suggest.

Each of the above-described configurations of the present invention simplifies the process and allows external signal wiring to be used for each pad electrode in both wire bonding and tapping.

The X-ray image sensing device according to the first aspect of the present invention for achieving the above object is a plurality of gate wirings formed in one direction on the substrate, a gate connection wiring connected to the gate wiring, and extending from the gate connection wiring A gate pad electrode; A data line defining a pixel region by crossing the gate line vertically with a gate insulating layer interposed therebetween, a data connection line connected to the data line, and a data pad electrode extending from the data connection line; A thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode at a point where the data line and the gate line cross each other; A ground line formed in the pixel area in one direction and having one end connected to a ground pad electrode; A first passivation layer covering the thin film transistor, the data pad electrode, and the ground pad electrode and exposing a portion of the ground wiring and a portion of the gate pad electrode; A capacitor electrode in contact with the exposed ground line and formed in the pixel region; A first gate pad terminal electrode formed in contact with the exposed gate pad electrode; A second passivation layer formed to expose a portion of the drain electrode and a portion of the first gate pad terminal electrode; A pixel electrode in contact with the drain electrode and a second gate pad terminal electrode in contact with the first gate pad terminal electrode; And a data pad contact hole exposing the data pad electrode and a ground pad contact hole exposing the ground pad electrode.

The gate electrode and the gate wiring are made of a double metal layer. The first layer of the double metal layer is aluminum, and the second layer is made of chromium (Cr), tungsten (W), and molybdenum (Mo).

The gate pad electrode, the data pad electrode, and the ground pad electrode are made of the same material on the same layer.

The data line and the ground line are formed in contact with the data connection line and the ground connection line through a contact hole formed in the gate insulating layer, and the pixel electrode extends to the upper portion of the source and drain electrodes.

According to an aspect of the present invention, there is provided a method of manufacturing an X-ray image sensing device, comprising: a gate wiring on a substrate, a gate connecting wiring extending from the gate wiring, a gate pad electrode extending from the gate connecting wiring, and a gate pad electrode; Forming a data connection line, a data pad electrode extending from the data connection line, a ground connection line, and a ground pad electrode extending from the ground connection line in one side of the non-parallel region; Forming a gate insulating film on a front surface of the substrate on which the gate wiring, the gate pad electrode, the data pad electrode, and the ground pad electrode are formed, a first insulating film exposing a portion of the gate connection line and a portion of the data connection line; ; A thin film transistor including an active layer, a source electrode, and a drain electrode formed at an intersection point of the data line crossing the gate line on the gate insulating layer, and a data line in contact with the exposed data connection line; Forming a ground line in contact with the connection line; Forming a first passivation layer on a front surface of the substrate on which the thin film transistor, the ground line, and the data line are formed, exposing a portion of the ground line and a portion of the gate pad electrode; Forming a capacitor electrode in contact with the ground wiring and a first gate pad terminal electrode in contact with the gate pad electrode; Exposing a portion of the drain electrode and the first gate pad electrode terminal on a front surface of the substrate on which the capacitor electrode and the first gate pad terminal electrode are formed, and etching the region corresponding to the ground pad electrode and the data pad electrode. Forming a second protective film that is a third insulating film; Forming a pixel electrode formed on the capacitor electrode while in contact with the drain electrode, and a second gate pad terminal electrode in contact with the first gate pad terminal electrode; Etching the first insulating film and the second insulating film in the region where the third insulating film is etched to form a data pad contact hole for exposing the data pad electrode and a ground pad contact hole for exposing the ground pad electrode. .

Forming a photoconductive film on the pixel electrode; The method may further include forming a conductive electrode on the photoconductive film.

The photoconductive film is formed of a material selected from the group consisting of amorphous selenium, HgI ₂ , PbO, CdTe, CdSe, thallium bromide, and cadmium sulfide.

The capacitor electrode, the pixel electrode, the first gate pad terminal electrode, and the second gate pad terminal electrode are formed of one selected from transparent indium tin oxide (ITO) and indium zinc oxide (IZO).

An X-ray image sensing device according to a second aspect of the present invention includes a gate wiring formed in one direction on a substrate, a gate pad electrode connected to the gate wiring; A data line defining a pixel area by vertically crossing the gate line with a gate insulating layer interposed therebetween, and a data pad electrode connected to the data line; A thin film transistor configured at a point where the gate wiring and the data wiring cross each other, the thin film transistor including a gate electrode, an active layer, a source electrode and a drain electrode; A ground line formed in one direction in the pixel area, and a ground pad electrode connected to the ground line; A silicon insulating layer formed on the substrate including the thin film transistor, the ground wiring, the data pad electrode, and the ground pad electrode, and exposing a part of the ground wiring, a portion of the gate pad electrode, the data pad electrode, and the ground pad electrode, respectively; Phosphorus first protective film; A capacitor electrode in contact with the exposed ground wiring, a first gate pad terminal electrode in contact with the gate pad electrode, a first data pad terminal electrode in contact with the data pad electrode, and a contact with the ground pad electrode 1 ground pad terminal electrode; A second passivation layer on the first passivation layer, the second passivation layer being a silicon insulating layer formed by exposing the drain electrode, the first gate pad terminal electrode, the first data pad terminal electrode, and the first ground pad terminal electrode; A pixel electrode formed on the capacitor electrode in contact with the drain electrode, a second gate pad terminal electrode in contact with the first gate pad terminal electrode, and a second data pad terminal electrode in contact with the first data pad terminal electrode. And a second ground pad terminal electrode in contact with the first ground pad terminal electrode.

A method of manufacturing an X-ray image sensing device according to a second aspect of the present invention includes forming a gate electrode and a gate wiring on a substrate and a gate pad electrode connected to the gate wiring; Forming a gate insulating film on the entire surface of the substrate on which the gate wiring is formed; A data line defining a pixel region crossing the gate line, a thin film transistor including an active layer, a source electrode, and a drain electrode formed at an intersection of the gate line and the data line, and a data pad electrode connected to the data line; Forming a ground line formed in one direction parallel to the data line and a ground pad electrode connected to the ground line; Exposing a portion of the ground line, a portion of the gate pad electrode, a portion of the data pad electrode, and a portion of the ground pad electrode on a front surface of the substrate on which the thin film transistor, the ground wiring, the data pad electrode, and the ground pad electrode are formed. Forming a first passivation film that is a second insulating film; A capacitor electrode in contact with the ground wiring, a first gate pad terminal electrode in contact with the gate pad electrode, a first data pad terminal electrode in contact with the data pad electrode, and a first ground in contact with the ground pad electrode Forming a pad terminal electrode; A portion of the drain electrode is exposed on the entire surface of the substrate on which the capacitor electrode, the first gate pad terminal electrode, the first data pad terminal electrode, and the first ground pad terminal electrode are formed, and the first gate pad terminal electrode and the first data are exposed. Forming a second protective film which is a third insulating film exposing the pad terminal electrode and the first ground pad terminal electrode; A pixel electrode formed on the capacitor electrode in contact with the drain electrode, a second gate pad terminal electrode in contact with the first gate pad terminal electrode, and a second data pad terminal in contact with the first data pad terminal electrode. Forming an electrode and a second ground pad terminal electrode in contact with the first ground pad terminal electrode.

Forming a photoconductive film on the pixel electrode; The method may further include forming a conductive electrode on the photoconductive film.                     

Hereinafter, the configuration and operation according to the embodiment of the present invention will be described with reference to the accompanying drawings.

First Embodiment

A feature of the first embodiment is to omit the organic insulating layer formed on the thin film transistor T, and to form a separate gate pad terminal electrode on the gate pad electrode, simplifying the process, and not only a wire bonding method but also a need. Therefore, an external signal line can be connected to the gate pad electrode by a tab (TAB) method.

Hereinafter, a first embodiment of the present invention will be described with reference to FIG. 4.

4 is a schematic plan view showing one pixel of the X-ray image sensing device according to the first embodiment of the present invention.

The gate wiring 151 constituting the gate pad electrode 134b is arranged in the row direction at one end, and the data wiring 152 constituting the data pad electrode 136b is arranged in the column direction at one end.

The gate pad electrode 134b is connected to the gate line 151 through the gate connection line 134a, and the data pad electrode 136b is connected to the data line 152 through the data connection line 136a.

In general, each of the connection lines 134a and 136a is formed between the pixel area P and the driving area (not shown).                     

In addition, the thin film transistor T is formed as a switching element at a portion where the gate wiring 151 and the data wiring 152 cross at right angles.

The capacitor electrode 162 and the pixel electrode 176 are formed in the pixel region P defined by the gate wiring 151 and the data wiring 152 crossing.

A ground wiring 154 is formed under the capacitor electrode, and the ground wiring 154 is in electrical contact with the capacitor electrode 162 through ground wiring contact holes 159a and 159b.

A ground pad electrode 137b is formed at an end of the ground wiring 154 and is connected through a ground connection wiring 137a.

In addition, a silicon nitride film SiN _X is interposed between the capacitor electrode 162 and the pixel electrode 176 as a dielectric material to form a storage capacitor C as a charge storage means.

In addition, the gate pad electrodes 134b are provided with separate gate pad terminal electrodes 166 and 178, so that the gate pad electrodes 134b and the external signal wirings can be connected in a tab manner.

Here, the pixel electrode 176 extends to the upper portion of the thin film transistor T, and although not shown, holes generated in the photoconductive film (2 of FIG. 1) may be accumulated in the storage capacitor C. It serves as a collecting electrode to collect electric charges.

In addition, holes stored in the storage capacitor C move to the source electrode 148 through the drain electrode 150 and are processed in an external circuit (not shown) via the data wiring 152 to be represented as an image. .

Hereinafter, a method of manufacturing DXD according to a first embodiment of the present invention will be described with reference to FIGS. 5A to 5J.

5A through 5J are cross-sectional views illustrating V-V, VI-VI, VIII-VIII and VIII-V in accordance with the process sequence of FIG. 4.

5A illustrates a process of forming a data buffer 104 and a ground pad buffer 105 on a region where a gate pad electrode, a data pad electrode, and a ground pad electrode are to be formed.

The buffers 104 and 105 are means for increasing the height of the data pad electrode and the ground pad electrode to be formed later.

The reason for raising the height of each pad electrode is as described above.

Since the buffer layers 104 and 105 do not have an electrical function, they may be formed of an insulating material or may be formed of a metal material.

5B illustrates a double deposition and patterning of a conductive metal to form a gate electrode 132, a gate wiring (not shown), a gate pad electrode 134b, a data pad electrode 136b, and a ground pad electrode 137b having a dual structure. The forming step is shown.

The first metal layer of the double metal layer is a low-resistance aluminum (Al), aluminum alloy (mainly AlNd) and the like, the second metal layer is selected from molybdenum (Mo), chromium (Cr), tungsten (W). Use

The reason for using each of the components as a double metal layer is that as the gate electrode 132 material, aluminum has a low resistance in order to reduce the RC delay, but pure aluminum has a low chemical resistance and subsequent corrosion. Since a wiring defect problem is caused by the formation of hillock in a high temperature process, the laminated structure is applied as described above.

The metal of the two-layer structure is etched to form the gate electrode 132 and the gate wiring (not shown), the gate connection wiring 134a extending from the gate wiring (not shown), and the gate connection wiring. A data pad electrode 136b which forms a gate pad electrode 134b at an end of 134a, and simultaneously covers the data buffer 104 at an end of the data connection line 136a and the data connection line 136a; A ground pad electrode 137b covering the ground pad buffer 105 is formed at the ends of the ground connection line 137a and the ground connection line 137a.

In this case, the gate pad electrode 134b, the data pad electrode 136b, and the ground pad electrode 137b may be a single layer in which a lower aluminum metal layer is exposed.

The reason for this is that each pad electrode 134b, 136b, 137b is bonded to an external wiring and receives a signal and thus requires a low resistance. Therefore, the lower aluminum layer having lower resistance than the upper layer having high resistance is used as the contact electrode.

Next, as shown in FIG. 5C, the substrate 100 having the gate electrode 132, the gate pad electrode 134b, the data pad electrode 136b, the ground pad electrode 137b, and the gate wiring 151 is formed. Inorganic insulating material group including a silicon nitride film (SiN _X ) and a silicon oxide film (SiO ₂ ) on the front of the), and in some cases, an organic material composed of benzocyclobutene (BCB) and acrylic resin (resin) A gate insulating layer 138 is formed to a thickness of 100 kV to 3000 kV by depositing or applying one selected from the group of insulating materials.

5D is a diagram illustrating a step of forming the active layer 140 and the ohmic contact layer 142.

First, pure amorphous silicon (A-Si: H) and impurity amorphous silicon (n + a-Si :) are continuously formed on the gate insulating film 138 while the gate insulating film 138 is not exposed to the outside air. H) is stacked in order and patterned to form the active layer 140 and the ohmic contact layer 142.

Next, the data insulating contact hole 146 and the ground wiring contact hole 147 are formed by etching the upper portion of the data connection line 136a and the gate insulating layer 138 on the ground connection line 137a.

FIG. 5E illustrates the deposition and patterning of a second metal layer on the gate insulating layer 138 on which the data wire contact hole 146, the ground pad contact hole 147, the active layer 140, and the ohmic contact layer 142 are formed. The source electrode 148 and the drain electrode 150 contacting the ohmic contact layer 142 and the data wiring 152 connected to the source electrode 148 are formed.

At the same time, a ground wiring 154 is formed across the center of the pixel region.

In this structure, one end of the data line 152 contacts the data connection line 136a through the data line contact hole 146, and one end of the ground line 154 contacts the ground line contact hole. In contact with the ground connection wiring 137a through 147.                     

Next, the ohmic contact layer 142 exposed between the source and drain electrodes 148 and 150 is etched using the patterned source and drain electrodes 148 and 150 as a mask to partially remove the active layer 140. Expose

Alternatively, the source and drain electrodes 148 and 150 may be patterned using a photoresist (not shown) photomask, and the ohmic contact layer 142 may be etched away without removing the photoresist.

The exposed surface of the active layer 140 functions as a channel through which electrons flow.

FIG. 5F illustrates a step of forming a first passivation layer 156 on the entire surface of the substrate 100 on which the source and drain electrodes 148 and 150, the ground line 154, the data line 152, and the like are formed.

The first passivation layer 156 is formed to have a thickness of about 4000 kV by depositing a silicon insulating layer (silicon nitride (SiN _x ) or silicon oxide (SiO ₂ )) by a predetermined method.

As such, when the first passivation layer, which is a layer in direct contact with the exposed active layer 140, is formed of a silicon insulating layer, the first active layer 140 may have excellent interfacial properties between the exposed active layer 140 and the first passivation layer 156. The area to be trapped becomes smaller, and therefore, the result is that the mobility of electrons becomes faster.

The first passivation layer 156 may be etched to expose a portion of the ground interconnection contact hole 154, and the first passivation layer 156 and the lower gate insulation layer 138 may be exposed. Etching to form a first gate pad contact hole 160a exposing the gate pad electrode 134b.

FIG. 5G illustrates a capacitor electrode 162 contacting the ground wiring 154 through the ground wiring contact hole 159 as a transparent electrode, and disposed on the data pad electrode 136a and the ground pad electrode 137a, respectively. A step of forming the first gate pad terminal electrode 166 in contact with the etch stoppers 164a and 164b and the gate pad electrode 134a is performed.

In other words, a transparent conductive material such as indium tin oxide (ITO) is deposited and patterned on the patterned first passivation layer 156.

The ground line 154 is formed to pass a portion of the pixel (FIG. 4), but the capacitor electrode 162 is wider than the ground line 154 so as not to overlap with the data line 152 so that the pixel electrode ( Formed in the process) and overlap with at least half of the total area.

Next, as shown in FIG. 5H, one of the above-described inorganic insulating material groups is deposited on the entire surface of the substrate 100 including the capacitor electrode 162 to form the second passivation layer 168. .

The etch star formed on the drain contact hole 170 exposing the drain electrode 150 and the data pad electrode 136b and the ground pad electrode 137b by patterning the second passivation layer 168. A first hole 172a and a second hole 172b exposing the etch stopers 164a and 164b are formed.

At the same time, a second gate pad contact hole 174 exposing a portion of the first gate pad terminal electrode 166 in contact with the gate pad electrode 134b is formed.                     

Next, FIG. 5I illustrates forming a pixel electrode 176 and a second gate pad terminal electrode 178 in contact with the first gate pad terminal electrode 166.

Deposition and patterning one selected from the group of transparent conductive metal materials including indium tin oxide (ITO) and indium zinc oxide (IZO) on the entire surface of the substrate 100 on which the contact holes 170 and 174 are formed. The pixel electrode 176 configured in the pixel region P while contacting the partially exposed drain electrode 150, and the second gate pad terminal electrode contacting the first gate pad terminal electrode 166 ( 178).

In this process, the etch stopper (164a in FIG. 5H and 164b in FIG. 5H) exposed through the first hole 172a and the second hole 172b is removed.

The pixel electrode 176 is formed to overlap the capacitor first electrode 162 with the second passivation layer 168 therebetween.

With the second passivation layer 168 inserted between the pixel electrode 176 and the storage first electrode 162, a storage capacitor C may be formed in the pixel region P. The pixel electrode Reference numeral 176 serves as the capacitor second electrode 176.

5J illustrates exposing the data pad electrode 136b and the ground pad electrode 137b. The first passivation layer 156 and the gate insulating layer 138 are etched to etch the data pad contact hole 180 and the ground pad contact. The hole 182 is formed.

The X-ray image sensing device according to the first embodiment of the present invention may be manufactured by the process as described above.

In the above-described process, unlike the conventional method, the organic passivation layer formed between the first passivation layer and the second passivation layer is removed, which not only simplifies the process but also separates the first gate pad terminal electrode 166 from the gate pad electrode 143b. ) And the second gate pad terminal electrode 178 without a process addition, so that the gate pad electrode 134b is tapped through the first gate pad terminal electrode 166 and the second gate pad terminal electrode 178. It can be connected to the external signal wiring.

Hereinafter, the configuration and manufacturing method of the X-ray image sensing device according to another feature of the present invention modified in the first embodiment through the second embodiment.

Second Embodiment

A feature of the second embodiment of the present invention is to simplify the process by omitting the organic insulating layer formed on the thin film transistor, and to form a terminal electrode on the gate pad electrode and the data pad electrode to connect external signal wiring in a tab manner. To make it possible.

6 is a plan view illustrating one pixel area of the X-ray image sensing device according to the second embodiment of the present invention.

As shown in the drawing, the gate wiring 251 constituting the gate pad electrode 234 is arranged in the row direction at one end thereof, and the data wiring 252 constituting the data pad electrode 253 is arranged in the column direction at one end thereof. Are arranged.

The gate pad electrode 234 is connected to the gate line 251 through the gate connection line 249, and the data pad electrode 253 is connected to the data line 252 through the data connection line 247.

The thin film transistor T is formed as a switching element at a portion where the gate wiring 251 and the data wiring 252 intersect.

An area defined by the intersection of the gate line 251 and the data line 252 is called a pixel area P, and the capacitor electrode 268 and the pixel electrode 290 are formed in the pixel area.

A ground line 254 parallel to the gate line 252 is formed under the pixel electrode 290.

The ground wire 254 contacts the capacitor electrode 268 through contact holes 260a and 260b, and a ground pad electrode 255 for applying a ground signal from the outside to one end of the ground wire 254. Configure

The ground pad electrode 255 is connected to the ground line 254 through a ground connection line 243.

In addition, a first gate pad terminal electrode 270 and a second gate pad terminal electrode 292 are formed on the gate pad electrode 234, and the first data pad terminal electrode 272 is formed on the data pad electrode 253. The second data pad terminal electrode 294 is formed.

A first ground pad terminal electrode 274 and a second ground pad terminal electrode 296 are formed on the ground pad electrode 255.

The capacitor electrode 268 and the pixel electrode 290 are formed to form the storage capacitor C as the charge storage means, and a silicon insulating layer is formed between the capacitor and the pixel electrodes 268 and 290 as a dielectric material. It is.

In addition, holes stored in the storage capacitor C move to the source electrode 248 through the drain electrode 250 by the operation of the thin film transistor T, and pass through an external circuit (not shown) through the data wiring 252. Is processed and represented as an image. The detailed operation thereof is the same as described with reference to FIG.

Hereinafter, a manufacturing process of the X-ray image sensing device according to the second embodiment of the present invention will be described with reference to FIGS. 7A to 7H.

7A to 7H are cross-sectional views illustrating a process sequence according to a second embodiment of the present invention, cut along the cutting lines VII-VII, VI-XI, XI-XI, and XII-XII of FIG. 6.

First, FIG. 7A illustrates a step of forming a double structured gate electrode 232 and a gate wiring (not shown) by depositing and patterning a conductive metal in duplicate.

Among the double metal layers, the first metal constituting the lower layer is made of low-resistance aluminum (Al), aluminum alloy (mainly AlNd), and the second metal constituting the upper layer is molybdenum (Mo), chromium (Cr), One selected from tungsten (W) is used.

A gate pad electrode 234 is formed at one end of the gate wiring while forming a gate wiring (not shown) with the gate electrode 232.

In this case, the gate pad electrode 234 and the gate line (not shown) are connected through the gate connection line 249.

Next, FIG. 7B illustrates silicon nitride (SiN _X ) formed on the entire surface of the substrate 200 on which the gate electrode 232, the gate pad electrode 234, the gate wiring (not shown), and the gate connection wiring 252 are formed. Depositing or applying one selected from the group of inorganic insulating materials including silicon oxide (SiO ₂ ) and optionally an organic insulating material group consisting of benzocyclobutene (BCB) and acrylic resin (resin) The gate insulating film 238 is formed to a thickness of 100 kV to 3000 kV.

FIG. 7C is a diagram illustrating the steps of forming the active layer 240 and the ohmic contact layer 242.

First, pure amorphous silicon (a-Si: H) and impurity amorphous silicon (n + a-Si: H) are sequentially formed on the gate insulating film 238 in a state where the insulating film is not exposed to the outside air. After stacking and patterning, the active layer 240 and the ohmic contact layer 242 are formed.

Next, FIG. 7D illustrates aluminum (Al), chromium (Cr), molybdenum (Mo), tungsten (W), and the like on the gate insulating layer 238 on which the active layer 240 and the ohmic contact layer 242 are formed. A source electrode 248 and a drain electrode 250 in contact with the ohmic contact layer 242, and a data line 252 connected to the source electrode 248 by depositing and patterning a selected one of the conductive metal groups including the conductive metal group. And a data pad electrode 253 extending from the end of the data line 252 to a predetermined area.

The data pad electrode 253 and the data line 252 are connected through a data connection line 247.

At the same time, a ground line 254 crossing the center of the pixel region P and a ground pad electrode 255 extending to a predetermined area are formed at the end of the ground line 254.

The ground line 254 and the ground pad electrode 255 are connected through a ground connection line 243.

Next, the ohmic contact layer 242 exposed between the source and drain electrodes 248 and 250 is etched using the patterned source and drain electrodes 248 and 250 as a mask to expose a portion of the active layer 240.

Alternatively, the source and drain electrodes 248 and 250 may be patterned using a photoresist (not shown) photomask, and the ohmic contact layer 242 may be etched away without removing the photoresist.

The exposed surface of the active layer 240 functions as a channel through which electrons flow.

FIG. 7E illustrates a step of forming the first passivation layer 256 on the entire surface of the substrate 200 on which the source and drain electrodes 248 and 250, the ground line 254, the data line 252, and the like are formed.

The first passivation layer 256 is formed by depositing a silicon insulating layer (silicon nitride (SiN _x ) or silicon oxide (SiO ₂ )) by a predetermined method to a thickness of 4000 kPa.

When the first passivation layer 256, which is a layer in direct contact with the exposed active layer 240, is formed of a silicon insulating layer, electrons are transferred because the interfacial property between the exposed active layer 240 and the first passivation layer 256 is excellent. The area to be trapped becomes smaller, and therefore, the result is that the mobility of electrons becomes faster.

The first passivation layer 256 may be patterned to expose a portion of the ground line 254, the gate pad electrode 234, the data pad electrode 253, and the ground pad electrode 255, respectively. A ground wiring contact hole 260a, a first gate pad contact hole 261a, a first data pad contact hole 263a, and a first ground pad contact hole 265a are formed.

FIG. 7F shows pad electrodes in contact with the exposed pads.

That is, in the transparent conductive metal material group including indium tin oxide (ITO) and indium zinc oxide (IZO) on the first passivation layer 256 having the contact holes 260a, 261a, 263a, and 265a. A capacitor electrode 268 in contact with the ground line 254, a first gate pad terminal electrode 270 in contact with the gate pad electrode 234, and the data pad electrode A first data pad terminal electrode 272 in contact with 253 and a first ground pad terminal electrode 274 in contact with the ground pad electrode 255 are formed.

Next, FIG. 7G illustrates a second passivation layer formed by depositing one selected from the group of inorganic insulating materials as described above on the entire surface of the substrate 200 on which the capacitor electrode 268 and the first gate pad terminal electrode 270 are formed. 280 is formed.

Subsequently, the second passivation layer 280 is patterned to form the drain electrode 250, the first gate pad terminal electrode 270, the first data pad terminal electrode 272, and the first ground pad terminal electrode. A drain contact hole 282, a second gate pad contact hole 261b, a second data pad contact hole 263b, and a second ground pad contact hole 265b exposing a portion of 274, respectively, are formed.

Next, FIG. 7H illustrates a pixel electrode 290 contacting the exposed drain electrode 250 by depositing and patterning a transparent conductive material such as indium tin oxide (ITO) on the patterned second passivation layer 280. And a second gate pad terminal electrode 292 in contact with the exposed first gate pad terminal electrode 270, and a second data pad terminal electrode in contact with the exposed first data pad terminal electrode 272 ( 294 and a second ground pad terminal electrode 296 in contact with the exposed first ground pad terminal electrode 274.

The pixel electrode 290 is planarly overlapped with the capacitor electrode 268 with the second passivation layer 280 therebetween. In this configuration, the storage capacitor C may be formed in the pixel region P, and the pixel electrode 290 also functions as a capacitor second electrode.

The structure of the second embodiment manufactured through the above process is simplified by omitting the organic insulating layer, and external signal wiring can be connected to both the gate pad electrode and the data pad electrode by using a tap method.

In the above-described first and second embodiments, the thickness of the first passivation film 256 is deposited at 4000 kPa, so that the step of forming an organic insulating film on the first passivation film can be omitted.

As described above, the X-ray image sensing device according to the first and second embodiments of the present invention can be manufactured.

As described above, the X-ray image sensing device formed by the manufacturing method according to the present invention has the following effects.

First, the organic insulating layer is omitted on the first passivation layer, and in the case of the second embodiment, the process of forming a buffer layer under each pad electrode is omitted, thereby simplifying the process.

Second, an external signal wiring can be connected to each pad electrode using a wire bonding method and a tap method.

Claims (26)

A plurality of gate lines formed in one direction on the substrate, a gate connection line connected to the gate line, and a gate pad electrode extending from the gate connection line; A data line defining a pixel region by crossing the gate line vertically with a gate insulating layer interposed therebetween, a data connection line connected to the data line, and a data pad electrode extending from the data connection line; A thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode at a point where the data line and the gate line cross each other; A ground line formed in the pixel area in one direction and having one end connected to a ground pad electrode; A first passivation layer covering the thin film transistor, the data pad electrode, and the ground pad electrode and exposing a portion of the ground wiring and a portion of the gate pad electrode; A capacitor electrode in contact with the exposed ground line and formed in the pixel region; A first gate pad terminal electrode formed in contact with the exposed gate pad electrode; A second passivation layer formed to expose a portion of the drain electrode and a portion of the first gate pad terminal electrode; A pixel electrode in contact with the drain electrode and a second gate pad terminal electrode in contact with the first gate pad terminal electrode; A data pad contact hole exposing the data pad electrode and a ground pad contact hole exposing the ground pad electrode X-ray image sensing device comprising a. The method of claim 1, And the gate electrode and the gate wiring are formed of a double metal layer. The method of claim 2, The first layer of the double metal layer is aluminum, the second layer is selected from the group of metals consisting of chromium (Cr), tungsten (W), molybdenum (Mo) X-ray image sensing device. The method of claim 1, And the gate pad electrode, the data pad electrode, and the ground pad electrode are made of the same material on the same layer. The method of claim 1, And the data line and the ground line are in contact with the data connection line and the ground connection line, respectively, through contact holes formed in the gate insulating layer. The method of claim 1, The pixel electrode extends to an upper portion of the source and drain electrodes. The method of claim 1, The first insulating film is a silicon insulating film is silicon nitride (SiN _x ) or silicon oxide (SiO _X ) _X -ray image sensing device.  The method of claim 1, And an x-ray photosensitive film formed on the pixel electrode. A gate wiring on a substrate, a gate connection wiring extending from the gate wiring, a gate pad electrode extending from the gate connecting wiring, a data connection wiring in one region not parallel to the gate pad electrode, and the data connection Forming a data pad electrode extending from the wiring, a ground connection wiring, and a ground pad electrode extending from the ground connection wiring; Forming a gate insulating film on a front surface of the substrate on which the gate wiring, the gate pad electrode, the data pad electrode, and the ground pad electrode are formed, a first insulating film exposing a portion of the gate connection line and a portion of the data connection line; ; A thin film transistor including an active layer, a source electrode, and a drain electrode formed at an intersection point of the data line crossing the gate line on the gate insulating layer, and a data line in contact with the exposed data connection line; Forming a ground line in contact with the connection line; Forming a first passivation layer on a front surface of the substrate on which the thin film transistor, the ground line, and the data line are formed, exposing a portion of the ground line and a portion of the gate pad electrode; Forming a capacitor electrode in contact with the ground wiring and a first gate pad terminal electrode in contact with the gate pad electrode; Exposing a portion of the drain electrode and the first gate pad electrode terminal on a front surface of the substrate on which the capacitor electrode and the first gate pad terminal electrode are formed, and etching the region corresponding to the ground pad electrode and the data pad electrode. Forming a second protective film that is a third insulating film; Forming a pixel electrode formed on the capacitor electrode while in contact with the drain electrode, and a second gate pad terminal electrode in contact with the first gate pad terminal electrode; Etching the first insulating film and the second insulating film in the region where the third insulating film is etched to form a data pad contact hole exposing the data pad electrode and a ground pad contact hole exposing the ground pad electrode; X-ray image sensing device manufacturing method comprising a. The method of claim 9, And the gate electrode and the gate wiring are formed of a double metal layer. The method of claim 10, The first layer of the double metal layer is aluminum, the second layer is selected from a group of metals consisting of chromium (Cr), tungsten (W), molybdenum (Mo) X-ray image sensing device manufacturing method. The method of claim 9, And the first insulating film, the second insulating film, and the third insulating film are formed of one selected from silicon nitride (SiN _x ) or silicon oxide (SiO _X ). The method of claim 9, Forming a photoconductive film on the pixel electrode; And forming a conductive electrode on the photoconductive film. The method of claim 13, The photoconductive film is a material selected from the group consisting of amorphous selenium (selenium), HgI ₂ , PbO, CdTe, CdSe, thallium bromide, cadmium sulfide. The method of claim 9, The capacitor electrode, the pixel electrode, the first gate pad terminal electrode and the second gate pad terminal electrode are formed of one selected from transparent indium tin oxide (ITO) and indium zinc oxide (IZO). . A gate wiring formed in one direction on the substrate, and a gate pad electrode connected to the gate wiring; A data line defining a pixel area by vertically crossing the gate line with a gate insulating layer interposed therebetween, and a data pad electrode connected to the data line; A thin film transistor configured at a point where the gate wiring and the data wiring cross each other, the thin film transistor including a gate electrode, an active layer, a source electrode and a drain electrode; A ground line formed in one direction in the pixel area, and a ground pad electrode connected to the ground line; A silicon insulating layer formed on the substrate including the thin film transistor, the ground wiring, the data pad electrode, and the ground pad electrode, and exposing a part of the ground wiring, a portion of the gate pad electrode, the data pad electrode, and the ground pad electrode, respectively; Phosphorus first protective film; A capacitor electrode in contact with the exposed ground wiring, a first gate pad terminal electrode in contact with the gate pad electrode, a first data pad terminal electrode in contact with the data pad electrode, and a contact with the ground pad electrode 1 ground pad terminal electrode; A second passivation layer on the first passivation layer, the second passivation layer being a silicon insulating layer formed by exposing the drain electrode, the first gate pad terminal electrode, the first data pad terminal electrode, and the first ground pad terminal electrode; A pixel electrode formed on the capacitor electrode in contact with the drain electrode, a second gate pad terminal electrode in contact with the first gate pad terminal electrode, and a second data pad terminal electrode in contact with the first data pad terminal electrode. And a second ground pad terminal electrode in contact with the first ground pad terminal electrode. X-ray image sensing device comprising a. The method of claim 16, The pixel electrode extends to an upper portion of the source and drain electrodes. The method of claim 16, The silicon insulating layer is silicon nitride (SiN _x ) or silicon oxide (SiO _X ) _X -ray image sensing device.  The method of claim 16, And an x-ray photosensitive film formed on the pixel region. Forming a gate electrode and a gate wiring on the substrate and a gate pad electrode connected to the gate wiring; Forming a gate insulating film on the entire surface of the substrate on which the gate wiring is formed; A data line defining a pixel region crossing the gate line, a thin film transistor including an active layer, a source electrode, and a drain electrode formed at an intersection of the gate line and the data line, and a data pad electrode connected to the data line; Forming a ground line formed in one direction parallel to the data line and a ground pad electrode connected to the ground line; Exposing a portion of the ground line, a portion of the gate pad electrode, a portion of the data pad electrode, and a portion of the ground pad electrode on a front surface of the substrate on which the thin film transistor, the ground wiring, the data pad electrode, and the ground pad electrode are formed. Forming a first passivation film that is a second insulating film; A capacitor electrode in contact with the ground wiring, a first gate pad terminal electrode in contact with the gate pad electrode, a first data pad terminal electrode in contact with the data pad electrode, and a first ground in contact with the ground pad electrode Forming a pad terminal electrode; A portion of the drain electrode is exposed on the entire surface of the substrate on which the capacitor electrode, the first gate pad terminal electrode, the first data pad terminal electrode, and the first ground pad terminal electrode are formed, and the first gate pad terminal electrode and the first data are exposed. Forming a second protective film which is a third insulating film exposing the pad terminal electrode and the first ground pad terminal electrode; A pixel electrode formed on the capacitor electrode in contact with the drain electrode, a second gate pad terminal electrode in contact with the first gate pad terminal electrode, and a second data pad terminal in contact with the first data pad terminal electrode. Forming an electrode and a second ground pad terminal electrode in contact with the first ground pad terminal electrode; X-ray image sensing device manufacturing method comprising a. The method of claim 20, The gate electrode and the gate wiring is a double metal layer X-ray image sensing device manufacturing method. The method of claim 21, The first layer of the double metal layer is aluminum, the second layer is selected from a group of metals consisting of chromium (Cr), tungsten (W), molybdenum (Mo) X-ray image sensing device manufacturing method. The method of claim 20, And the first insulating film, the second insulating film, and the third insulating film are formed of one selected from silicon nitride (SiN _x ) or silicon oxide (SiO _X ). The method of claim 20, Forming a photoconductive film on the pixel electrode; And forming a conductive electrode on the photoconductive film. The method of claim 24, The photoconductive film is an X-ray image sensing device manufacturing method of a material selected from the group consisting of amorphous selenium (selenium), HgI ₂ , PbO, CdTe, CdSe, thallium bromide, cadmium sulfide. The method of claim 20, The capacitor electrode, the pixel electrode, the first and second gate pad terminal electrodes, the first and second data pad terminal electrodes, and the first and second ground pad terminal electrodes are transparent indium-tin-oxide (ITO) and indium-zinc- Method of manufacturing an x-ray image sensing device to form one selected of oxide (IZO).

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