KR20030058336A - A X-ray detector and a method for fabricating thereof - Google Patents

Abstract

PURPOSE: An X-ray detector and a fabricating method thereof are provided to prevent the leakage current from an active channel by forming a silicon insulating layer on an exposed active layer of a TFT. CONSTITUTION: An X-ray detector includes a gate pad electrode(134b), a data pad electrode(136b), a TFT, a ground pad electrode(137b), the first protective layer(156), the second protective layer(164), a capacitor electrode, the third protective layer(172), and a pixel electrode(174). The gate pad electrode is connected to a gate line. The data pad electrode is connected to a data line. The TFT includes a gate electrode, an active layer, a source electrode, and a drain electrode. The ground pad electrode is connected to a ground line. The first protective layer is formed with a silicon insulating layer. The second protective layer is formed with a transparent organic insulating layer. The capacitor electrode is connected to the ground line. The third protective layer includes a contact hole. The pixel electrode is electrically connected to the exposed drain electrode.

Description

X-ray detector and a method for manufacturing the same

The present invention relates to an X-ray image sensing device using a TFT array process and a method of manufacturing the same.

Diagnostic X-ray (X-ray) test method, which is widely used for medical purposes today, is photographed using an X-ray detection film, and a predetermined film print time has to be passed in order to know the result.

However, in recent years, with the development of semiconductor technology, digital X-ray detectors (hereinafter referred to as X-ray image sensing devices) using thin film transistors have been researched and developed. The X-ray image sensing device has an advantage of using a thin film transistor as a switching device, and diagnosing a result by displaying an X-ray image on a screen in real time immediately after the X-ray is photographed.

Hereinafter, the configuration and operation of the X-ray image sensing device will be described.

FIG. 1 is a schematic diagram illustrating the configuration and operation of the X-ray image sensing device 100, wherein a substrate 1 is formed under the thin film transistor 3, the storage capacitor 10, the pixel electrode 12, and the luminous intensity. And the front film 2, the protective film 20, the high voltage electrode 24, the high voltage DC power supply 26, and the like.

The photoconductive film 2 forms an electrical signal, that is, electron and hole pair 6, internally in proportion to the signal intensity of an external electric wave or magnetic wave incident thereto. The photoconductive film 2 serves as a converter for converting an external signal, in particular, an X-ray into an electrical signal. The electron-hole pair 6 formed by the X-ray light is provided under the photoconductive film 2 by the voltage Ev applied from the high voltage DC power supply 26 to the high voltage electrode 24 positioned on the photoconductive film 2. Collected in the form of charge on the pixel electrode 12 is located, and is stored in the storage capacitor 10 formed with the capacitor electrode grounded from the outside. At this time, the charge stored in the storage capacitor 10 is turned on by the gate signal applied to the gate of the thin film transistor 3 and turned on through the data line connected to the source of the thin film transistor 3. It is sent to an image processing circuit to produce an x-ray image.

In order to detect and convert even weak X-ray light into charge in the X-ray image sensing device, the number of trap state densities trapping charge in the photoconductive film 2 is reduced, and the thin film transistor 3 is turned off. The leakage current when there is to be reduced.

2 is a plan view illustrating one pixel area of a conventional X-ray image sensing device.

As shown, the gate wiring 31 is arranged in the row direction, and the data wiring 40 is arranged in the column direction. Further, the thin film transistor T is formed as a switching element at a portion where the gate wiring 31 and the data wiring 40 cross at right angles.

The thin film transistor T may include a gate electrode 30 protruding from the gate wiring 31, an active layer 62 positioned on the gate electrode 30, and a source protruding from the data wiring 40. It consists of an electrode 42 and a drain electrode 44 spaced apart therefrom.

A capacitor electrode 46 is formed in the pixel region, and a pixel electrode 56 in contact with the drain electrode 44 is formed on the capacitor electrode.

The capacitor electrode 46 and the pixel electrode constitute a storage capacitor C, and a dielectric material is inserted between the capacitor and the pixel electrodes 46 and 56.

Here, the pixel electrode 56 serves as a current collecting electrode that collects charges so that holes generated in the photoconductive film can accumulate in the storage capacitor C.

In addition, the pixel electrode 56 may be connected to the drain electrode 44 through the drain contact hole 50 to allow holes stored in the storage capacitor C to flow through the thin film transistor T to the data line. It is electrically connected.

The function of the above-described X-ray image sensing device is summarized as follows.

Holes generated from the photoconductive film (not shown) are collected by the pixel electrode 56 and stored in the storage capacitor C configured together with the capacitor electrode 46.

Also, holes stored in the storage capacitor C move to the source electrode 42 through the drain electrode 44 and the pixel electrode 56 by the operation of the thin film transistor T, and pass through the data line 40. The circuit is processed by an external circuit (not shown) to represent an image.

Here, the electric charges that do not completely escape to the outside through the external circuit, that is, the remaining electric charge remaining in the storage capacitor C, are completely removed by the external circuit before detecting the new X-ray phase.

3A to 3G are sectional views taken along the cutting line II-II 'of FIG. 2 and shown in a process sequence.

First, referring to FIG. 3A, a low-resistance metal such as aluminum (Al) or an aluminum alloy (preferably AlNd) is deposited and patterned as a first metal on the substrate 1 to form the gate electrode 30. do.

As the substrate 1, an expensive quartz plate having a high melting point of an insulating material or a glass substrate mainly used in a low temperature process is used.

3B is a step of depositing a first insulating film and a semiconductor layer, the gate insulating film 60 is formed by depositing an inorganic insulating film such as a silicon nitride film (SiN _x ) or a silicon oxide film (SiO _x ) having a thickness of 4000 Å.

Thereafter, in the step of forming the semiconductor layer 62, the pure amorphous silicon 62 and the impurity amorphous silicon 64 are successively deposited.

Thereafter, the semiconductor layer deposited on the gate insulating layer 60 is patterned to form an active layer 62 and an ohmic contact layer 64, respectively.

FIG. 3C is a view illustrating the steps of forming the source and drain electrodes 42 and 44 of the second metal layer.

When the source and drain electrodes 42 and 44 are formed, a capacitor electrode 46 for forming a storage capacitor is formed.

As the second metal layer, a metal such as chromium (Cr) or chromium alloy (Cr alloy) is used.

In addition, the ohmic contact layer 64 exposed between the source electrode 42 and the drain electrode 44, that is, a portion to become an active channel of the thin film transistor using the source and drain electrodes 42 and 44 as a mask. Only the channel is removed by exposing a portion of the active layer 62 to form a channel (CH).

3D is a diagram showing the step of forming the protective film 66.

An insulating film is coated on the entire surface of the substrate 1 on which the second metal layers 42, 44, and 46 are formed to form a protective film 66.

Subsequently, the passivation layer 66 is patterned to form a drain contact hole 50 so that a part of the drain electrode 44 is exposed.

The passivation layer is formed of one selected from the group of organic insulating materials including benzocyclobutene (BCB), acryl resin, and the like. By using such an organic insulating film, the entire substrate can be flattened to uniformly apply a photosensitive material to the entire pixel region.

3E illustrates a step of forming a pixel electrode, in which a transparent conductive metal is deposited on the entire surface of the substrate 1 on which the passivation layer 66 is formed, and then patterned to contact the exposed drain electrode 44. ).

The pixel electrode 56 together with the capacitor electrode 46 constitutes a storage capacitor C.

Next, as shown in FIG. 3F, the photosensitive material 2 and the upper passivation layer 20 are coated, and the photosensitive material is used as a transducer which receives an external signal and converts the signal into an electrical signal. The compound of amorphous selenium is used. Is deposited to a thickness of 100-500 μm using an evaporator. When the photosensitive material is exposed to X-ray light, electrons and hole pairs are generated in the photosensitive material according to the intensity of the X-ray light.

Finally, as shown in FIG. 3G, a transparent conductive electrode is formed as the high voltage electrode 24 so that the X-ray light can be transmitted. When the X-ray light is applied while applying a voltage to the conductive electrode, electrons and hole pairs formed in the photosensitive material are separated from each other, and holes separated by the conductive electrode are collected in the pixel electrode 56 and stored in the storage capacitor C.

The X-ray image sensing device may be formed by the process as described above.

However, the active channel of the thin film transistor according to the conventional X-ray image sensing device forming method as described above is formed in a structure in direct contact with the organic film (BCB film). However, since the active channel and the organic film (BCB film) do not have good contact characteristics with each other, a trap level capable of trapping electrons is partially present at the interface.

Therefore, as shown in FIG. 4, abnormal leakage current characteristics are exhibited.

FIG. 4 is a graph showing the relationship between the gate voltage (V _g ) and the drain current (I _d ) of a thin film transistor formed in an X-ray image sensing device manufactured according to a conventional method, which is a leakage current of the device. You can see the characteristics.

That is, when the gate voltage is 0V, the thin film transistor is not in an operating state, so the current value flowing through the thin film transistor should be almost a value H. If the trap state of electrons exists in the thin film transistor, Even when the gate voltage is 0V, the thin film transistor is allowed to flow a current (K), that is, a leakage current, which affects the operating characteristics of the liquid crystal panel.

The present invention has been made to solve the above-described problems, the first configuration of the present invention is to form an inorganic insulating film between the thin film transistor and the organic insulating film.

The second configuration of the present invention is a modification of the first configuration, which prevents leakage current and improves the structure of the pad portion.

A first object of the present invention according to the first configuration and the second configuration is to prevent leakage current generated in the thin film transistor, and a second object is to simplify the process by improving the structure of the pad portion.

1 is a cross-sectional view showing the operation of the X-ray image sensing device,

2 is a plan view showing one pixel area of a conventional X-ray image sensing device,

3A to 3G are cross-sectional views illustrating a process according to a conventional process by cutting II-II ′ of FIG. 2;

4 is a graph illustrating leakage current characteristics of a thin film transistor configured in a conventional X-ray image sensing device.

5 is a plan view illustrating one pixel area of an image sensing device according to a first embodiment of the present invention;

6A through 6K are cross-sectional views illustrating the process sequence of the present invention by cutting III-III ′, IV-IV ′, and V-V ′ of FIG. 5.

7 is a graph illustrating leakage current characteristics of a thin film transistor configured in an X-ray image sensing device manufactured according to the present invention.

8 is a plan view illustrating one pixel area of an image sensing device according to a second embodiment of the present invention;

9A to 9J are cross-sectional views illustrating cutting processes of cutting lines Ⅶ-Ⅶ`, Ⅷ-Ⅷ`, Ⅸ-Ⅸ`, Ⅹ-Ⅹ` of FIG.

<Explanation of symbols for main parts of drawing>

100 substrate 102 gate buffer

104: data buffer 134b: gate pad electrode

136b: data pad electrode 137b: ground pad electrode

138: gate insulating film 156: first protective film

164: second passivation layer 166: drain auxiliary electrode

168 capacitor electrode 172 third protective film

174: pixel electrode

According to an aspect of the present invention, there is provided an X-ray image sensing device comprising: a gate wiring formed in one direction on a substrate, and a gate pad electrode connected to the gate wiring; A data line defining a pixel region by crossing the gate line vertically with a gate insulating layer interposed therebetween, and a data pad electrode connected to the data line; A thin film transistor positioned at the intersection of the two wires, the thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; A ground line formed in parallel with the data line and a ground pad electrode connected to the ground line; A first passivation layer formed on the substrate on which the thin film transistor and the ground line are formed and patterned to expose a portion of the drain electrode and a portion of the ground line; A second passivation film formed on the first passivation film and formed of the same pattern as the first passivation film, the second passivation film being a transparent organic insulating film exposing a part of the ground wiring and part of the drain electrode; A capacitor electrode in contact with the ground wiring; A third passivation layer on the capacitor electrode and including a contact hole exposing the drain electrode; The capacitor electrode is formed to overlap the planar surface with the third passivation layer interposed therebetween, and includes a pixel electrode electrically connected to the exposed drain electrode.

The gate electrode and the gate wiring are formed of one selected from a metal group consisting of aluminum having a first layer and chromium (Cr), tungsten (W), and molybdenum (Mo).

The gate pad electrode, the data pad electrode, and the ground pad electrode are made of the same material on the same layer.

The gate line contacts the gate pad electrode through a gate connection line, the data line contacts the data pad electrode through a data connection line, and the ground line connects with the ground pad electrode through a ground connection line.

The data line and the ground line may be in contact with the data connection line and the ground connection line through a contact hole formed in the gate insulating layer.

An auxiliary electrode is further configured between the drain electrode and the pixel electrode.

The pixel electrode extends to the top of the source and drain electrodes.

The low temperature deposition takes place in the range of 220 ° C to 240 ° C.

According to an aspect of the present invention, there is provided a method of manufacturing an X-ray image surveillance device comprising: forming a plurality of first buffer layers, second buffer layers, and third buffer layers on a substrate; A gate wiring and a gate electrode on the substrate on which the plurality of buffer layers are formed, a gate connection wiring extending from the gate wiring, a gate pad electrode extending above the first buffer layer on the gate connection wiring, and not parallel to the gate pad electrode. A data connection wiring formed in an area, a data pad electrode extending over the second buffer layer in the data connection wiring, a ground connection wiring spaced in parallel with the data connection wiring, and an extension of the third buffer layer in the ground connection wiring Forming a ground pad electrode; Forming an active layer and an ohmic contact layer stacked on the gate insulating layer on the gate electrode; Forming and patterning a gate insulating film, which is the first insulating film, to form a data wiring contact hole and a ground wiring contact hole exposing a portion of the data connection wiring and the ground connection wiring; A source electrode and a drain electrode in contact with the ohmic contact layer, a data line connected to the source electrode and having one end thereof in contact with the data connection wire, and one end in a pixel area, and one end of which is connected to the ground connection wire. Forming a contact ground wire; Depositing and patterning a silicon insulating film on the entire surface of the substrate on which the data wiring and the ground wiring are formed, thereby forming a first passivation layer exposing a part of the ground wiring and a part of the drain electrode; Forming a second passivation layer formed on the first passivation layer, the second passivation layer formed in the same pattern as the first passivation layer and exposing a part of the ground wiring and part of the drain electrode; Forming a transparent capacitor electrode in contact with the exposed ground wiring; Forming a third passivation layer formed on the substrate on which the capacitor electrode is formed, forming a contact hole exposing the drain electrode, and removing regions corresponding to the gate pad electrode, the data pad electrode, and the ground pad electrode; ; Forming a transparent pixel electrode overlapping the first electrode and the third passivation layer in a planar manner, the transparent pixel electrode being electrically connected to the exposed drain electrode; Etching the second passivation layer, the first passivation layer, and the gate insulating layer to form a gate pad contact hole, a data pad contact hole, and a ground pad contact hole exposing the gate pad electrode, the data pad electrode, and the ground pad electrode. .

According to another aspect of the present invention, an X-ray image sensing device includes: a gate wiring configured in one direction on a substrate and connected to a gate pad electrode having a predetermined area at one end thereof; A data line connected to the gate line vertically with a gate insulating layer interposed therebetween to define a pixel area, and one end of which is connected to a data pad electrode; A thin film transistor formed in the switching region on the substrate and including a gate electrode connected to the gate wiring, an active layer, a source electrode connected to the data wiring, and a drain electrode spaced apart from the drain electrode; A ground line formed in the pixel area in parallel with the data line and having one end connected to a ground pad electrode; A first passivation layer formed of a silicon insulating film patterned to expose a part of the ground wiring, a part of the drain electrode, a part of the data pad electrode, a part of the ground pad electrode, and a part of the gate pad electrode; A data pad auxiliary electrode, a ground pad auxiliary electrode, and a gate pad auxiliary electrode in contact with the exposed data pad electrode, the ground pad electrode, and the gate pad electrode; A second passivation layer formed on the first passivation layer, the second passivation layer being a transparent organic insulating layer exposing part of the drain electrode and the ground wiring again;

A capacitor electrode in contact with the ground wiring; A third passivation layer on the capacitor electrode and exposing the drain electrode; A pixel electrode formed to overlap the capacitor electrode in a planar manner with the third passivation layer interposed therebetween and electrically connected to the exposed drain electrode; And a gate pad contact hole, a data pad contact hole, and a ground pad contact hole exposing the gate pad auxiliary electrode, the data pad auxiliary electrode, and the ground pad auxiliary electrode.

The gate electrode and the gate wiring are one selected from a metal group consisting of aluminum, and a second layer is chromium (Cr), tungsten (W), and molybdenum (Mo).

The data pad electrode and the ground pad electrode are made of the same material on the same layer.

The gate pad auxiliary electrode, the data pad auxiliary electrode, and the ground pad auxiliary electrode are formed of one selected from a group of low resistance metals including aluminum (Al) and an aluminum alloy.

The pixel electrode extends to the top of the source and drain electrodes.

A first mask process step of forming a gate wiring including a gate pad and a gate electrode on a second substrate of the present invention; Depositing an insulating material on the substrate on which the gate electrode is formed to form a gate insulating film as a first insulating film; A second mask process step of forming an active layer and an ohmic contact layer on the gate electrode of the first insulating layer; A source wire in contact with the ohmic contact layer, a drain electrode spaced apart from the predetermined distance, a data wire connected to the source electrode and including a data pad electrode at one end thereof, and parallel to the data wire in one direction. A third mask process step of forming a ground wiring including a ground pad electrode at an end thereof; A fourth mask process of depositing an inorganic insulating material on the entire surface of the substrate on which the source and drain electrodes are formed to form a first passivation layer, and then patterning and exposing a part of the drain electrode, the ground wiring, the data pad, the ground pad, and the gate pad Steps; Depositing and patterning a conductive metal on the first passivation layer to form a data pad auxiliary electrode, a ground pad auxiliary electrode, and a gate pad auxiliary electrode in contact with the exposed data pad electrode, the ground pad electrode, and the gate pad electrode, respectively; 5 mask process steps; A sixth mask process step of applying an organic insulating material to the entire surface of the substrate on which the pad auxiliary electrode is formed to form a second passivation layer, which is a planarization film, and then patterning the semiconductor substrate to expose a portion of the drain electrode and the ground wiring; A seventh mask process step of forming a transparent drain auxiliary electrode in contact with the exposed drain electrode and a transparent capacitor electrode in contact with the exposed ground wiring; An eighth mask process step of exposing a portion of the drain auxiliary electrode by patterning a silicon insulating film on the entire surface of the substrate on which the drain auxiliary electrode and the capacitor electrode are formed to form a third passivation layer; A ninth mask process step of forming a transparent pixel electrode connected to the exposed auxiliary drain electrode and formed to overlap the capacitor electrode in a plane; And etching the third and fourth insulating layers to expose portions of the data pad auxiliary electrode, the ground pad auxiliary electrode, and the gate pad auxiliary electrode.

Hereinafter, the configuration and operation according to the embodiment of the present invention will be described with reference to the accompanying drawings.

First Embodiment

FIG. 5 is a plan view illustrating a pixel area of an X-ray image sensing device according to a first exemplary embodiment of the present invention.

As shown in the drawing, the gate wiring 151 is formed in the row direction and the data wiring 152 is formed in the column direction to intersect the gate wiring 151.

An area defined by the intersection of the two wires 151 and 152 is called a pixel area, and a ground wire 154 spaced in parallel with the data wire 152 is formed in the pixel area.

The gate line 151 is connected to the gate pad electrode 134b through the gate connection line 134a, and the data line 152 is connected to the data pad electrode 136b through the data connection line 136a. The ground line 154 is connected to the ground pad electrode 137b through a ground connection line 137a.

The connection wirings 134a, 136a, and 137a are disposed between the driving region where the pad electrodes 134b, 136b, and 137b are located and the pixel region where the wirings 151, 152, and 154 are located, respectively. Connect.

A capacitor electrode 168 and a pixel electrode 174 are formed in the pixel region, and the capacitor electrode 168 is in contact with the ground wiring 154 through the ground wiring contact holes 160a and 160b and the pixel electrode ( 174 is configured to contact the drain electrode 150.

The capacitor electrode 168 and the pixel electrode 174 are formed with a thinly deposited inorganic insulating layer (not shown) to form a storage capacitor C.

In the above-described configuration, the gate pad electrode 134b, the data pad electrode 136b, and the ground pad electrode 137b have a structure exposed through each contact hole 176, 178, and 180.

Although not shown, the pixel electrode 174 serves as a current collecting electrode that collects charges so that holes generated in the photoconductive film (2 of FIG. 1) can accumulate in the storage capacitor C.

6A through 6K are cut along the cutting line III-III ', the cutting line IV-IV', the cutting line V-V ′ and the cutting line VI-VI ′ of FIG. 5, and are shown according to a process sequence according to the present invention. 6A illustrates a process of forming the gate buffer 102, the data buffer 104, and the ground pad buffer 105 on an area including the gate pad electrode, the data pad electrode, and the ground pad electrode.

The buffer layers 102, 104, and 105 are means for increasing the height of the gate pad electrode, the data pad electrode, and the ground pad electrode to be formed later.

The reason for increasing the height of each pad electrode is to expose the pad electrodes by etching the insulating layer on each of the pad electrodes without forming an auxiliary electrode on each pad electrode separately in the last step. The height of each pad electrode is increased by using the buffer layer so as to easily contact each pad electrode.

Since the buffer layers 102, 104, and 105 do not have an electrical function, the buffer layers 102, 104, and 105 may be formed by depositing an insulating material, or may be formed by depositing a metal material.

FIG. 6B illustrates the steps of depositing and patterning a conductive metal in duplicate to form a first metal layer of dual structure.

Among the double metal layers, the first metal 132a uses low-resistance aluminum (Al), an aluminum alloy (mainly AlNd), and the like, and the second metal 132b includes molybdenum (Mo), chromium (Cr), and tungsten. Use the selected one of (W).

A metal layer having a double structure is patterned to form a gate line 151a of FIG. 5, a gate connection line 134a extending from the gate line, and a gate pad electrode 134b extending from the gate connection line 134a.

At the same time, a data pad electrode 136b extending from the data connection wiring 136a and the data connection wiring, and a ground pad electrode 137b extending from the ground connection wiring 137a and the ground connection wiring are formed.

The reason why the gate electrode 132 is used as a double metal layer is that aluminum has a low resistance in order to reduce the RC delay, but pure aluminum has low chemical resistance. In the subsequent high temperature process, a wiring defect problem due to hillock formation is caused, so that the laminated structure is applied as described above.

In the above-described configuration, however, the upper metal layer is etched to expose the lower aluminum layer of the data pad electrode, the gate pad electrode, and the ground pad electrode.

Because the pad electrodes 134b, 136b, and 137b on the buffer layers 102, 104, and 105 are bonded to an external wiring and receive a signal, they require low resistance. Therefore, the lower aluminum metal layer having lower resistance than the upper metal layer having high resistance is used as the contact electrode.

In this case, the pad electrodes 134b, 136b, and 137b are formed on the buffer layers 102, 104, and 105, respectively.

Next, as shown in FIG. 6C, a silicon nitride film is formed on the entire surface of the substrate 100 on which the gate electrode 132, the gate pad electrode 134b, the data pad electrode 136b, and the ground pad electrode 137b are formed. One selected from the group of inorganic insulating materials including (SiN _X ) and silicon oxide (SiO ₂ ), and in some cases, an organic insulating material group consisting of benzocyclobutene (BCB) and acrylic resin (resin) Is deposited or coated to form a gate insulating film 138 having a thickness of 100 mV to 3000 mV.

FIG. 6D illustrates a step of forming the active layer 140 and the ohmic contact layer 142.

First, pure amorphous silicon (A-Si: H) and impurity amorphous silicon (n + a-Si: H) are sequentially formed on the gate insulating film 138 while the insulating film is not exposed to the outside air. After stacking and patterning, the active layer 140 and the ohmic contact layer 142 are formed.

Next, a portion of the gate insulating layer 138 on the upper portion of the data connection line 136a and the upper portion of the ground connection line 137a is etched to form a data line contact hole 146 and a ground line contact hole 147.

FIG. 6E shows a second metal layer formed over the gate insulating layer 138 on which the data wire contact hole 146, the ground wire contact hole 147, the active layer 140, and the ohmic contact layer 142 are formed and patterned. The source electrode 148 and the drain electrode 150 formed on both sides of the active layer 140 and the data wiring 152 connected to the source electrode 148 are formed.

At the same time, a ground wiring 154 is formed across the center of the pixel region.

In this structure, one end of the data line 152 contacts the data connection line 136a through the data line contact hole 146, and one end of the ground line 154 contacts the ground line contact hole. In contact with the ground connection wiring 137a through 147.

Next, the ohmic contact layer 142 exposed between the source and drain electrodes is etched using the patterned source and drain electrodes 148 and 150 as a mask to expose a portion of the active layer 140.

Alternatively, the ohmic contact layer 142 may be etched away while the source and drain electrodes 148 and 150 are patterned using a photoresist (not shown) photomask and the photoresist is not removed.

The exposed surface of the active layer 140 functions as a channel through which electrons flow.

FIG. 6F illustrates a step of forming a first passivation layer 156 on the entire surface of the substrate 100 on which the source and drain electrodes 148 and 150, the ground wiring 154, the data wiring 152, and the like are formed.

The first passivation layer 156 is formed by depositing a silicon insulating layer (silicon nitride (SiN _x ) or silicon oxide (SiO ₂ )) by a predetermined method to a thickness of 500 kV to 1300 kV.

As such, when the first passivation layer, which is a layer in direct contact with the exposed active layer 140, is formed of a silicon insulating layer, the electrons are attracted because the interface property between the exposed active layer 140 and the first passivation layer 156 is excellent. The area to be trapped becomes smaller, and therefore, the result is that the mobility of electrons becomes faster.

Therefore, it is possible to prevent an increase in leakage current due to direct contact between the second passivation layer 156 made of the organic insulating layer formed in a subsequent process and the channel.

Here, the first passivation layer 156 is patterned so that a part of the drain electrode 150 and a part of the ground wiring 154 are exposed to expose the first drain contact hole 158a and the first ground wiring contact hole, respectively. 160a).

6G is a step of forming a second passivation layer 164, which is a transparent organic layer, on the patterned first passivation layer 156.

That is, the second passivation layer may be coated on the first passivation layer 156 by applying one selected from the group of transparent organic insulating materials including benzocyclobutene (BCB), acryl resin, etc. to 1 μm to 1.5 μm. 164 is formed.

Before the organic insulating layer is coated, the thin film transistor region is higher than the pixel pixel region P as shown in FIG. 6F. However, by applying the organic insulating film, the surface of the organic insulating film on these two regions can be flattened to the same height.

Subsequently, the second protective layer 164 of the portion corresponding to the first drain contact hole 158a and the first ground interconnection contact hole 160a is etched to form the drain electrode 150 and the ground wiring 154. The second drain contact hole 158b and the second ground interconnection contact hole 160b are formed so as to be exposed again.

In this case, each of the first and second drain contact holes 158a and 158b and the first and second ground contact holes 160a and 160b are exposed with the same mask, respectively, and then the first passivation layer 156 using dry etching. ) And the second passivation layer 164 may be simultaneously formed by etching.

Next, FIG. 6H is a step of forming a drain auxiliary electrode 166 and a capacitor electrode 168 as an etch stop layer on the drain contact holes 158a and b as transparent electrodes.

That is, the drain auxiliary electrode 166 contacting the exposed drain electrode 150 by depositing and patterning a transparent conductive material such as indium tin oxide (ITO) on the patterned second passivation layer 164, and the A capacitor electrode 168 is formed in contact with the exposed ground line 154.

The ground line 154 is formed to pass a portion of the pixel (FIG. 5), but the capacitor electrode 168 is wider than the ground line 154 so as not to overlap with the data line 152, and then the process It overlaps with at least half of the area of the pixel electrode formed at.

Next, as shown in FIG. 6I, one of the above-described organic insulating material groups is deposited on the entire surface of the substrate 100 including the drain auxiliary electrode 166 and the capacitor electrode 168 to form a third passivation layer 172. ).

The third passivation layer 172 is patterned to form a third drain contact hole 158c exposing the drain auxiliary electrode 166.

As described above, the third drain contact hole 158c is formed to have a smaller area than the drain auxiliary electrode already formed. Since the drain auxiliary electrode 166 is formed on the drain electrode, damage to the drain electrode 150 may be prevented when the third drain contact hole 158c is formed.

At the same time, the third passivation layer 172 on the gate pad electrode 134b, the data pad electrode 136b, and the ground wiring pad electrode 137b is removed.

Next, FIG. 6J illustrates a method of depositing and patterning a transparent conductive metal on the entire surface of the third passivation layer 172 on which the third drain contact hole 158c is formed to contact the exposed drain auxiliary electrode 166. The pixel electrode 174 is formed on the drain electrodes 148 and 150 and on the pixel region P.

The pixel electrode 174 is formed to overlap with the capacitor first electrode 168 with the third passivation layer 172 therebetween.

The passivation layer interposed between the pixel electrode 174 and the storage first electrode 168 electrode is thicker than the third passivation layer 172 of the present invention used for surface planarization or the conventional planarization layer (66 in FIG. 3D). Since it is small, the capacity of the storage capacitor C can be increased.

Accordingly, a storage capacitor C may be formed in the pixel region P, and the pixel electrode 174 also functions as a capacitor second electrode.

6K illustrates a gate pad electrode 134b, a data pad electrode 136b, and a ground wiring pad electrode 137b disposed over the gate buffer 102, over the data buffer layer 104, and over the ground wiring buffer layer 105. Step.

As illustrated, the gate insulating layer 138, the first passivation layer 156, and the second passivation layer 164 are disposed on the gate pad electrode 134b, the data pad electrode 136b, and the ground wiring pad electrode 137b. The gate pad contact hole 176, the data pad contact hole 178, and the ground wiring contact hole 180 exposing the lower gate pad electrode 134b, the data pad electrode 136b, and the ground pad electrode 137b are etched. ). The third passivation layer 172 formed on the etched insulating layer is already removed in the previous step.

Although the following process is not shown, the photosensitive material is applied, and the photosensitive material is used as a transducer which receives an external signal and converts the signal into an electrical signal. The compound of amorphous selenium is converted to 100 by using an evaporator. Deposit at -500 μm thickness. In addition, an X-ray photosensitive material having a low dark conductivity and sensitive to an external signal, particularly X-ray photoconductivity, may be used, such as HgI ₂ , PbO, CdTe, CdSe, thallium bromide, cadmium sulfide, and the like. When the photosensitive material is exposed to X-ray light, electrons and hole pairs are generated in the photosensitive material according to the light intensity.

After application of the X-ray photosensitive material, the metal layer is formed thin enough to transmit transparent conductive electrodes or X-ray light as high voltage electrodes.

When the X-ray light is applied while applying a voltage to the conductive electrode, electrons and hole pairs formed in the photosensitive material are separated from each other, and holes separated by the conductive electrode are collected in the pixel electrode 174 and stored in the storage capacitor C.

The thin film transistor array substrate for the x-ray image sensing device according to the present invention may be manufactured by the process as described above.

According to an exemplary embodiment of the present invention, a silicon insulating material is deposited on the thin film transistor T to improve contact characteristics between the exposed active layer 140 and the insulating layer 156 of the thin film transistor T. The carrier mobility is improved.

Therefore, since the thickness of the insulating layer formed between the capacitor electrode and the pixel electrode can be reduced, the storage capacitance of the storage capacitor can be increased.

In addition, it is possible to provide a clear image to the display device connected to the outside.

As described above, the leakage current characteristics of the thin film transistor configured in the X-ray image sensing device manufactured according to the present invention will be described below with reference to FIG. 7.

7 is a graph illustrating leakage current characteristics of a thin film transistor configured in an X-ray image sensing device according to the present invention.

As shown, the thin film transistor according to the present invention shows that when the gate voltage (v _g ) is 0V, the drain current (I _d ) value (I) close to 0V shows the ideal operating characteristics flowing.

Hereinafter, the second embodiment of the present invention further improves the structure of the first embodiment to simplify the process, and at the same time, a more improved pad part structure for improving the contact of the wire in the pad part used by the wire bonding method. Suggest.

Second Embodiment

In the second embodiment of the present invention, the structure of the pad portion is further improved and the process is simplified.

8 is a plan view illustrating one pixel area of the X-ray image sensing device according to the second embodiment of the present invention.

As shown in the drawing, the gate wiring 251 is formed in the row direction and the data wiring 252 is formed in the column direction so as to intersect the gate wiring 251.

An area defined by the intersection of the two wires 251 and 252 is called a pixel area, and a ground wire 254 spaced apart from and parallel to the data line 252 is formed in the pixel area.

The gate line 251 is connected to the gate pad electrode 234b through the gate connection line 234a, and the data line 252 is connected to the data pad electrode 253b through the data connection line 253a. The ground line 254 is connected to the ground pad electrode 255b through a ground connection line 255a.

The connection wirings 234a, 253a, and 255a are disposed between the driving region where the pad electrodes 234b, 253b and 255b are located and the pixel region where the wirings 251, 252, and 254 are positioned to connect each wiring and the pad electrode. Connect.

A capacitor electrode 268 and a pixel electrode 274 are formed in the pixel region, and the capacitor electrode 268 is in contact with the ground wiring 254 through the ground wiring contact holes 260a and 260b and the pixel electrode ( 274 is configured to be in contact with the drain electrode 250.

The capacitor electrode 268 and the pixel electrode 274 are formed with a thinly deposited inorganic insulating layer (not shown) to form a storage capacitor (C).

In the above-described configuration, the gate pad auxiliary electrode 257, the data pad auxiliary electrode 259, and the ground pad auxiliary electrode which are in contact with the data pad electrode 253b, the ground pad electrode 255b, and the gate pad electrode 234b, respectively. It configures 261.

In the above configuration, the gate pad auxiliary electrode 257, the data pad auxiliary electrode 259, and the ground pad auxiliary electrode 261 are exposed through the respective contact holes 278, 280, and 282.

Although not illustrated, the pixel electrode 274 serves as a current collecting electrode that collects charges so that holes generated in the photoconductive film (2 of FIG. 1) can accumulate in the storage capacitor C.

In the above-described configuration, the first feature of the second embodiment of the present invention comprises the data line 252 and the data pad electrode 253b and the ground line 254 and the ground pad electrode 255b on the same layer, It is to form a separate auxiliary electrode (257, 259, 261) in contact with each pad electrode.

In this way, there is no fear that the metal of the pad portion is overetched, and the process can be simplified.

In addition, another feature of the second embodiment of the present invention is to form a silicon insulating film formed on top of the thin film transistor and the capacitor electrode by a low temperature deposition method of about 230 ° C.

When the silicon insulating film is deposited at low temperature, the deposition characteristic is further improved, and thus the operation characteristic of the thin film transistor is further improved, and the film of the protection layer is not generated on the capacitor electrode 268.

Hereinafter, a manufacturing process of the X-ray image sensing device according to the second embodiment of the present invention will be described with reference to FIGS. 9A to 9J.

9A to 9J are cross-sectional views showing the process sequence of the present invention by cutting along the cutting lines Ⅶ-Ⅶ ′, Ⅷ-Ⅷ ′, Ⅸ-Ⅸ ′, and Ⅹ-Ⅹ ′ of FIG. 8.

First, FIG. 9A illustrates a step of forming a double structured gate electrode 232 and a gate wiring 251 by depositing and patterning a conductive metal in a first mask process.

The first metal of the double metal layer is a low-resistance aluminum (Al), aluminum alloy (mainly AlNd) and the like, the second metal is selected from molybdenum (Mo), chromium (Cr), tungsten (W). use.

The double metal layer is patterned to form a gate electrode 232, a gate line 251, a gate connection line 234a extending from the gate line 251, and a gate pad electrode 234b extending from the gate connection line. do.

Next, as shown in FIG. 9B, silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) are formed on the entire surface of the substrate 200 on which the gate pad electrode 234b and the gate wiring 251 are formed. The gate insulating film 238 may be deposited or coated by depositing or applying one selected from the group of inorganic insulating materials and, optionally, a group of organic insulating materials including benzocyclobutene (BCB), acrylic resin, and the like. It is formed to the thickness of.

9C is a diagram illustrating a step of forming an active layer 240 and an ohmic contact layer 242 by a second mask process.

First, pure amorphous silicon (a-Si: H) and impurity amorphous silicon (n + a-Si: H) are sequentially formed on the gate insulating film 238 in a state where the insulating film is not exposed to the outside air. After stacking and patterning, the active layer 240 and the ohmic contact layer 242 are formed.

Next, FIG. 9D illustrates a third mask process, in which aluminum (Al), chromium (Cr), and molybdenum are formed on the gate insulating layer 238 on which the active layer 240 and the ohmic contact layer 242 are formed. One selected from the group of conductive metals including (Mo), tungsten (W), and the like is deposited to form a second metal layer.

Successively, patterning the second metal layer, the source electrode 248 and the drain electrode 250 contacting the ohmic contact layer 242, the data wiring 252 connected to the source electrode 248, and the The data connection wiring 253a extending from the data wiring 252 and the data pad electrode 253b extending from the data connection wiring are formed.

At the same time, a ground line 254 spaced apart from the data line 252, a ground connection line 255a extending from the ground line, and a ground pad electrode 255b extending from the ground line are formed.

Next, the ohmic contact layer 242 exposed between the source and drain electrodes 248 and 250 is etched using the patterned source and drain electrodes 248 and 250 as a mask to expose a portion of the active layer 240.

Alternatively, the ohmic contact layer 242 may be etched away while the source and drain electrodes 248 and 250 are patterned using a photoresist (not shown) photo mask and the photoresist is not removed.

The exposed surface of the active layer 240 functions as a channel through which electrons flow.

9E illustrates a method of forming a first passivation layer 256 on the entire surface of the substrate 200 on which the source and drain electrodes 248 and 250, the ground line 254, the data line 252, and the like are formed in a fourth mask process. Figure is shown.

The first passivation layer 256 is formed by depositing a silicon insulating film (silicon nitride (SiN _x ) or silicon oxide (SiO ₂ )) by a predetermined method to a thickness of 500 kPa to 1300 kPa.

As such, when the first passivation layer, which is a layer directly in contact with the exposed active layer 240, is formed of a silicon insulating layer, the electrons are formed because the interface property between the exposed active layer 240 and the first passivation layer 256 is excellent. Since the trapping area is reduced, the mobility of electrons can be increased.

Therefore, it is possible to prevent an increase in leakage current due to direct contact between the second passivation layer, which is an organic insulating layer formed in a subsequent process, and the channel.

The first passivation layer 256 is patterned to expose a portion of the drain electrode 250, the ground wiring 254, the gate pad electrode 234b, the data pad electrode 253b, and the ground pad electrode 255b. The first drain contact hole 258a, the first ground wiring contact hole 260a, the first gate pad contact hole 261a, the first data pad contact hole 263a, and the first ground pad contact hole 265a may be formed. Form.

9F illustrates a fifth mask process to form auxiliary electrodes in contact with the exposed pad electrodes.

In other words, a low-resistance metal material such as aluminum (Al) or aluminum alloy (AlNd) is deposited and patterned on the first passivation layer 256 having the contact hole to contact the exposed gate pad electrode 234b. The auxiliary gate pad electrode 257 and the auxiliary data pad electrode 259 in contact with the data pad terminal electrode 253b and the auxiliary ground pad electrode 261 in contact with the ground pad terminal electrode 255b are formed.

In this case, the low resistance metal layer may be left in contact with the exposed drain electrode 250 and the ground wiring 254 or may be completely removed.

In this drawing, the drain electrode 250 exposed between the first passivation layer and the aluminum layer deposited on the upper portion of the ground line 254 are completely removed.

Next, FIG. 9G illustrates benzocyclobutene (BCB) on the entire surface of the substrate 200 on which the auxiliary gate pad electrode 257, the auxiliary data pad electrode 259, and the auxiliary ground pad electrode 261 are formed in a sixth mask process. And a selected one of a group of organic insulating materials including an acrylic resin and the like, to form a second passivation layer 264 that is a planarization layer.

A second drain contact hole 258b for patterning the second passivation layer 264 to expose the drain electrode 250 in a portion corresponding to the first drain contact hole 258a and a first ground; A second ground wiring contact hole 260b exposing a part of the ground wiring 254 is formed in a portion corresponding to the wiring contact hole 260a.

In this case, each of the first and second drain contact holes 258a and 258b and the first and second ground contact holes 260a and 260b are exposed with the same mask, respectively, and then the first passivation layer 256 is formed using dry etching. ) And the second passivation layer 264 may be simultaneously etched.

However, the etching process is performed separately.

Next, FIG. 9H illustrates a step of forming a drain auxiliary electrode 266 as an etch stop layer and forming a capacitor electrode 268 in the pixel region in a seventh mask process.

That is, a drain auxiliary electrode 266 contacting the exposed drain electrode 250 by depositing and patterning a transparent conductive material such as indium tin oxide (ITO) on the patterned second passivation layer 264, and the The capacitor electrode 268 is formed in contact with the exposed ground line 254.

The ground line 254 is formed to pass through a part of the pixel electrode (FIG. 8), but the capacitor electrode 268 is wider than the ground line 254 without overlapping with the data line 252, so that the pixel electrode is wider than the pixel electrode. It overlaps with more than half of the total area.

In FIG. 9I, a third passivation layer 272 is formed by depositing the above-described silicon insulating material on the entire surface of the substrate 200 on which the drain auxiliary electrode 266 and the capacitor electrode 268 are formed.

The third passivation layer 272 is patterned to form a third drain contact hole 258c exposing the drain auxiliary electrode 266.

The third drain contact hole 258c is formed to have a smaller area than the drain auxiliary electrode 266 that is already formed. Since the drain auxiliary electrode 266 is formed on the drain electrode, damage to the drain electrode 250 may be prevented when the third drain contact hole 258c is formed.

Next, FIG. 9J is a diagram illustrating a cross section of a substrate formed through a ninth mask process and a tenth mask process.

As illustrated, the transparent conductive metal as described above is deposited and patterned on the entire surface of the third passivation layer 272 on which the third drain contact hole 258c is formed, and exposed through the third drain contact hole 258c. The pixel electrode 274 in contact with the drain auxiliary electrode 266 is formed.

The pixel electrode 274 is planarly overlapped with the capacitor electrode 268 with the third passivation layer 272 interposed therebetween.

The third passivation layer 272 inserted between the pixel electrode 274 and the capacitor electrode 268 is smaller in thickness than the conventional planarization layer 66 (see FIG. 3D), thereby increasing the capacity of the storage capacitor C. FIG. .

Accordingly, a storage capacitor C may be formed in the pixel region P, and the pixel electrode 274 also functions as a capacitor second electrode 274.

Next, a portion of the second passivation layer 264 and the third passivation layer 272 are etched in a 10 mask process, so that the auxiliary gate pad electrode 257, the auxiliary data pad electrode 259, and the auxiliary ground pad electrode ( A gate pad contact hole 278, a data pad contact hole 280, and a ground pad contact hole 282 exposing a portion of the 261 are formed.

In the processes of the first and second embodiments described above, the first protective film formed on the thin film transistor and the third protective film formed on the capacitor electrode are formed of silicon nitride (SiN _X) in a low-temperature atmosphere at 230 ° C. ) And one selected from the group of inorganic insulating materials including silicon oxide (SiO ₂ ).

In this case, since the adhesion property of the insulating layer is further improved, the thin film transistor T may further improve operating characteristics, and in the storage unit, the third passivation layer deposited on the capacitor electrode 268. Since the state of 272 is satisfactory, the film lifting phenomenon between the capacitor electrode 268 and the third protective film 272 does not occur.

The X-ray image sensing device according to the first and second embodiments of the present invention can be manufactured by the above processes.

As described above, the X-ray image sensing device formed by the manufacturing method according to the present invention has the following effects.

First, when the X-ray image sensing device is fabricated by forming a backchannel etch type TFT formed by exposing an active layer as described above, unlike the related art, a silicon insulating layer is formed on an exposed active layer of a thin film transistor. Configure more.

In this way, the leakage current (off current) that can occur in the active channel is prevented to improve the operating characteristics of the thin film transistor.

Second, by depositing a silicon insulating film formed on top of the thin film transistor and the upper portion of the storage capacitor electrode at a low temperature, not only the operating characteristics of the thin film transistor, but also the film lifting phenomenon of the storage capacitor electrode is removed to prevent product defects. It works.

Third, by forming each auxiliary pad electrode in contact with the gate pad electrode, the data pad electrode, and the ground pad electrode, a process of forming a buffer layer can be omitted, unlike in the related art, thereby simplifying the process.

In addition, there is an effect of improving the contact characteristics of the pad portion by the auxiliary pad electrode.

Claims (41)

A gate wiring formed in one direction on the substrate and a gate pad electrode connected to the gate wiring; A data line defining a pixel region by crossing the gate line vertically with a gate insulating layer interposed therebetween, and a data pad electrode connected to the data line; A thin film transistor positioned at the intersection of the two wires, the thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; A ground line formed in parallel with the data line and a ground pad electrode connected to the ground line; A first passivation layer formed on the substrate on which the thin film transistor and the ground line are formed and patterned to expose a portion of the drain electrode and a portion of the ground line; A second passivation film formed on the first passivation film and formed of the same pattern as the first passivation film, the second passivation film being a transparent organic insulating film exposing a part of the ground wiring and part of the drain electrode; A capacitor electrode in contact with the ground wiring; A third passivation layer on the capacitor electrode and including a contact hole exposing the drain electrode; The pixel electrode overlaps the capacitor electrode in a planar manner with the third passivation layer interposed therebetween, and the pixel electrode electrically connected to the exposed drain electrode. X-ray image sensing device comprising. The method of claim 1, And the gate electrode and the gate wiring are formed of a double metal layer. The method of claim 2, The first layer of the double metal layer is aluminum, the second layer is selected from the group of metals consisting of chromium (Cr), tungsten (W), molybdenum (Mo) X-ray image sensing device. The method of claim 1, And the gate pad electrode, the data pad electrode, and the ground pad electrode are made of the same material on the same layer. The method of claim 1, The gate line contacts the gate pad electrode through a gate connection line, the data line contacts the data pad electrode through a data connection line, and the ground line is connected to a ground pad electrode through a ground connection line. . The method according to any one of claims 1 to 5, And the data line and the ground line are in contact with the data connection line and the ground connection line through a contact hole formed in the gate insulating layer. The method of claim 1, An X-ray image sensing device further comprising an auxiliary electrode between the drain electrode and the pixel electrode. The method of claim 1, The pixel electrode extends to an upper portion of the source and drain electrodes. The method of claim 1, The second passivation layer is one of a group of transparent organic insulating materials including BCB (benzocyclobutene) and acrylic resin. The method of claim 1, The first insulating film is a silicon insulating film is silicon nitride (SiN _x ) or silicon oxide (SiO _X ) _X -ray image sensing device. The method of claim 1, The third passivation layer is an inorganic insulating material containing silicon nitride and silicon oxide, or an X-ray image sensing device selected from organic insulating materials containing benzocyclobutene and acrylic resin. The method according to any one of claims 10 to 11, The silicon insulating film forming the first protective film and the third protective film is an X-ray image sensing device formed by low temperature deposition. The method of claim 12, The low temperature deposition is an x-ray image sensing device made in the range of 220 ℃ to 240 ℃. The method of claim 1, And an x-ray photosensitive film formed on the pixel electrode. Forming a plurality of first buffer layers, second buffer layers, and third buffer layers on the substrate; A gate wiring and a gate electrode on the substrate on which the plurality of buffer layers are formed, a gate connection wiring extending from the gate wiring, a gate pad electrode extending above the first buffer layer on the gate connection wiring, and not parallel to the gate pad electrode. A data connection wiring formed in an area, a data pad electrode extending over the second buffer layer in the data connection wiring, a ground connection wiring spaced in parallel with the data connection wiring, and an extension of the third buffer layer in the ground connection wiring Forming a ground pad electrode; Forming an active layer and an ohmic contact layer stacked on the gate insulating layer on the gate electrode; Forming and patterning a gate insulating film, which is the first insulating film, to form a data wiring contact hole and a ground wiring contact hole exposing a portion of the data connection wiring and the ground connection wiring; A source electrode and a drain electrode in contact with the ohmic contact layer, a data line connected to the source electrode and having one end thereof in contact with the data connection wire, and one end in a pixel area, and one end of which is connected to the ground connection wire. Forming a contact ground wire; Depositing and patterning a silicon insulating film on the entire surface of the substrate on which the data wiring and the ground wiring are formed, thereby forming a first passivation layer exposing a part of the ground wiring and a part of the drain electrode; Forming a second passivation layer formed on the first passivation layer, the second passivation layer formed in the same pattern as the first passivation layer and exposing a part of the ground wiring and part of the drain electrode; Forming a transparent capacitor electrode in contact with the exposed ground wiring; Forming a third passivation layer formed on the substrate on which the capacitor electrode is formed, forming a contact hole exposing the drain electrode, and removing regions corresponding to the gate pad electrode, the data pad electrode, and the ground pad electrode; ; Forming a transparent pixel electrode which is formed in a planar manner with the capacitor first electrode and the third passivation layer interposed therebetween and electrically connected to the exposed drain electrode; Etching the second passivation layer, the first passivation layer, and the gate insulating layer to form a gate pad contact hole, a data pad contact hole, and a ground pad contact hole exposing the gate pad electrode, the data pad electrode, and the ground pad electrode; X-ray image sensing device manufacturing method comprising a. The method of claim 15, The gate electrode and the gate wiring is a double metal layer X-ray image sensing device manufacturing method. The method of claim 16, The first layer of the double metal layer is aluminum, the second layer is selected from a group of metals consisting of chromium (Cr), tungsten (W), molybdenum (Mo) X-ray image sensing device manufacturing method. The method of claim 15, And the gate pad electrode, the data pad electrode, and the ground pad electrode are formed of the same material on the same layer. The method of claim 15, The silicon insulating film as the first passivation layer is formed of one selected from silicon nitride (SiN _x ) or silicon oxide (SiO _X ). The method of claim 15, The third passivation layer is formed of an inorganic insulating material including silicon nitride (SiN _x ) and silicon oxide (SiO _X ), or one selected from organic insulating materials including benzocyclobutene (BCB) and acrylic resin. X-ray image sensing device manufacturing method. The method according to any one of claims 19 to 20, The silicon insulating film forming the first protective film and the third protective film is a low-temperature deposition x-ray image sensing device manufacturing method. The method of claim 21, The low temperature deposition is an x-ray image sensing device manufacturing method made in the range of 220 ℃ to 240 ℃. The method of claim 15, Forming an island-shaped auxiliary electrode between the pixel electrode and the drain electrode; Forming a photoconductive film on the pixel electrode; And forming a conductive electrode on the photoconductive film. The method of claim 23, The photoconductive film is a material selected from the group consisting of amorphous selenium (selenium), HgI ₂ , PbO, CdTe, CdSe, thallium bromide, cadmium sulfide. The method of claim 15, The second passivation layer is one selected from the group of transparent organic insulating materials including benzocyclobutene (BCB) and acrylic resin. The method of claim 15, And after the source and drain electrodes are formed, removing impurity amorphous silicon formed between the source and drain electrodes using the source and drain electrodes as masks. The method of claim 15, And the capacitor electrode and the pixel electrode are formed of one selected from transparent indium tin oxide (ITO) and indium zinc oxide (IZO). A gate wiring formed in one direction on the substrate and connected to a gate pad electrode having a predetermined area at one end thereof; A data line connected to the gate line vertically with a gate insulating layer interposed therebetween to define a pixel area, and one end of which is connected to a data pad electrode; A thin film transistor formed in the switching region on the substrate and including a gate electrode connected to the gate wiring, an active layer, a source electrode connected to the data wiring, and a drain electrode spaced apart from the drain electrode; A ground line formed in the pixel area in parallel with the data line and having one end connected to a ground pad electrode; A first passivation layer formed of a silicon insulating film patterned to expose a part of the ground wiring, a part of the drain electrode, a part of the data pad electrode, a part of the ground pad electrode, and a part of the gate pad electrode; A data pad auxiliary electrode, a ground pad auxiliary electrode, and a gate pad auxiliary electrode in contact with the exposed data pad electrode, the ground pad electrode, and the gate pad electrode; A second passivation layer formed on the first passivation layer, the second passivation layer being a transparent organic insulating layer exposing part of the drain electrode and the ground wiring again; A capacitor electrode in contact with the ground wiring; A third passivation layer on the capacitor electrode and exposing the drain electrode; A pixel electrode formed to overlap the capacitor electrode in a planar manner with the third passivation layer interposed therebetween and electrically connected to the exposed drain electrode; A gate pad contact hole, a data pad contact hole, and a ground pad contact hole exposing the gate pad auxiliary electrode, the data pad auxiliary electrode, and the ground pad auxiliary electrode. X-ray image sensing device comprising. The method of claim 28, And the gate electrode and the gate wiring are formed of a double metal layer. The method of claim 29, The first layer of the double metal layer is aluminum, the second layer is selected from the group of metals consisting of chromium (Cr), tungsten (W), molybdenum (Mo) X-ray image sensing device. The method of claim 28, And the data pad electrode and the ground pad electrode are formed of the same material on the same layer. The method of claim 28, An X-ray image sensing device further comprising a drain auxiliary electrode between the drain electrode and the pixel electrode. The method of claim 32, The gate pad auxiliary electrode, the data pad auxiliary electrode, and the ground pad auxiliary electrode are formed of a low resistance metal group including aluminum (Al) and an aluminum alloy. The method of claim 28, The pixel electrode extends to an upper portion of the source and drain electrodes. The method of claim 28, The second passivation layer is one of a group of transparent organic insulating materials including BCB (benzocyclobutene) and acrylic resin. The method of claim 28, The first insulating film is a silicon insulating film is silicon nitride (SiN _x ) or silicon oxide (SiO _X ) _X -ray image sensing device. The method of claim 28, The third passivation layer is an inorganic insulating material including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ), or is selected from organic insulating materials including benzocyclobutene (BCB) and acrylic resin. One x-ray image sensing device. 38. A compound according to any of claims 36 to 37, The silicon insulating film forming the first protective film and the third protective film is an X-ray image sensing device formed by low temperature deposition. The method of claim 38, The low temperature deposition is an x-ray image sensing device made in the range of 220 ℃ to 240 ℃. The method of claim 28, And an x-ray photosensitive film formed on the pixel electrode. A first mask process step of forming a gate wiring comprising a gate pad and a gate electrode on the substrate; Depositing an insulating material on the substrate on which the gate electrode is formed to form a gate insulating film as a first insulating film; A second mask process step of forming an active layer and an ohmic contact layer on the gate electrode of the first insulating layer; A source wire in contact with the ohmic contact layer, a drain electrode spaced apart from the predetermined distance, a data wire connected to the source electrode and including a data pad electrode at one end thereof, and parallel to the data wire in one direction. A third mask process step of forming a ground wiring including a ground pad electrode at an end thereof; A fourth mask process of depositing an inorganic insulating material on the entire surface of the substrate on which the source and drain electrodes are formed to form a first passivation layer, and then patterning and exposing a part of the drain electrode, the ground wiring, the data pad, the ground pad, and the gate pad Steps; Depositing and patterning a conductive metal on the first passivation layer to form a data pad auxiliary electrode, a ground pad auxiliary electrode, and a gate pad auxiliary electrode in contact with the exposed data pad electrode, the ground pad electrode, and the gate pad electrode, respectively; 5 mask process steps; A sixth mask process step of applying an organic insulating material to the entire surface of the substrate on which the pad auxiliary electrode is formed to form a second passivation layer, which is a planarization film, and then patterning the semiconductor substrate to expose a portion of the drain electrode and the ground wiring; A seventh mask process step of forming a transparent drain auxiliary electrode in contact with the exposed drain electrode and a transparent capacitor electrode in contact with the exposed ground wiring; An eighth mask process step of forming a third passivation layer by depositing a silicon insulating film on the entire surface of the substrate on which the drain auxiliary electrode and the capacitor electrode are formed, and then patterning a portion of the drain auxiliary electrode; A ninth mask process step of forming a transparent pixel electrode connected to the exposed auxiliary drain electrode and formed to overlap the capacitor electrode in a plane; A tenth mask process step of etching the third insulating film and the fourth insulating film to expose a portion of the data pad auxiliary electrode, the ground pad auxiliary electrode, and the gate pad auxiliary electrode; X-ray image sensing device manufacturing method comprising a.