KR100783638B1 - semiconductor chip package of stack type - Google Patents

semiconductor chip package of stack type Download PDF

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KR100783638B1
KR100783638B1 KR1020040029516A KR20040029516A KR100783638B1 KR 100783638 B1 KR100783638 B1 KR 100783638B1 KR 1020040029516 A KR1020040029516 A KR 1020040029516A KR 20040029516 A KR20040029516 A KR 20040029516A KR 100783638 B1 KR100783638 B1 KR 100783638B1
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semiconductor chip
attached
metal pad
solder
package
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KR1020040029516A
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Korean (ko)
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KR20050104164A (en
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김일규
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

Abstract

적층형 반도체 패키지가 개시된다. 제1관통형 메탈 패드를 갖는 제1반도체 칩과, 제2관통형 메탈 패드를 갖고, 상기 제1반도체 칩 위에 부착되는 제2반도체 칩을 포함한다. 그리고, 상기 제1관통형 메탈 패드와 제2관통형 메탈 패드 사이에는 골드 범프와, 접착 부재 및 몰딩부가 형성되어 있고, 상기 제1반도체 칩 아래에는 솔더 레지스트와 솔더부가 있고, 전기적 신호를 외부 단자로 전달하기 위한 솔더볼이 더 형성된다. 따라서, 보다 얇은 형태를 갖고, 전기적 신뢰성이 우수한 반도체 칩 패키지를 얻을 수 있다.A stacked semiconductor package is disclosed. And a first semiconductor chip having a first through metal pad, and a second semiconductor chip having a second through metal pad and attached onto the first semiconductor chip. In addition, a gold bump, an adhesive member, and a molding part are formed between the first through metal pad and the second through metal pad, a solder resist and a solder part are formed under the first semiconductor chip, and electrical signals are external terminals. Solder balls are further formed to deliver them. Therefore, a semiconductor chip package having a thinner form and excellent in electrical reliability can be obtained.

Description

적층형 반도체 칩 패키지{semiconductor chip package of stack type}Semiconductor chip package of stack type

도 1 및 도 2는 종래의 적층형 반도체 칩 패키지를 나타내는 개략적인 구성도이다.1 and 2 are schematic configuration diagrams illustrating a conventional stacked semiconductor chip package.

도 3a 내지 도 3j는 본 발명의 실시예 1에 따른 적층형 반도체 칩 패키지를 제조하는 방법을 설명하기 위한 구성도들이다.3A to 3J are configuration diagrams for describing a method of manufacturing a stacked semiconductor chip package according to a first embodiment of the present invention.

도 4는 본 발명의 실시예 2에 따른 적층형 반도체 칩 패키지를 나타내는 구성도이다.4 is a configuration diagram illustrating a stacked semiconductor chip package according to a second exemplary embodiment of the present invention.

본 발명은 적층형 반도체 패키지에 관한 것으로서, 보다 상세하게는 적어도 두 개의 반도체 패키지들을 적층하는 형태의 반도체 패키지에 관한 것이다. The present invention relates to a stacked semiconductor package, and more particularly, to a semiconductor package in which at least two semiconductor packages are stacked.

최근, 전자기기들은 경박 단소화의 추세에 있다. 이에 따라, 반도체 칩을 실장한 패키지도 고밀도의 형태를 갖추고, 경박 단소화시키는 것이 중요하다. 이에 따라, 반도체 패키지는 평면적 형태에서 적어도 두 개의 칩을 적층하는 형태로 발전되고 있다.In recent years, electronic devices are in the trend of light and thin shortening. Accordingly, it is important that the package in which the semiconductor chip is mounted also has a high density form and is light and thin. Accordingly, the semiconductor package has been developed to stack at least two chips in a planar form.

도 1은 두 개의 반도체 칩 패키지(10a, 10b)를 적층한 형태로서, 아웃 리드 들(12a, 12b)을 서로 솔더를 이용하여 적층한 구조를 갖는 반도체 칩 패키지를 나타낸다.FIG. 1 illustrates a semiconductor chip package having a structure in which two semiconductor chip packages 10a and 10b are stacked, and out leads 12a and 12b are stacked using solder.

그러나, 상기 적층 형태의 반도체 칩 패키지(10a, 10b)의 경우에는 패키지 자체를 적층함으로서 전체 높이가 높아지는 단점을 갖는다. 그리고, 아웃 리드들(12a, 12b)이 접합되므로 상부에 적층되는 패키지(10a)의 경우에는 전기적 신호의 전달을 위한 경로가 길어지는 단점을 갖는다. 아울러, 상기 아웃 리드들(12a, 12b)의 연결을 솔더링에 의해 달성하기 때문에 그 신뢰성이 결여되는 단점을 갖는다.However, the stack type semiconductor chip packages 10a and 10b have a disadvantage in that the overall height is increased by stacking the packages themselves. In addition, since the out leads 12a and 12b are bonded to each other, the package 10a stacked on the upper side has a long path for transmitting an electrical signal. In addition, since the connection of the out leads 12a and 12b is achieved by soldering, there is a disadvantage in that the reliability is lacking.

도 2는 단위 패키지 내에 두 개의 반도체 칩(20a, 20b)을 적층한 형태를 나타낸다. 이때, 두 개의 반도체 칩(20a, 20b)은 리드 프레임에 의해 연결되는데, 상기 연결은 주로 레이저를 이용한 용접에 의해 달성된다.2 illustrates a stack of two semiconductor chips 20a and 20b in a unit package. At this time, the two semiconductor chips 20a and 20b are connected by a lead frame, which is mainly achieved by welding using a laser.

그러나, 상기 적층 형태의 반도체 칩 패키지는 신호 전달을 위한 상,하 골드 와이어 간의 거리가 짧아 두 개의 반도체 칩 각각이 동시에 동작할 때 신호 간섭이 발생할 가능성이 있다. 아울러, 리드 프레임이 다운셋(downset)으로 구성되기 때문에 그 공차로 인한 불량이 발생할 수 있다. However, since the stacked semiconductor chip package has a short distance between the upper and lower gold wires for signal transmission, signal interference may occur when each of the two semiconductor chips simultaneously operates. In addition, since the lead frame is composed of a downset, a defect may occur due to the tolerance.

본 발명의 목적은 보다 얇은 형태를 갖고, 전기적 신뢰성이 우수한 반도체 칩 패키지를 제공하는데 있다.An object of the present invention is to provide a semiconductor chip package having a thinner shape and excellent electrical reliability.

상기 목적을 달성하기 위한 본 발명의 반도체 칩 패키지는, The semiconductor chip package of the present invention for achieving the above object,                     

제1관통형 메탈 패드를 갖는 제1반도체 칩;A first semiconductor chip having a first through metal pad;

제2관통형 메탈 패드를 갖고, 상기 제1반도체 칩 위에 부착되는 제2반도체 칩;A second semiconductor chip having a second penetrating metal pad and attached to the first semiconductor chip;

상기 제1관통형 메탈 패드와 제2관통형 메탈 패드 사이에 부착되고, 상기 제1반도체 칩과 제2반도체 칩을 전기적으로 연결하는 골드 범프;A gold bump attached between the first penetrating metal pad and the second penetrating metal pad and electrically connecting the first semiconductor chip and the second semiconductor chip;

상기 제1반도체 칩과 제2반도체 칩을 부착시키는 접착 부재;An adhesive member attaching the first semiconductor chip to the second semiconductor chip;

상기 제1반도체 칩과 제2반도체 칩 사이를 몰딩하는 몰딩부;A molding part for molding between the first semiconductor chip and the second semiconductor chip;

상기 제1반도체 칩 아래에 부착되는 솔더 레지스트;A solder resist attached to the first semiconductor chip;

상기 제1반도체 칩과 솔더 레지스트 사이에 부착되고, 상기 제1반도체 칩과 제2반도체 칩의 전기적 신호를 전달하는 솔더부; 및A solder part attached between the first semiconductor chip and the solder resist and transferring an electrical signal between the first semiconductor chip and the second semiconductor chip; And

상기 솔더부에 부착되고, 상기 솔더부의 전기적 신호를 외부 단자로 전달하기 위한 솔더볼을 포함한다.It is attached to the solder portion, and includes a solder ball for transmitting the electrical signal to the solder terminal.

이때, 상기 접착 부재는 테이프, 큐어링된 에폭시 또는 큐어링된 스크린 프린팅 물질인 것이 바람직하다.In this case, the adhesive member is preferably a tape, a cured epoxy or a cured screen printing material.

상기 목적을 달성하기 위한 본 발명의 다른 반도체 칩 패키지는,Another semiconductor chip package of the present invention for achieving the above object,

제1관통형 메탈 패드를 갖는 제1반도체 칩;A first semiconductor chip having a first through metal pad;

제2관통형 메탈 패드를 갖고, 상기 제1반도체 칩 위에 부착되는 제2반도체 칩;A second semiconductor chip having a second penetrating metal pad and attached to the first semiconductor chip;

상기 제1관통형 메탈 패드와 제2관통형 메탈 패드 사이에 부착되고, 상기 제1반도체 칩과 제2반도체 칩을 전기적으로 연결하는 제1골드 범프; A first gold bump attached between the first through metal pad and the second through metal pad, the first gold bump electrically connecting the first semiconductor chip and the second semiconductor chip;                     

상기 제1반도체 칩과 제2반도체 칩이 부착된 단부에 설치되고, 상기 제1반도체 칩과 제2반도체 칩을 부착할 때 균형을 잡아주는 제2골드 범프;A second gold bump installed at an end portion to which the first semiconductor chip and the second semiconductor chip are attached and balancing the first semiconductor chip and the second semiconductor chip;

상기 제1반도체 칩과 제2반도체 칩 사이를 몰딩하는 몰딩부;A molding part for molding between the first semiconductor chip and the second semiconductor chip;

상기 제1반도체 칩 아래에 부착되는 솔더 레지스트; 및A solder resist attached to the first semiconductor chip; And

상기 제1반도체 칩과 솔더 레지스트 사이에 부착되고, 상기 제1반도체 칩과 제2반도체 칩의 전기적 신호를 전달하고, 그 단부에 외부 단자와의 연결을 위한 연결 부재를 갖는 솔더부를 포함한다.And a solder part attached between the first semiconductor chip and the solder resist and transmitting electrical signals between the first semiconductor chip and the second semiconductor chip and having a connection member at an end thereof for connection with an external terminal.

(실시예)(Example)

이하, 본 발명의 바람직한 실시예를 첨부한 도면에 따라서 더욱 상세히 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

실시예 1Example 1

도 3a 내지 도 3j는 본 발명의 실시예 1에 따른 적층형 반도체 칩 패키지를 제조하는 방법을 설명하기 위한 구성도들이다.3A to 3J are configuration diagrams for describing a method of manufacturing a stacked semiconductor chip package according to a first embodiment of the present invention.

먼저, 약 280㎛ 이하의 두께를 갖고, 제1관통형 메탈 패드(30a)를 갖는 제1반도체 칩(30)을 마련한다. 그리고, 상기 제1반도체 칩(30)의 일면에 에폭시와 같은 접착 부재(32)를 도포한다. 이때, 상기 접착 부재(32)가 도포되는 일면은 제2반도체 칩(40)과 부착될 부분이다. 이어서, 상기 제1관통형 메탈 패드(30a)에 골드 범프(34)를 형성한다. 상기 골드 범프(34)는 전기적 연결을 위한 부분이다.First, a first semiconductor chip 30 having a thickness of about 280 μm or less and having a first through metal pad 30a is prepared. Then, an adhesive member 32 such as epoxy is coated on one surface of the first semiconductor chip 30. In this case, one surface to which the adhesive member 32 is applied is a portion to be attached to the second semiconductor chip 40. Subsequently, gold bumps 34 are formed on the first through metal pad 30a. The gold bump 34 is part for electrical connection.

그리고, 약 280㎛ 이하의 두께를 갖고, 제2관통형 메탈 패드(40a)를 갖는 제2반도체 칩(40)을 마련한다. 이어서, 상기 제2반도체 칩(40)을 제1반도체 칩(30) 위에 위치시키고, 접착을 실시한다. 이때, 상기 제2반도체 칩(40)과 접착되는 제1반도체 칩(30)의 일면은 앞서 설명한 바와 같이 접착 부재(32)가 도포되어 있는 부분이다. 이와 같이, 상기 제1반도체 칩(30)과 제2반도체 칩(40)의 부착을 실시한 후, 상기 부착을 강화시키기 위하여 큐어링을 실시한다.Then, a second semiconductor chip 40 having a thickness of about 280 μm or less and having a second penetrating metal pad 40a is provided. Subsequently, the second semiconductor chip 40 is placed on the first semiconductor chip 30 and adhesion is performed. In this case, one surface of the first semiconductor chip 30 to be bonded to the second semiconductor chip 40 is a portion to which the adhesive member 32 is coated as described above. As described above, after the first semiconductor chip 30 and the second semiconductor chip 40 are attached, curing is performed to strengthen the adhesion.

계속해서, 상기 제1반도체 칩(30)과 제2반도체 칩(40)이 부착된 패키지를 봉지하기 위한 몰딩을 실시한다. 이때, 상기 몰딩은 인젝터를 사용하여 실시하는데, 반도체 칩들의 앞측면에서부터 몰딩이 이루어지도록 실시한다. 이에 따라, 상기 제1반도체 칩(30)과 제2반도체 칩(40)이 부착된 부분에는 몰딩부(36)가 형성된다.Subsequently, molding for encapsulating the package to which the first semiconductor chip 30 and the second semiconductor chip 40 are attached is performed. In this case, the molding is performed using an injector, and molding is performed from the front surface of the semiconductor chips. Accordingly, the molding part 36 is formed at a portion where the first semiconductor chip 30 and the second semiconductor chip 40 are attached.

그리고, 상기 제1반도체 칩(30)과 제2반도체 칩(40) 중에서 보텀 부분으로 이루어지는 것을 정하는데, 실시예 1에서는 제1반도체 칩(30)을 보텀 부분으로 정의한다. 따라서, 상기 제1반도체 칩(30)의 이면 즉, 제2반도체 칩(40)이 부착되지 않는 면에 솔더 레지스트(38)를 도포한다. 그리고, 에칭을 실시하여 상기 제1반도체 칩(30)의 패드(30a) 부분과 전기적으로 연결을 위한 부분의 솔더 레지스트(38)를 제거한다.The bottom portion of the first semiconductor chip 30 and the second semiconductor chip 40 is determined. In the first embodiment, the first semiconductor chip 30 is defined as the bottom portion. Accordingly, the solder resist 38 is applied to the back surface of the first semiconductor chip 30, that is, the surface on which the second semiconductor chip 40 is not attached. Then, etching is performed to remove the solder resist 38 in the portion for electrically connecting the pad 30a portion of the first semiconductor chip 30.

이어서, 상기 일부분이 제거된 솔더 레지스트(38) 상에 전기적 연결을 위한 솔더를 디스펜싱한다. 이에 따라, 솔더부(42)가 형성된다. 그리고, 상기 솔더부(42) 상에 다시 솔더 레지스트(38)를 도포하고, 에칭을 통하여 전기적 연결을 위한 부분을 제거한다. 즉, 솔더 볼(44)이 부착될 부분의 솔더 레지스트(38)를 제거하여 부분적으로 솔더부(42)를 노출시키는 것이다. 이와 같이, 노출된 솔더부(42)에 솔더 볼(44)을 부착함으로서 적층형 반도체 칩 패키지를 얻는다. Subsequently, a solder for electrical connection is dispensed onto the solder resist 38 from which the portion has been removed. As a result, the solder portion 42 is formed. Then, the solder resist 38 is again applied on the solder portion 42, and the portion for electrical connection is removed by etching. That is, the solder portion 42 is partially exposed by removing the solder resist 38 to which the solder ball 44 is to be attached. Thus, by attaching the solder ball 44 to the exposed solder portion 42, a laminated semiconductor chip package is obtained.                     

즉, 제1관통형 메탈 패드(30a)를 갖는 제1반도체 칩(30)과, 제2관통형 메탈 패드(40a)를 갖고, 상기 제1반도체 칩(30) 위에 부착되는 제2반도체 칩(40)과, 상기 제1관통형 메탈 패드(30a)와 제2관통형 메탈 패드(40a) 사이에 부착되는 골드 범프(34)와, 상기 제1반도체(30) 칩과 제2반도체 칩(40)을 부착시키는 접착 부재(32)와, 상기 제1반도체 칩(30)과 제2반도체 칩(40) 사이를 몰딩하는 몰딩부(36)와, 상기 제1반도체 칩(30) 아래에 부착되는 솔더 레지스트(38)와, 상기 제1반도체 칩(30)과 솔더 레지스트(38) 사이에 부착되는 솔더부(42) 및 상기 솔더부(42)에 부착되는 솔더 볼(44)을 포함하는 적층형 반도체 칩 패키지를 얻는 것이다.That is, a second semiconductor chip 30 having a first semiconductor chip 30 having a first through metal pad 30a and a second through metal pad 40a, and attached to the first semiconductor chip 30. 40, a gold bump 34 attached between the first through metal pad 30a and the second through metal pad 40a, the first semiconductor chip 30 and the second semiconductor chip 40. ) Is attached to the adhesive member 32 for attaching the first member, the molding part 36 for molding between the first semiconductor chip 30 and the second semiconductor chip 40, and the bottom of the first semiconductor chip 30. A stacked semiconductor including a solder resist 38, a solder portion 42 attached between the first semiconductor chip 30 and the solder resist 38, and a solder ball 44 attached to the solder portion 42. To get the chip package.

실시예 1에 의하여 얻는 반도체 칩 패키지의 경우에는 솔더를 이용하여 전기적 연결을 달성하기 때문에 인터커넥션을 위한 공정이 매우 용이하다. 그리고, 와이어 본딩을 이용하지 않기 때문에 불량률의 감소 및 비용 절감을 얻을 수 있다. 아울러, 몰딩부가 반도체 칩 전체를 둘러싸지 않기 때문에 경박 단소한 패키지를 얻을 수 잇다. 또한, 솔더 자체에 솔더 볼이 접합됨으로서 접합 부위에서의 불량을 충분하게 줄일 수 있다.In the case of the semiconductor chip package obtained in Example 1, the process for interconnection is very easy since the electrical connection is achieved using solder. In addition, since wire bonding is not used, a reduction in defect rate and cost reduction can be obtained. In addition, since the molding part does not surround the entire semiconductor chip, a light and simple package can be obtained. In addition, since solder balls are bonded to the solder itself, defects at the joining site can be sufficiently reduced.

실시예 2Example 2

실시예 2의 반도체 칩 패키지는 실시예 1의 솔더 볼이 형성된 부분과 골드 범프를 제외하고는 실시예 1과 동일한 구조를 갖는다. 즉, 솔더부(68)의 단부에 연결을 위한 단자(68a)를 더 형성하는 것이다. 이때, 상기 단자(68a)는 솔더부(68)를 형성한 후, 리플로우를 통하여 얻을 수 있다. 때문에, 실시예 1의 솔더 볼의 생략 이 가능하다. 아울러, 실시예 2는 제1반도체 칩(50)의 제1관통형 메탈 패드(50a)와 제2반도체 칩(60)의 제2관통형 메탈 패드(60a)의 전기적 연결을 위한 제1골드 범프(62a) 이외에도 균형을 잡기 위한 제2골드 범프(62b)를 더 포함한다.The semiconductor chip package of Example 2 has the same structure as that of Example 1 except for the portions where the solder balls of Example 1 are formed and the gold bumps. That is, the terminal 68a for connection is further formed at the end of the solder portion 68. In this case, the terminal 68a may be obtained through reflow after forming the solder portion 68. Therefore, the solder ball of Example 1 can be omitted. In addition, Example 2 is a first gold bump for the electrical connection of the first through-type metal pad 50a of the first semiconductor chip 50 and the second through-type metal pad 60a of the second semiconductor chip 60. In addition to 62a, a second gold bump 62b for balancing is further included.

이에 따라, 실시예 2의 반도체 칩 패키지는 제1관통형 메탈 패드(50a)를 갖는 제1반도체 칩(50)과, 제2관통형 메탈 패드(60a)를 갖고, 상기 제1반도체 칩(50) 위에 부착되는 제2반도체 칩(60)을 포함한다. 그리고, 상기 제1관통형 메탈 패드(50a)와 제2관통형 메탈 패드(60a) 사이에 부착되는 제1골드 범프(62a)와 상기 제1반도체 칩(50)과 제2반도체 칩(60)이 부착된 단부에 설치됨으로서 상기 제1반도체 칩(50)과 제2반도체 칩(60)을 부착할 때 균형을 잡아주는 제2골드 범프(62b)를 포함한다. 아울러, 상기 제1반도체 칩(50)과 제2반도체 칩(60) 사이를 몰딩하는 몰딩부(64)와 상기 제1반도체 칩(50) 아래에 부착되는 솔더 레지스트(66) 및 상기 제1반도체 칩(50)과 제2반도체 칩(60)의 전기적 신호를 전달하고, 그 단부에 외부 단자와의 연결을 위한 연결 부재인 단자(68a)를 갖는 솔더부(68)를 포함한다.Accordingly, the semiconductor chip package of Example 2 has the first semiconductor chip 50 having the first through metal pad 50a and the second through metal pad 60a, and the first semiconductor chip 50 as described above. ) And a second semiconductor chip 60 attached thereto. The first gold bump 62a and the first semiconductor chip 50 and the second semiconductor chip 60 are attached between the first through metal pad 50a and the second through metal pad 60a. The second gold bump 62b is provided at the attached end to balance the first semiconductor chip 50 and the second semiconductor chip 60. In addition, a molding portion 64 for molding between the first semiconductor chip 50 and the second semiconductor chip 60, a solder resist 66 attached to the bottom of the first semiconductor chip 50, and the first semiconductor. It includes a solder portion 68 for transmitting an electrical signal between the chip 50 and the second semiconductor chip 60, and having a terminal 68a, which is a connection member for connection with an external terminal, at an end thereof.

실시예 1과 마찬가지로, 실시예 2에 의하여 얻는 반도체 칩 패키지의 경우에도 솔더를 이용하여 전기적 연결을 달성하기 때문에 인터커넥션을 위한 공정이 매우 용이하다. 그리고, 와이어 본딩을 이용하지 않기 때문에 불량률의 감소 및 비용 절감을 얻을 수 있다. 아울러, 몰딩부가 반도체 칩 전체를 둘러싸지 않기 때문에 경박 단소한 패키지를 얻을 수 잇다. 특히, 솔더 볼을 사용하지 않기 때문에 비용 절감 측면에서 더욱 유리하다.As in the first embodiment, the semiconductor chip package obtained in the second embodiment is also very easy to interconnect because the electrical connection is achieved using solder. In addition, since wire bonding is not used, a reduction in defect rate and cost reduction can be obtained. In addition, since the molding part does not surround the entire semiconductor chip, a light and simple package can be obtained. In particular, since it does not use solder balls, it is more advantageous in terms of cost reduction.

이와 같이, 본 발명에 의하면 경박 단소한 반도체 칩 패키지의 획득 뿐만 아니라 전기적 신뢰성이 우수한 반도체 칩 패키지의 획득이 가능하다. As described above, according to the present invention, not only the light and simple semiconductor chip package can be obtained but also the semiconductor chip package having excellent electrical reliability can be obtained.

상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (3)

제1관통형 메탈 패드를 갖는 제1반도체 칩;A first semiconductor chip having a first through metal pad; 제2관통형 메탈 패드를 갖고, 상기 제1반도체 칩 위에 부착되는 제2반도체 칩;A second semiconductor chip having a second penetrating metal pad and attached to the first semiconductor chip; 상기 제1관통형 메탈 패드와 제2관통형 메탈 패드 사이에 부착되고, 상기 제1반도체 칩과 제2반도체 칩을 전기적으로 연결하는 골드 범프;A gold bump attached between the first penetrating metal pad and the second penetrating metal pad and electrically connecting the first semiconductor chip and the second semiconductor chip; 상기 제1반도체 칩과 제2반도체 칩을 부착시키는 접착 부재;An adhesive member attaching the first semiconductor chip to the second semiconductor chip; 상기 제1반도체 칩과 제2반도체 칩 사이를 몰딩하는 몰딩부;A molding part for molding between the first semiconductor chip and the second semiconductor chip; 상기 제1반도체 칩 아래에 부착되는 솔더 레지스트;A solder resist attached to the first semiconductor chip; 상기 제1반도체 칩과 솔더 레지스트 사이에 부착되고, 상기 제1반도체 칩과 제2반도체 칩의 전기적 신호를 전달하는 솔더부; 및A solder part attached between the first semiconductor chip and the solder resist and transferring an electrical signal between the first semiconductor chip and the second semiconductor chip; And 상기 솔더부에 부착되고, 상기 솔더부의 전기적 신호를 외부 단자로 전달하기 위한 솔더볼을 포함하는 적층형 반도체 칩 패키지.And a solder ball attached to the solder part and including a solder ball for transmitting an electrical signal to the solder part to an external terminal. 제1항에 있어서, 상기 접착 부재는 테이프, 큐어링된 에폭시 또는 큐어링된 스크린 프린팅 물질인 것을 특징으로 하는 적층형 반도체 칩 패키지.The stacked semiconductor chip package of claim 1, wherein the adhesive member is a tape, cured epoxy, or cured screen printing material. 제1관통형 메탈 패드를 갖는 제1반도체 칩;A first semiconductor chip having a first through metal pad; 제2관통형 메탈 패드를 갖고, 상기 제1반도체 칩 위에 부착되는 제2반도체 칩;A second semiconductor chip having a second penetrating metal pad and attached to the first semiconductor chip; 상기 제1관통형 메탈 패드와 제2관통형 메탈 패드 사이에 부착되고, 상기 제1반도체 칩과 제2반도체 칩을 전기적으로 연결하는 제1골드 범프;A first gold bump attached between the first through metal pad and the second through metal pad, the first gold bump electrically connecting the first semiconductor chip and the second semiconductor chip; 상기 제1반도체 칩과 제2반도체 칩이 부착된 단부에 설치되고, 상기 제1반도체 칩과 제2반도체 칩을 부착할 때 균형을 잡아주는 제2골드 범프;A second gold bump installed at an end portion to which the first semiconductor chip and the second semiconductor chip are attached and balancing the first semiconductor chip and the second semiconductor chip; 상기 제1반도체 칩과 제2반도체 칩 사이를 몰딩하는 몰딩부;A molding part for molding between the first semiconductor chip and the second semiconductor chip; 상기 제1반도체 칩 아래에 부착되는 솔더 레지스트; 및A solder resist attached to the first semiconductor chip; And 상기 제1반도체 칩과 솔더 레지스트 사이에 부착되고, 상기 제1반도체 칩과 제2반도체 칩의 전기적 신호를 전달하고, 그 단부에 외부 단자와의 연결을 위한 연결 부재를 갖는 솔더부를 포함하는 적층형 반도체 칩 패키지.A multilayer semiconductor attached between the first semiconductor chip and the solder resist, the solder part including a solder part having a connection member for transmitting an electrical signal between the first semiconductor chip and the second semiconductor chip and connecting to an external terminal at an end thereof; Chip package.
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