KR100781865B1 - Method for manufacturing of semiconductor device - Google Patents

Method for manufacturing of semiconductor device Download PDF

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KR100781865B1
KR100781865B1 KR1020060070194A KR20060070194A KR100781865B1 KR 100781865 B1 KR100781865 B1 KR 100781865B1 KR 1020060070194 A KR1020060070194 A KR 1020060070194A KR 20060070194 A KR20060070194 A KR 20060070194A KR 100781865 B1 KR100781865 B1 KR 100781865B1
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South Korea
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storage electrode
film
layer
silicon carbide
etch stop
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KR1020060070194A
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Korean (ko)
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김석민
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to secure capacitance of a lower electrode and to prevent collapse of the lower electrode by forming a crystal silicon carbide(SiC) whisker on a surface of a crystal silicon layer. An interlayer dielectric(13) including a storage electrode contact(15) is formed on an upper portion of a semiconductor substrate(11) where a predetermined lower structure is formed. An etch stop layer(17) and an oxide layer for a storage electrode are formed on an upper portion of the interlayer dielectric. The oxide layer for a storage electrode and the etch stop layer are etched by a photo-etch process using a storage electrode mask to form a trench. A crystal silicon layer(23) is deposited in the trench to form a lower electrode. The oxide layer for a storage electrode is removed by performing a full dip-out process. A crystal silicon carbide(SiC) whisker is grown on a surface of the crystal silicon layer by CVD. A dielectric and an upper electrode are formed on an upper portion of the crystal silicon carbide whisker.

Description

반도체 소자의 제조방법{METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 제조방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11 : 반도체 기판 13 : 층간절연막      11 semiconductor substrate 13 interlayer insulating film

15 : 저장전극 콘택 17 : 식각정지막      15: storage electrode contact 17: etch stop film

19 : 저장전극용 절연막 23 : 결정질 실리콘막      19: insulating film for storage electrode 23: crystalline silicon film

25 : 실리콘 카바이드(SiC) 휘스커       25: Silicon Carbide (SiC) Whiskers

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 실린더 구조의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor having a cylinder structure.

최근 반도체 메모리 소자로서 고용량을 갖는 디램(DRAM)소자가 이용되고 있다. Recently, a DRAM device having a high capacity has been used as a semiconductor memory device.

디램소자는 전하의 형태로 정보 데이타를 저장하는 메모리 셀 영역과 데이터 의 입출력을 위한 주변회로 영역으로 구성되며, 기본적으로 하나의 트랜지스터와, 하나의 캐패시터를 구비한다. The DRAM element includes a memory cell region for storing information data in the form of electric charge and a peripheral circuit region for inputting / outputting data, and basically includes one transistor and one capacitor.

그런데, 메모리 소자가 고집적화되어 디자인 룰이 작아짐에 따라 캐패시터의 정전 용량을 확보하는데 어려움이 있다. However, as the memory devices are highly integrated and the design rules become smaller, it is difficult to secure the capacitance of the capacitor.

이에 대한 방안으로 캐패시터 하부 전극을 실린더(Cylinder) 구조, 콘케이브(Concave) 구조 등의 3차원 구조로 형성하고 있다. As a solution to this, the lower electrode of the capacitor is formed into a three-dimensional structure such as a cylinder structure and a concave structure.

실린더 구조는 산화막에 저장전극이 형성될 트렌치를 만들고, 트렌치의 내측에 티타늄 질화(TiN)막을 증착하여 하부전극을 형성한 후, 산화막을 제거하기 위한 풀 딥-아웃(full dip-out) 공정을 실시하고, 유전체막 및 상부전극을 형성하는 형태이다.The cylinder structure forms a trench for forming a storage electrode in the oxide film, deposits a titanium nitride (TiN) film inside the trench to form a lower electrode, and then performs a full dip-out process for removing the oxide film. The dielectric film and the upper electrode are formed.

그러나, 메모리 소자의 집적도가 점점 더 증가되어 실린더 구조의 캐패시터도 제조되는 전극의 형태가 그 폭은 점점 더 좁아지고, 높이는 점점 더 높아지고 있는 실정이다. However, the degree of integration of memory devices is increasing, so that the shape of the electrode for which the capacitor of the cylindrical structure is also manufactured is getting narrower in width and higher in height.

이 경우, 산화물을 제거하기 위한 풀 딥-아웃(full dip-out) 공정 후 하부전극이 스스로 지탱하지 못하고 쓰러지면서 이웃한 캐패시터와 붙는 현상을 유발함으로써 소자 페일(fail)이 발생되는 문제점이 있다. In this case, after the full dip-out process for removing the oxide, the lower electrode fails to support itself, causing the device to fail due to the phenomenon of sticking with neighboring capacitors.

본 발명은 상기와 같은 문제점을 해결하기 위하여 창출된 것으로, 실린더 구조의 캐패시터가 쓰러지는 현상을 방지할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of preventing the capacitor from collapsing in a cylinder structure.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, The semiconductor device manufacturing method of the present invention for achieving the above object,

소정의 하부구조물이 구비된 반도체 기판 상부에 저장전극 콘택을 포함한 층간절연막을 형성하는 단계;Forming an interlayer insulating film including a storage electrode contact on a semiconductor substrate having a predetermined substructure;

층간절연막 상부에 식각정지막, 저장전극용 산화막을 형성하는 단계;Forming an etch stop film and an oxide film for a storage electrode on the interlayer insulating film;

저장전극 마스크를 이용한 사진 식각공정으로 저장전극용 산화막, 식각정지막을 식각하여 트렌치를 형성하는 단계;Forming a trench by etching the oxide layer and the etch stop layer for the storage electrode by a photolithography process using the storage electrode mask;

트렌치 내측에 결정질 실리콘막을 증착하여 하부전극을 형성하는 단계;Depositing a crystalline silicon film inside the trench to form a lower electrode;

풀 딥-아웃(full dip-out) 공정을 수행하여 저장전극용 산화막을 제거하는 단계;Removing the oxide film for the storage electrode by performing a full dip-out process;

화학기상증착법(CVD)을 이용하여 결정질 실리콘막의 표면에 결정질의 실리콘 카바이드(SiC) 휘스커(whisker)를 성장시키는 단계; 및Growing crystalline silicon carbide (SiC) whiskers on the surface of the crystalline silicon film using chemical vapor deposition (CVD); And

결정질의 실리콘 카바이드 휘스커 상부에 유전체막 및 상부전극을 형성하는 단계Forming a dielectric film and an upper electrode on the crystalline silicon carbide whisker

를 포함하는 것을 특징으로 한다.Characterized in that it comprises a.

그리고, 본 발명의 저장전극 콘택은 폴리실리콘층으로 형성하는 것과,In addition, the storage electrode contact of the present invention is formed of a polysilicon layer,

식각정지막은 질화막으로 형성하는 것과,The etch stop layer is formed of a nitride layer,

화학기상증착법(CVD)은 실리콘 카바이드 휘스커의 구성성분이 되는 탄소와 실리콘 원소를 함유하고 있는 기체원료를 진공 쳄버에 유입시키고, 활성화 에너지로 열을 가해주어 기체원료에 화학적 반응을 유발시키는 방법으로 수행하는 것Chemical Vapor Deposition (CVD) is a method in which a gaseous material containing carbon and silicon elements, which are components of a silicon carbide whisker, is introduced into a vacuum chamber and heated with activation energy to cause a chemical reaction in the gaseous material. To do

삭제delete

을 특징으로 한다.It is characterized by.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 제조방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 1a를 참조하면, 소정의 하부구조물이 구비된 반도체 기판(11) 상부에 층간절연막(13)을 형성한다.Referring to FIG. 1A, an interlayer insulating layer 13 is formed on a semiconductor substrate 11 having a predetermined substructure.

그 다음, 저장전극 콘택마스크를 이용한 사진 식각공정으로 상기 층간절연막(13)을 식각하여 저장전극 콘택(15)을 형성한다.Next, the interlayer insulating layer 13 is etched by a photolithography process using a storage electrode contact mask to form a storage electrode contact 15.

이때, 상기 저장전극 콘택(15)은 폴리실리콘층으로 형성하는 것이 바람직하다.In this case, the storage electrode contact 15 is preferably formed of a polysilicon layer.

그 다음, 상기 층간절연막(13) 상부에 식각정지막(17)을 형성한다.Next, an etch stop layer 17 is formed on the interlayer insulating layer 13.

이때, 상기 식각정지막(17)은 질화막으로 형성하는 것이 바람직하다.In this case, the etch stop film 17 is preferably formed of a nitride film.

그 다음, 상기 식각정지막(17) 상부에 저장전극용 절연막(19)을 형성한다.Next, an insulating layer 19 for a storage electrode is formed on the etch stop layer 17.

이때, 상기 저장전극용 절연막(19)은 산화막으로 형성하는 것이 바람직하다.At this time, the storage electrode insulating film 19 is preferably formed of an oxide film.

그 다음, 저장전극 마스크(미도시)를 이용한 사진 식각공정으로 상기 저장전극용 절연막(19) 및 상기 식각정지막(17)을 식각하여 트렌치(21)를 형성한다.Next, a trench 21 is formed by etching the storage electrode insulating layer 19 and the etch stop layer 17 by a photolithography process using a storage electrode mask (not shown).

도 1b를 참조하면, 상기 트렌치(21) 내측에 결정질 실리콘막(23)을 증착하여 하부전극을 형성한다.Referring to FIG. 1B, the lower electrode is formed by depositing a crystalline silicon film 23 inside the trench 21.

도 1c를 참조하면, 풀 딥-아웃(full dip-out) 공정을 수행하여 상기 저장전극용 절연막(19)을 제거한다.Referring to FIG. 1C, the storage electrode insulating layer 19 is removed by performing a full dip-out process.

도 1d를 참조하면, 화학기상증착법(CVD; Chemical Mechanical Deposition)을 이용하여 상기 결정질 실리콘막(23)의 표면에 결정질의 실리콘 카바이드(SiC) 휘스커(whisker)(25)를 성장시킨다.Referring to FIG. 1D, crystalline silicon carbide (SiC) whiskers 25 are grown on the surface of the crystalline silicon film 23 using chemical mechanical deposition (CVD).

여기서, 화학기상증착법은 상기 실리콘 카바이드 휘스커(25)의 구성성분이 되는 탄소와 실리콘 원소를 함유하고 있는 기체원료를 진공 쳄버에 유입시키고, 활성화 에너지로 열을 가해주어 기체원료에 화학적 반응을 유발시키는 방법으로 수행하는 것이 바람직하다.Here, the chemical vapor deposition method introduces a gas raw material containing carbon and silicon elements, which are components of the silicon carbide whisker 25, into a vacuum chamber, and heats it with activation energy to cause a chemical reaction to the gas raw material. It is preferable to carry out by the method.

이러한 화학기상증착법에 의해 상기 실리콘 카바이드 휘스커(25)가 침상 구조로 성장되어 하부전극의 표면적이 증가된다. By the chemical vapor deposition method, the silicon carbide whisker 25 is grown in a needle-like structure to increase the surface area of the lower electrode.

이후, 상기 실리콘 카바이드 휘스커(25) 상부에 유전체막(미도시) 및 상부전극(미도시)을 형성하여 캐패시터를 완성한다.Subsequently, a dielectric film (not shown) and an upper electrode (not shown) are formed on the silicon carbide whisker 25 to complete the capacitor.

따라서, 하부전극의 정전용량을 확보하면서 높이를 낮게 형성할 수 있어 높은 높이에 의한 하부전극의 쓰러짐 현상을 방지할 수 있다.Therefore, the height can be formed low while securing the capacitance of the lower electrode, thereby preventing the lower electrode from falling down due to the high height.

이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 소자의 제조방법은 결정질 실리콘막을 하부전극으로 형성하고, 결정질 실리콘막 표면에 침상 구조의 실리콘 카바이드(SiC) 휘스커(whisker)를 형성함으로써 하부전극의 정전용량을 확보하면서 높이를 낮게 형성할 수 있어 하부전극이 쓰러지는 현상을 방지할 수 있는 효 과를 제공한다.As described above, in the method of manufacturing a semiconductor device according to the present invention, the capacitance of the lower electrode is formed by forming a crystalline silicon film as a lower electrode and forming a needle-shaped silicon carbide (SiC) whisker on the surface of the crystalline silicon film. It is possible to form a low height while ensuring the effect of preventing the fall of the lower electrode.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허 청구 범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

소정의 하부구조물이 구비된 반도체 기판 상부에 저장전극 콘택을 포함한 층간절연막을 형성하는 단계;Forming an interlayer insulating film including a storage electrode contact on a semiconductor substrate having a predetermined substructure; 상기 층간절연막 상부에 식각정지막, 저장전극용 산화막을 형성하는 단계;Forming an etch stop film and an oxide film for a storage electrode on the interlayer insulating film; 저장전극 마스크를 이용한 사진 식각공정으로 상기 저장전극용 산화막, 상기 식각정지막을 식각하여 트렌치를 형성하는 단계;Forming a trench by etching the storage electrode oxide layer and the etch stop layer by a photolithography process using a storage electrode mask; 상기 트렌치 내측에 결정질 실리콘막을 증착하여 하부전극을 형성하는 단계;Depositing a crystalline silicon film inside the trench to form a lower electrode; 풀 딥-아웃(full dip-out) 공정을 수행하여 상기 저장전극용 산화막을 제거하는 단계;Removing the oxide for the storage electrode by performing a full dip-out process; 화학기상증착법(CVD)을 이용하여 상기 결정질 실리콘막의 표면에 결정질의 실리콘 카바이드(SiC) 휘스커(whisker)를 성장시키는 단계; 및Growing crystalline silicon carbide (SiC) whiskers on the surface of the crystalline silicon film using chemical vapor deposition (CVD); And 상기 결정질의 실리콘 카바이드 휘스커 상부에 유전체막 및 상부전극을 형성하는 단계Forming a dielectric film and an upper electrode on the crystalline silicon carbide whisker 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, 상기 저장전극 콘택은 폴리실리콘층으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the storage electrode contact is formed of a polysilicon layer. 제 1 항에 있어서, 상기 식각정지막은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the etch stop layer is formed of a nitride layer. 삭제delete 제 1 항에 있어서, 상기 화학기상증착법(CVD)은 상기 실리콘 카바이드 휘스커의 구성성분이 되는 탄소와 실리콘 원소를 함유하고 있는 기체원료를 진공 쳄버에 유입시키고, 활성화 에너지로 열을 가해주어 기체원료에 화학적 반응을 유발시키는 방법으로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.2. The chemical vapor deposition method of claim 1, wherein the chemical vapor deposition (CVD) introduces a gaseous material containing carbon and a silicon element as a constituent of the silicon carbide whisker into a vacuum chamber, and heats the gaseous raw material with activation energy. A method for manufacturing a semiconductor device, characterized in that performed by a method of inducing a chemical reaction.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010087910A (en) * 2000-03-09 2001-09-26 장인순 Method of fabricating high density fiber reinforced SiC matrix composite by Chemical vapor infiltration process
KR20040057788A (en) * 2002-12-26 2004-07-02 주식회사 하이닉스반도체 Method for fabrication of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010087910A (en) * 2000-03-09 2001-09-26 장인순 Method of fabricating high density fiber reinforced SiC matrix composite by Chemical vapor infiltration process
KR20040057788A (en) * 2002-12-26 2004-07-02 주식회사 하이닉스반도체 Method for fabrication of semiconductor device

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