KR20050002381A - Method of Fabricating Semiconductor Memory Device Capacitor - Google Patents

Abstract

PURPOSE: A method of manufacturing a capacitor of a semiconductor memory device is provided to prevent adjacent lower electrodes from contacting with each other due to leaning by supporting the lower electrode with a first insulating layer and to increase effective surface area of the lower electrode by performing a surface treatment on the lower electrode using sequentially an ion-implantation and a heat treatment. CONSTITUTION: A first insulating layer(12) and a second insulating layer are sequentially deposited on a semiconductor substrate. A trench is formed in the resultant structure. A lower electrode(14) is formed along an inner surface of the trench. An ion-implantation and a heat treatment are sequentially performed on the lower electrode, so that the surface of the lower electrode becomes rough. The second insulating layer is removed therefrom. At this time, the lower electrode is supported by the first insulating layer. A dielectric film(15) and an upper electrode(16) are sequentially formed thereon.

Description

Capacitor manufacturing method of semiconductor memory device {Method of Fabricating Semiconductor Memory Device Capacitor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor memory device, and more particularly, a technology for preventing a lining phenomenon and increasing a capacitor capacity by using two insulating materials having different etch rate characteristics. to be.

Recently, with the development of semiconductor device manufacturing technology, the demand for dynamic random access memory (DRAM) devices is rapidly increasing. As the number of memory cells constituting such DRAM devices increases, Occupied area is decreasing.

On the other hand, the capacitor formed in each memory cell needs a sufficient capacitance for reading the correct stored data. Accordingly, current DRAM devices require a memory cell in which a capacitor having a larger capacity while forming a smaller area is formed.

As described above, there is a method of increasing the area of the capacitor in order to secure the capacitance according to the integration of the DRAM device.

The method of increasing the area of the capacitor is a method of the three-dimensional structure of the capacitor to apply a three-dimensional structure, such as cylindrical or pin-shaped to the capacitor to increase the electrode area of the capacitor to secure the capacitance.

However, even if the structure of the capacitor is formed three-dimensionally to secure the capacitor area, there is a limit to the increase in the electrode area, and the height of the device continues to increase, causing difficulty in the subsequent contact hole etching process.

In the conventional concave cylindrical capacitor shown in Fig. 1A, the insulating film 2 and the lower electrode 3 are formed on the nitride film 1, and because of the insulating film 2, the inside of the lower electrode 3 is formed. Only volume is used as capacitance. Therefore, the concave cylindrical capacitor has to be deep in order to increase the area of the lower electrode 3, which causes difficulty in the subsequent contact hole etching process.

In the conventional dip-out cylindrical capacitor shown in FIG. 1B, the insulating film surrounding the lower electrode 3 is not etched. This structure has a problem in that the yield of the DRAM is lowered due to the occurrence of lining between the adjacent capacitors in the cleaning step.

An object of the present invention for solving the above problems is to increase the effective area of the lower electrode of the capacitor of the semiconductor memory device to secure sufficient capacitance.

Another object of the present invention is to form a double insulating film having a different density, thereby preventing the full phenomenon of full-dip-out with the lower insulating film having a high density.

Another object of the present invention is to increase the effective area of the lower area by depositing a double insulating film having different etch rate characteristics and removing the insulating film having a high etch rate through etching.

1A and 1B are cross-sectional views of a capacitor of a conventional semiconductor memory device.

2A to 2F are process diagrams illustrating a method of manufacturing a capacitor of a semiconductor memory device according to an embodiment of the present invention.

The present invention for achieving the above object is a process of depositing a first insulating film and a second insulating film of different materials in order, forming a trench in a predetermined region, forming a lower electrode in the trench, and a series of Performing impurity implantation and heat treatment on the lower electrode in an uneven manner, and removing a second insulating film to form a structure in which the lower electrode is supported by the first insulating film, And forming a top electrode on top of the dielectric film.

The present invention can be implemented in a DRAM having a capacitor.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are flowcharts illustrating a method of manufacturing a capacitor of a semiconductor memory device according to an embodiment of the present invention.

The capacitor may be manufactured in a stack structure, a cup structure, a cylinder structure, or the like, but the embodiment illustrates the cylinder structure.

Referring to FIG. 2A, a lower structure (not shown) is formed on a semiconductor substrate, and a stopper nitride 11 is deposited on the structure (not shown).

The first insulating film 12 is deposited on the nitride film 11, and the second insulating film 13 is deposited on the first insulating film 12. The first insulating film 12 is an oxide and the second insulating film 13 is a Phosphor Silicate Glass (PSG) layer.

The density of the second insulating film 13 is lower than that of the first insulating film 12, and the etch rate of the second insulating film 13 is faster than the etch rate of the first insulating film 12. Form using material. Here, the etch rate refers to the thickness of the film etched per unit time, and means the etch rate.

The first insulating film 12 is formed using a plasma chemical vapor deposition (PECVD) method. Plasma chemical vapor deposition (PECVD) is a technique in which a thin film is formed on the semiconductor substrate by chemical reaction after decomposing a gaseous compound by using an unbalanced characteristic of plasma.

The second insulating layer 13 is deposited using a thermal chemical vapor deposition (thermal CVD) method.

Referring to FIG. 2B, the first insulating layer 12 and the second insulating layer 13 are etched and dip-outed to form trenches.

Referring to FIG. 2C, after forming the lower electrode 14 in the deep-out of FIG. 2B, the adjacent capacitor is removed by removing the lower electrode formed on the second insulating layer 13 through an etch back or the like. Isolate with.

Referring to FIG. 2D, an impurity is injected or heat-treated into a polycrytalline sillicon used as the lower electrode 14 to form a rugged PSG having an uneven surface, thereby forming a rugged PSG. Increase the surface area.

The polycrystalline silicon layer is in a state where the energy state is much more unstable at the grain boundary than in the grain. When an impurity is injected or heat-treated into the polycrystalline silicon layer, the energy state tends to be stabilized to a high energy state, and impurities are collected at a crystal boundary, thereby making the bumpy lower electrode 14.

Referring to FIG. 2E, the second insulating film 13 having a high etch rate is etched and removed, and the dielectric film 15 is deposited. The effective area of the lower electrode 14 is increased by the portion where the second insulating film 13 is removed. Here, the etching process includes a dry (etch) process and a wet (wet etch) process.

As described above, the second insulating film 13 has a lower density and faster etch rate than the first insulating film 12, resulting in higher concentration of impurities and higher etching amount. Accordingly, the second insulating film 13 is etched away and removed faster than the first insulating film 12, and only the first insulating film 12 remains. The first insulating film 12 thus left prevents a short circuit between adjacent capacitors.

Referring to FIG. 2F, the upper electrode 16 is deposited on the dielectric film 15 of FIG. 2E.

As described above, the present invention includes a double insulating film having a different etch rate and a density, and removes only one of the insulating films by etching to remove the full-dip-out lining phenomenon. There is an effect of preventing with an insulating film.

In addition, by increasing the effective area of the lower electrode, the height of the capacitor is reduced and the capacitance is increased.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

(a) depositing a first insulating film and a second insulating film of different materials in order; (b) forming a trench in a predetermined region; (c) forming a lower electrode in the trench; (d) performing a series of impurity implantation and heat treatment to roughly surface the lower electrode; (e) removing the second insulating film to form a structure in which the lower electrode is supported by the first insulating film, and forming a dielectric film on the lower electrode; And (f) forming an upper electrode on the dielectric film Method for manufacturing a capacitor of a semiconductor memory device comprising a. The method of claim 1, And the second insulating film is formed of a material having a higher etch rate than that of the first insulating film. The method of claim 1, The second insulating film is a manufacturing method of the capacitor of the semiconductor memory device, characterized in that using a material having a lower density than the first insulating film. The method of claim 1, The first insulating film is an oxide film, the manufacturing method of the capacitor of the semiconductor memory device. The method according to any one of claims 1 to 4, And the first insulating layer is deposited by plasma chemical vapor deposition (PECVD).