KR100764661B1 - Plasma display panel device - Google Patents

Abstract

The present invention relates to a plasma display device employing a plurality of inductors of an energy recovery unit for forming a resonance current to separate a charge path and a discharge path, including a first capacitor and a second inductor for forming a panel capacitor and a resonance current. The energy recovery unit configured to apply the sustain signal through the first resonant current path formed by the first inductor and the sustain signal through the second resonant current path formed by the second inductor. By including the portion, there is an effect that the number of switch elements mounted in the circuit is reduced.

PDP, Sustain, Resonant Current, Energy Recovery, Inductor

Description

Plasma display panel device

1 is a driving circuit of a conventional plasma display panel;

2 is a driving circuit of the plasma display panel of the present invention;

3 is a waveform diagram of a plasma display panel of the present invention.

<Explanation of symbols on main parts of the drawings>

10: energy recovery unit 20: sustain signal applying unit

30su, 30su ': setup signal applying unit 30sd: set down signal applying unit

40sb: scan bias signal applying unit 40sp: scan pulse applying unit

The present invention relates to a plasma display device that can reduce the number of switch elements by separating a charge path and a discharge path by employing a plurality of inductors of an energy recovery unit for forming a resonance current.

Recently developed flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and the like. Among them, PDPs are in the spotlight as large display devices because they have higher luminance and luminous efficiency and wider viewing angles than other flat panel display devices.

1 shows a driving circuit of a conventional plasma display panel, which includes an energy recovery unit 1 including a panel capacitor and an inductor for forming a resonance current in order to reuse the reactive current recovered from the panel capacitor, and a sustain pulse. It is configured to include a sustain signal applying unit (2) for supplying the.

Further, a reset signal applying unit 3 for supplying a setup signal rising in the form of a ramp and a setdown signal descending in the form of a ramp, and a scan signal applying unit for supplying a scan pulse synchronously falling to the scan bias signal and the data pulse It consists of (4).

In this case, a node 1 (n1) is formed on a path through which a resonance current flows toward the panel capacitor Cp, and the setup signal is supplied to the panel capacitor through the node 1, and the setdown signal or A first path blocking switch Q12 is provided to block another path to the sustain signal applying unit 2 on the current path so that a scan pulse is supplied toward the panel capacitor.

The second path blocking switch Q13 is provided to prevent the setup signal supplied to the panel capacitor from flowing into the sustain signal applying unit 2 during the reset period.

That is, the first path blocking switch Q12 and the second path blocking switch Q13 form a resonance current / discharge current as the energy recovery unit 1 and the sustain signal applying unit 2 operate. This is supplied to the panel capacitor Cp through the current path where node 1 (n1) is present.

As described above, the first path interruption switch Q12 and the second path interruption switch Q13 connected on the path through which the resonance current and the discharge current flow are required to have a large capacity element, and there is a burden of manufacturing cost.

To this end, circuit designers increased the switch capacity by connecting a large number of switch elements such as FETs in parallel, but since current is difficult to pass through multiple switch elements at the same time, signal distortion occurs and the efficiency of switching operation is reduced. As the number of switch elements to be mounted increases, there is an increase in board size and a manufacturing cost.

In addition, when a large number of switch elements are connected on the resonance current path, a recovery rate by the energy recovery unit 1 may decrease due to a voltage drop caused by the switch element, thereby increasing power consumption of the plasma display apparatus.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and its object is to adopt a plurality of inductors of an energy recovery unit for forming a resonance current, thereby separating the supply paths of the highest sustain signal and the lowest sustain signal. The present invention provides a plasma display device capable of reducing the number.

According to an aspect of the present invention, there is provided a plasma display device including a panel capacitor, a first inductor and a second inductor for forming a resonance current, and a first capacitor current passing through the first inductor during the sustain period. An energy recovery unit for recovering power from the panel capacitor through the second inductor, and applying a highest sustain signal when a current is supplied to the panel through the first inductor, and recovering current from the panel through the second inductor. A sustain signal applying unit for applying the lowest sustain signal, a setup signal applying unit and a set down signal applying unit for supplying a waveform to the panel during a reset period connected to the path of the first resonance current, and Scan bias signal applying unit and scan connected to the path to supply the waveform to the panel during the address period Switch is characterized in that the scan driver comprises applying portion configured.

The sustain signal applying unit includes a first switch connected to the same node (node 1) and the first inductor so that the highest sustain signal is applied through the first resonance current path, and a lowest sustain signal through the second resonance current path. And a second switch connected to the same inductor (node 2) and the second inductor to be applied.

At this time, the setup switch is connected on the first resonant current path to apply a setup signal, and the set down switch is connected to the same node as the setup switch to apply a set down signal.

In addition, a path blocking element for blocking the path to the node 1 side is connected between the node 1 and the setup switch so that the setup signal is applied to the panel capacitor through the first path.

The scan switch is connected to the scan IC to apply the scan bias signal to the panel capacitor during the address period, and the scan pulse switch is also connected to the scan IC and applies the scan pulse synchronously with the data pulse.

A complementary scan switch is coupled between the node 2 and the scan switch to form a second resonant current path through which the lowest sustain signal flows.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of the plasma display device of the present invention, Figure 3 is a waveform diagram output from the circuit of the plasma display device of the present invention. The configuration of the present invention will be described in detail with reference to this.

First, the energy recovery unit 10 is a circuit for minimizing the loss caused by reactive power generated by charging the panel capacitor Cp to the sustain voltage during the sustain period and discharging it again.

The energy recovery unit 10 of the present invention includes a first inductor L1 and a second inductor L2 that form a first resonance current and a second resonance current together with the panel capacitor Cp. And a switch Q1 and Q2 connected to each inductor, and a source capacitor storing reactive power from the panel capacitor.

In this case, the panel capacitor Cp equivalently represents the capacitance formed between the scan electrode Y and the sustain electrode Z, and removes a current path passing through the first inductor L1 toward the panel capacitor. The current path that passes through the second inductor L2 to the panel capacitor is called a second resonance current path.

In the sustain signal applying unit 20, a first switch Q3 to which the highest sustain signal is applied is connected on the first resonance current path, and the connected node is referred to as node 1 (n1). Further, a second switch Q4, which is alternately connected to the first switch and applies the lowest sustain signal, is connected on the second resonance current path, and the connected node is referred to as node 2 (n2).

That is, the highest sustain signal is supplied through the node 1 (n1) and the first resonant current path, and the lowest sustain signal is supplied through the node 2 (n2) and the second resonant current path, and is supplied to the energy recovery unit 10. The current charged to the panel capacitor is supplied through the first resonant current path, and the current discharged from the panel capacitor is recovered through the second resonant current path.

In this case, the external voltage source Vsus of the highest sustain signal is illustrated as a positive voltage, and the voltage source of the lowest sustain signal is illustrated as a ground level. However, since the level of the external power supplied in the circuit differs depending on the level of the voltage of the node 1, the technical concept of the present invention is not limited by the voltage level presented in this embodiment.

In addition, whether the external power is shared or not used alone illustrated in the present embodiment is not limited, and each switch may be further connected to a switch connected to the push pull.

The reset signal applying unit includes a setup signal applying unit 30su for applying the setup signal and a setdown signal applying unit 30sd for applying the setdown signal during the reset period.

First, the setup signal applying unit 30su applies a setup signal in the form of a ramp in which the setup switch Q5 connected on the first resonant current path is turned on and rises up to the setup voltage source Vsu to the panel capacitor Cp. . A variable resistor VR1 for adjusting the slope of the ramp waveform is connected to the control terminal of the setup switch.

In addition, the set down signal applying unit 30sd supplies the panel capacitor a set down signal in the form of a lamp in which the set down switch Q6 connected on the first resonant current path is turned on to drop down to the set down voltage source -Vy. A variable resistor VR2 for adjusting the slope of the ramp waveform is connected to the control terminal of the set-down switch.

That is, as the first resonant current path to which the setup switch Q5 and the set-down switch Q6 are connected and the second resonant current path to which the second switch is connected are separated, the voltage of the panel capacitor Cp is set by the set-down switch. The conventional first path blocking switch which blocks the current path to the sustain signal applying unit 20 side during the set down period in which the level is lowered can be removed.

In addition, a path blocking element Q13 is connected between the node 1 and the setup switch Q5 to block the path to the node 1 (n1) side so that the setup signal is applied to the panel capacitor through the first resonant current path. do.

The scan signal applying unit includes a scan bias signal applying unit 40sb for applying a scan bias signal and a scan pulse applying unit 40sp for applying a scan pulse during an address period.

First, the scan bias signal applying unit 40sb includes a scan switch Q7 for applying a scan bias signal to the panel capacitor Cp in an address period, and the scan switch is connected to the scan IC.

In addition, the scan pulse applying unit 40sp includes a scan pulse switch Q8 connected to the scan IC and a scan voltage source, and as the scan pulse switch is conducted, the scan pulse voltage to the scan pulse voltage The falling scan pulse is applied to cause an address discharge. In this case, the scan pulse voltage source can be shared with the set-down voltage source (-Vy).

In addition, the scan bias signal applying unit 40sb has a complementary scan switch Q11 that is complementary to the scan switch Q7 connected to the second resonant current path, and a control terminal is connected to the complementary scan switch. A switch Q12 that is connected to be common may be connected, thereby enabling bidirectional control.

Accordingly, the complementary scan switch Q11 is turned on so that the lowest sustain signal is applied to the panel capacitor through the first resonant current path during the sustain period. In this descending section, the complementary scan switch is shielded to block the path.

In addition, a high side switch Q9 and a low side switch Q10 connected between the scan voltage source −Vy and the first node n1 in a push-pull form a scan IC. Since the output terminal between each switch is connected to the panel capacitor Cp, a scan bias signal, a signal on the first resonance current, a signal on the second resonance current, and the like are applied according to whether the switch constituting the scan IC is connected. The charging voltage of the capacitor is discharged.

In the circuit of the present invention configured as described above, the current path in the section constituting the unit subfield will be described with reference to FIG. 2, and the waveform in each section will be described with reference to FIG. 3.

First, the reset section R is a section for erasing the wall charge state formed by the previous sustain discharge and initializing the state of each cell. The reset section R is a setup section SU to which a rising setup signal is supplied, and a ramp down. down) It is divided into a set down period (SD) to which a set down signal of a waveform is supplied.

In the present invention, the setup signal is supplied via a setup switch-first resonant current path-scan IC (eighth switch) at the setup voltage source, and the setdown signal is supplied via a setdown switch-scan IC (eighth switch) at the setdown voltage source. .

The address section A is a section for selecting a cell to be discharged, and the scan bias signal is supplied from the scan bias voltage source through the scan switch-scan IC (seventh switch), and the scan pulse is scanned at the instant of synchronization with the data pulse. It is supplied from a pulse voltage source via a scan pulse switch-scan IC (eighth switch).

In addition, the sustain section S is a section in which pulses are alternately applied to the scan electrode and the sustain electrode, and the highest sustain signal is the first switch-node 1-path interruption switch-first resonant current path-scan at the highest sustain voltage source. Supply (ⓐ) through the IC (Eighth Switch), and the lowest sustain signal is supplied from the lowest sustain voltage source via the second switch-node 2-second resonant current path-complementary scan switch-scan IC (seventh switch) Ⓑ), whereby a sustain discharge is generated.

As described above with reference to the drawings illustrated with respect to the plasma display device according to the present invention, the present invention is not limited by the embodiments and drawings disclosed herein, having a general knowledge in the field to which the present invention belongs Applicability is possible within the scope of the technical idea of the present invention protected by the ruler.

The plasma display device of the present invention configured as described above adopts one or more inductors of the energy recovery unit for forming the resonance current to separate the paths of the charge current and the discharge current, and thus, a large-capacity switch element conventionally mounted to block the paths. Since it can be omitted, manufacturing cost can be reduced, and board size can be reduced.

In addition, it is possible to prevent signal distortion due to the switch element connected on the resonant current path, and the recovery rate by the energy recovery unit is also increased, thereby improving power efficiency.

Claims (8)

A first inductor and a second inductor forming a resonant current with the panel capacitor are provided, and the first resonant current passing through the first inductor during the sustain period is supplied to the panel capacitor, and is recovered from the panel capacitor through the second inductor. An energy recovery unit; a sustain signal applying unit configured to apply a highest sustain signal when a current is supplied to the panel through the first inductor, and apply a lowest sustain signal when current is recovered from the panel through the second inductor; A setup signal applying unit and a set down signal applying unit connected on the path of the first resonance current to supply a waveform to the panel during the reset period; And a scan bias signal applying unit and a scan pulse applying unit connected to the path of the first resonant current to supply a waveform to the panel during the address period. In claim 1, The sustain signal applying unit includes: a first switch connected to the same node (node 1) as the first inductor so that the highest sustain signal is applied to the panel; A second switch connected to the same node (node 2) and the second inductor to apply a lowest sustain signal to the panel; Plasma display device comprising a. In claim 1, And the setup signal applying unit is connected to a setup switch on the first resonance current path so that a setup waveform gradually rising during the reset period is applied. In claim 1, And the set down signal is connected to the set down switch on the first resonant current path so that the set down waveform is gradually applied during the reset period. In claim 3, A path blocking element for blocking a path to the first inductor even when the setup waveform is applied to the panel capacitor is connected on a first resonant current path between the first inductor and the setup switch; Device. In claim 1, The scan bias signal applying unit includes a scan switch for applying a positive scan bias signal to the panel capacitor during an address period, and the scan switch is connected to a scan IC connected to the panel capacitor. In claim 4, And the scan pulse applying unit is connected on a first resonant current path such that a scan pulse switch for applying a scan pulse that falls negatively during an address period is in parallel with the set-down switch. In claim 6, And a complementary scan switch that is complementary to the scan switch is connected to a first resonant current path through which a current of the panel capacitor is recovered during the sustain period.

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