KR100767201B1 - Plasma display panel device - Google Patents

Abstract

The present invention relates to a plasma display device, comprising: a scan switch connected between a node 1 on a resonant current path and a scan IC to apply a scan bias signal to the panel capacitor, and directly connected to the scan IC to provide a setup signal to the panel capacitor. By including an applied setup switch, the voltage across the scan switch and the first path blocking switch is reduced, thereby improving device durability, and eliminating the complementary scan switch and the second path blocking switch. This saves the effect.

PDP, Scan Switch, Breakdown Voltage, Setup Switch, Reset Section

Description

Plasma display panel device

1 is a driving circuit diagram of a conventional plasma display device;

2 shows waveforms during unit subfields in a plasma display device;

3 is a driving circuit diagram of a plasma display device of the present invention;

4 is a waveform diagram during unit subfields in the plasma display device of the present invention;

5 is a waveform diagram of a scan switch voltage in the plasma display device of the present invention;

6 is a voltage waveform diagram of a first path blocking switch in the plasma display device of the present invention.

<Explanation of symbols on main parts of the drawings>

10: energy recovery unit 20: sustain signal applying unit

30su, 30su ': setup signal applying unit 30sd: set down signal applying unit

40sb: scan bias signal applying unit 40sp: scan pulse applying unit

The present invention reduces the voltage across the scan switch for applying the scan bias signal by switching the circuit connection of the scan switch or the setup switch, while reducing the number of switch elements by switching the path of the lowest sustain signal. It relates to a display device.

Recently developed flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and the like. Among them, PDPs are in the spotlight as large display devices because they have higher luminance and luminous efficiency and wider viewing angles than other flat panel display devices.

FIG. 1 illustrates a driving circuit of a conventional plasma display panel, and includes an energy recovery unit 1, a sustain signal applying unit 2, a reset signal applying unit 3, and a scan signal applying unit 4. However, the circuit configuration of the sustain signal applying unit 2, the reset signal applying unit 3, and the scan signal applying unit 4 associated with the conventional problem will be described.

The reset signal applying unit 3 has a third switch Q3 connected between the setup voltage source Vsu and the first node n1 to be turned on so that the setup signal rising up to the setup voltage source is supplied to the first node. The fourth switch Q4 is turned on to supply the first node with the setdown signal falling down to the setdown voltage source -Vy.

During the address period, the scan signal applying unit 4 conducts the fifth switch Q5 to raise the scan bias voltage source (-Vsus / 2) from the voltage level lowered to the set-down voltage (-Vy) during the reset period. Apply a signal.

Subsequently, when a data signal is applied to the address electrode, the sixth switch Q6 is synchronously supplied to thereby supply a scan pulse that falls to the scan voltage source -Vy to the first node n1 to cause an address discharge. .

In this case, the scan IC includes seventh and eighth switches Q7 and Q8 connected in a push-pull form, and output terminals between the switches are connected to the panel capacitor Cp. Each of the seventh and eighth switches supplies a signal or scan pulse on the first node to the panel capacitor.

In addition, the circuit includes a first path blocking switch Q10 for blocking another path on node 1 so that a setdown signal and a scan pulse are applied toward the panel capacitor, and another direction on node 1 so that a setup signal is applied toward the panel capacitor. It comprises a second path blocking switch (Q11) for blocking the path of.

The sustain signal applying unit 2 causing sustain discharge in the discharge cells selected during the address period causes the voltage difference of the discharge voltage or higher to be formed in the scan electrode and the sustain electrode during the sustain period. To this end, the first switch Q1 is turned on to supply the highest sustain voltage Vsus / 2 to the first node n1, and the second switch Q2 is turned on to supply the lowest sustain voltage (-Vsus / 2). Supply.

At this time, the level of the DC voltage source supplied in the circuit is different depending on the level at which the voltage of the node 1 (n1) is set. In FIG. 1, the node 1 is set to ground and the highest sustain voltage is set to Vsus / 2. It is assumed that the lowest sustain voltage is supplied at -Vsus / 2.

Here, the scan signal applying unit 4 is connected to the scan bias voltage source to share the lowest sustain voltage source (-Vsus / 2), so that the fifth switch Q5 is turned on when the address period is started, -Vsus / 2 level. Scan bias voltage is applied.

At this time, one end of the fifth switch Q5 is connected to the lowest sustain voltage source (-Vsus), the other end is connected to the panel capacitor Cp, and a voltage of node 1 is connected to the setup voltage source Vsu during the setup period. As it rises, a voltage equal to [Vsu − (− Vsus / 2)], that is, [Vsu + Vsus / 2] is applied to both ends of the fifth switch.

This is the same as the waveform 2 in FIG. 2A, which may cause the internal pressure of the fifth switch (scan switch) to be exceeded in the setup section.

In addition, during the sustain period, the highest sustain signal is applied in the same path as ⓐ of FIG. 1, and the lowest sustain signal is applied in the same path as ⓑ of FIG. 1, so that both ends of the first path blocking switch are [highest sustain signal − The minimum sustain signal = Vsus] is applied.

This is the same as the waveform 3 of FIG. 2b, which may cause the internal pressure of the first path blocking switch to be exceeded in the sustain section.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a plasma display apparatus capable of preventing the risk of exceeding the breakdown voltage of a scan switch applying a scan bias signal by switching a circuit connection. .

In addition, the present invention provides a plasma display apparatus capable of preventing the risk of exceeding the breakdown voltage of the second path blocking switch by switching the path to which the lowest sustain signal is applied, and reducing the number of switch elements.

According to an aspect of the present invention, a plasma display device includes a scan switch connected between a node 1 on a resonance current path and a scan IC to apply a scan bias signal to the panel capacitor, and a panel directly connected to the scan IC. It is configured to include a setup switch for applying a setup signal to the capacitor, the voltage across the scan switch in the set-up section is reduced compared to the conventional, while the conventional second path blocking switch is removable.

In addition, an energy recovery unit includes an inductor connected to the node 1 to form a resonance current with the panel capacitor, and an energy recovery switch connected to the inductor.

The first switch and the second switch connected to the node 1 are alternately connected to each other to form a sustain signal applying unit configured to apply the highest sustain signal and the lowest sustain signal to the panel capacitor.

In this case, a set down switch for applying a set down signal to the panel capacitor and a scan pulse switch for applying a falling scan pulse from the scan bias signal are respectively connected to the scan IC.

A first path blocking switch is connected on the node 1 to block a path in the other direction so that a setdown signal or a scan pulse is applied toward the panel capacitor.

Thus, in the present invention, since the complementary scan switch is removed and the path of the lowest sustain signal is passed through the node 1 and the scan switch to the panel capacitor, the voltage across the first path blocking switch during the sustain period is higher than that of the conventional method. Is reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of the plasma display device of the present invention, the configuration of the present invention will be described in detail with reference to this.

First, the energy recovery unit 10 is a circuit for minimizing the loss caused by reactive power generated by charging the panel capacitor Cp to the sustain voltage during the sustain period and discharging it again.

Accordingly, the energy recovery unit 10 includes an inductor forming an LC resonance current together with the panel capacitor Cp, a switch connected to the inductor, and a source capacitor storing energy lost during charging / discharging of the panel. It is composed. This resonant current is supplied or recovered through node 1 (n1).

Here, the panel capacitor Cp equivalently represents the capacitance formed between the scan electrode Y and the sustain electrode Z. FIG.

In the sustain signal applying unit 20, a first switch connected between the highest sustain voltage source Vsus / 2 and the first node n1 is turned on to supply the highest sustain signal to the first node n1. .

In addition, a second switch Q2 connected between the first node n1 and the lowest sustain voltage source (-Vsus / 2) is alternately turned on with the first switch to provide the lowest sustain signal to the first node. To supply.

At this time, the level of the external power supplied in the circuit is different depending on the level at which the node 1 voltage is set. In this embodiment, the node 1 is set to the ground level, the highest sustain voltage is set to Vsus / 2, and the lowest is set. The supply of the sustain voltage to -Vsus / 2 is illustrated.

In addition, whether the external power supply used in the present embodiment is not limited to common use or not, the value of the voltage level, etc. can be changed, and each switch may be further connected to a switch connected to this by a push pull. State that

The reset signal applying unit includes a setup signal applying unit 30su for applying the setup signal and a setdown signal applying unit 30sd for applying the setdown signal during the reset period.

First, in the setup signal applying unit 30su, the setup switch Q3 connected between the setup voltage source Vsu and the scan IC is turned on to directly apply a setup signal in the form of a ramp rising to the setup voltage source directly to the panel capacitor Cp. do. A variable resistor VR1 for adjusting the slope of the ramp waveform is connected to the control terminal of the setup switch.

In this way, since the setup signal is directly applied to the panel capacitor without passing through node 1 (n1), the conventional second path blocking switch Q11 for blocking another path on node 1 can be removed in the present invention.

In addition, the setdown signal applying unit 30sd is connected to the setdown switch Q4 connected between the scan IC and the setdown voltage source (-Vy) to conduct a ramp-down setdown signal falling down to the setdown voltage source (-Vy). Supply to panel capacitor. A variable resistor VR2 for adjusting the slope of the ramp waveform is connected to the control terminal of the set-down switch.

The scan signal applying unit includes a scan bias signal applying unit 40sb for applying a scan bias signal and a scan pulse applying unit 40sp for applying a scan pulse during an address period.

First, the scan bias signal applying unit 40sb includes a scan switch Q5 for applying a scan bias signal to the panel capacitor Cp in an address period, and the scan switch is connected to a scan bias voltage source through a node 1. Connected.

In addition, the scan pulse applying unit 40sp includes a scan pulse switch Q6 connected to the scan IC and a scan voltage source (-Vy). As the scan pulse switch is turned on, the scan bias voltage ( A scan pulse that drops from -Vsus / 2) to the scan pulse voltage source (-Vy) is applied to cause an address discharge.

In this case, the scan bias voltage source may be shared with the lowest sustain voltage source (-Vsus / 2) of the sustain driver 20, and the scan pulse voltage source may be shared with the setdown voltage source (-Vy).

In addition, in the conventional scan bias signal applying unit, the complementary scan switch Q9 which is complementary to the scan switch Q5 is connected in parallel with the scan switch, so that the lowest sustain signal is transmitted to the node 1 and the complementary scan switch during the sustain period. Unlike (ⓑ), the scan bias signal applying unit 40sb of the present invention removes the complementary scan switch that is connected in parallel with the scan switch Q5, and thus, the lowest sustain signal during the sustain period. Is supplied to the panel capacitor via node 1 (n1) and scan switch (Q5).

In addition, a seventh switch (high side, Q7) and an eighth switch (low side, Q8) connected between the scan voltage source (-Vy) and the first node n1 in a push-pull form a scan IC. Since the output terminal between each switch is connected to the panel capacitor Cp, the setup signal / node 1 phase signal is applied according to the conduction of the switch constituting the scan IC, and the charging voltage of the panel capacitor is discharged.

In addition, a first path blocking switch Q10 is connected on the first node to block the path in the other direction on the node 1 so that the set down signal or the scan pulse is applied toward the panel capacitor.

In the circuit of the present invention configured as described above, the waveforms during the unit subfields will be described with reference to FIG. 4 as follows.

First, the reset section R is a section for erasing the wall charge state formed by the previous sustain discharge and initializing the state of each cell. The reset section R is a setup section SU to which a rising setup signal is supplied, and a ramp down. down) It is divided into a set down period (SD) to which a set down signal of a waveform is supplied.

The set-up signal is supplied via a set-up switch-scan IC (seventh switch) at the set-up voltage source, and the set-down signal is supplied via a set-down switch-scan IC (eighth switch) at the set-down voltage source.

The address section A is a section for selecting a cell to be discharged, and a scan bias signal is supplied from a scan bias voltage source through a second switch-node 1-scan switch-scan IC (seventh switch) and synchronized with a data pulse. At the moment of being supplied, the address discharge is generated from the scan pulse voltage source via the scan pulse switch-scan IC (the eighth switch).

In addition, the sustain section S is a section in which pulses are alternately applied to the scan electrode and the sustain electrode, and the highest sustain signal is the first switch-node 1-first path-blocking switch-scan IC (eighth) at the highest sustain voltage source. And the lowest sustain signal is supplied via the second switch-node 1-scan switch-scan IC (seventh switch) from the lowest sustain voltage source to generate sustain discharge. .

In particular, the voltage applied to both ends of the scan switch and the first path blocking switch in which the switch breakdown voltage is a problem will be described with reference to FIGS. 5 and 6.

First, during the setup period in which the breakdown voltage of the scan switch is increased, the setup signal is directly applied to the panel capacitor Cp through [Setup Voltage Source-Setup Switch-Scan IC], and the voltage at node 1 is maintained during the setup period. The maximum voltage across the scan switch is [Vsu-Vsus / 2].

This is shown in the graph '2' of FIG. 5, which is a reduced value compared to [Vsu + Vsus / 2] across the scan switch in the conventional setup section shown in the section 2a of FIG.

In addition, since the path of the lowest sustain signal is formed along the scan switch at the first node during the sustain period in which the breakdown voltage of the first path blocking switch is increased, the resonance current and the discharge current flowing to the first path blocking switch are conventionally reduced. Compared to half, the maximum voltage across the first path blocking switch becomes [Vsus / 2].

This is shown in the 3 'graph of FIG. 6, which is a reduced value compared to [Vsus] across the first path blocking switch in the conventional sustain section shown in 3 of FIG.

As described above with reference to the drawings illustrated with respect to the plasma display device according to the present invention, the present invention is not limited by the embodiments and drawings disclosed herein, having a general knowledge in the field to which the present invention belongs Applicability is possible within the scope of the technical idea of the present invention protected by the ruler.

The plasma display device of the present invention configured as described above can remove the second path blocking switch element by switching the circuit connection of the scan switch applying the scan bias signal and the circuit connection of the setup switch applying the setup signal. Of course, it is possible to reduce the voltage across the scan switch during the setup period, it is possible to adopt a switch element with a low breakdown voltage.

In addition, it is possible to reduce the voltage across the first path blocking switch during the sustain period by removing the complementary scan switch and switching the path through which the lowest sustain signal is supplied, thereby reducing the manufacturing cost.

Claims (9)

An energy recovery unit is connected to Node 1 between the first switch that supplies the highest sustain signal and the second switch that supplies the lowest sustain signal during the sustain period. A scan switch for supplying the lowest sustain signal as a scan bias signal during an address period is connected between the node 1 and the scan IC, And a setup switch for supplying a setup signal gradually increasing from the highest sustain signal value to a setup voltage during a reset period is directly connected to the scan IC. In claim 1, The energy recovery unit includes an inductor connected to node 1 to form a resonance current with the panel capacitor, and an energy recovery switch connected to the inductor. In claim 1, The highest sustain signal is a positive voltage less than the setup voltage, And the lowest sustain signal is a negative voltage that is symmetrical to the highest sustain signal. In claim 1, And a set down switch connected to the scan IC for supplying a set down signal that gradually descends during a reset period. In claim 4, And a scan pulse switch for applying a scan pulse to the panel capacitor during the address period is connected with the scan IC and connected in parallel with the set down switch. In claim 5, And a first path blocking switch connected between the node 1 and the scan IC to block a path in a different direction so that the set down signal or the scan pulse is applied toward the panel capacitor. In claim 1, During the sustain period, the first switch and the second switch are alternately switched, And the lowest sustain signal is applied to the panel capacitor via the node 1 and the scan switch. delete delete

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