KR100763535B1 - Method of manufacturing a non-volatile memory device - Google Patents

Abstract

A method for manufacturing a nonvolatile memory device is provided to improve threshold voltage and breakdown voltage characteristics by using a charge trapping pattern composed of silicon nitride and hafnium aluminum oxide. A tunnel insulating layer is formed on a substrate(100) with a channel region(100a). A charge trapping layer is formed on the tunnel insulating layer to trap electrons from the channel region. The charge trapping layer is composed of a silicon nitride layer and a hafnium aluminum oxide layer. A dielectric film is formed on the charge trapping layer. A conductive layer is formed on the dielectric film. A gate structure(150) composed of a control gate electrode, a dielectric pattern(140), a charge trapping pattern(142) and a tunnel insulating pattern is formed on the channel region by patterning selectively the conductive layer, the dielectric film, the charge trapping layer and the tunnel insulating layer.

Description

Method of manufacturing a non-volatile memory device

1 to 5 are schematic cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

6 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device in accordance with another embodiment of the present invention.

7 is a cross-sectional view for describing a method of manufacturing a nonvolatile memory device according to still another embodiment of the present invention.

8 is a cross-sectional view for describing a method of manufacturing a nonvolatile memory device according to still another embodiment of the present invention.

9 is a cross-sectional view for describing a method of manufacturing a nonvolatile memory device according to still another embodiment of the present invention.

10 is a graph showing capacitance of a nonvolatile memory device formed by a conventional method.

11 is a graph illustrating capacitance of a nonvolatile memory device formed in accordance with an embodiment of the present invention.

12 is a graph showing a threshold voltage of a nonvolatile memory device formed by a conventional method.

13 is a graph illustrating a threshold voltage of a nonvolatile memory device formed according to an embodiment of the present invention.

14 is a graph illustrating a leakage current of a nonvolatile memory device formed by a conventional method and a leakage current of a nonvolatile memory device formed according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10 nonvolatile memory device 100 semiconductor substrate

100a: channel region 120: control gate electrode

122: first metal nitride film pattern 124: second metal nitride film pattern

126: metal film pattern 134: spacer

140 dielectric layer pattern 142 charge trapping film pattern

146 silicon nitride film pattern 148 hafnium aluminum oxide film pattern

150: gate structures 152a, 152b: source / drain regions

The present invention relates to a method of manufacturing a nonvolatile memory device. More particularly, the present invention relates to a method of manufacturing a nonvolatile memory device including a charge trapping film.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), have relatively fast data input and output, while volatile memory devices lose data over time, and ROM Although data input and output is relatively slow, such as read only memory, it can be classified as a non-volatile memory device that can store data permanently. In the case of the nonvolatile memory device, there is an increasing demand for an electrically erasable programmable read only memory (EEPROM) or a flash EEPROM memory capable of electrically inputting / outputting data. The flash EEPROM memory device electrically performs programming and erasing of data using F-N tunneling or channel hot electron injection. The flash memory device may be classified into a nonvolatile memory device of a floating gate type and a nonvolatile memory device of a silicon oxide nitride oxide semiconductor (SONOS) or a metal oxide nitride oxide semiconductor (MONOS) type.

The SONOS or MONOS type nonvolatile memory device includes a tunnel insulating film formed on a semiconductor substrate, a charge trapping film for trapping electrons from the channel region, a dielectric film formed on the charge trapping film, and a gate formed on the dielectric film. An electrode may include a spacer formed on side surfaces of the gate electrode.

The SONOS or MONOS type nonvolatile memory device may be used as a single level cell (SLC) or a multi level cell (MLC).

When the nonvolatile memory device is used as a single level cell, a logic state of '0' or '1' may be stored in the charge trapping layer.

When the nonvolatile memory device 10 is used as a multi-level cell, a logic state of '00', '01', '10', or '11' may be stored in the charge trapping layer.

When the nonvolatile memory device is used as a multi-level cell, more stress may be applied to the nonvolatile memory device as compared with the case where the nonvolatile memory device is used as a single level cell. Thus, when the nonvolatile memory device is used as a multi-level cell, an improved breakdown voltage characteristic and an increased threshold voltage window are required.

An object of the present invention to solve the above problems is to provide a method of manufacturing a nonvolatile memory device having an improved breakdown voltage characteristics and an increased threshold voltage window.

According to an aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, including forming a tunnel insulating film on a substrate having a channel region, and forming silicon nitride and hafnium aluminum oxide on the tunnel insulating film. Forming a charge trapping film for trapping electrons from the channel region, forming a dielectric film on the charge trapping film, forming a conductive film on the dielectric film, the conductive film, Patterning a dielectric film, a charge trapping film, and a tunnel insulating film to form a gate structure including a control gate electrode, a dielectric film pattern, a charge trapping film pattern, and a tunnel insulating film pattern on the channel region.

According to an embodiment of the present disclosure, the forming of the charge trapping film may include forming a silicon nitride film on the tunnel insulating film, and forming a hafnium aluminum oxide film on the silicon nitride film. The hafnium aluminum oxide film may be formed using atomic layer deposition.

According to an embodiment of the present disclosure, the forming of the hafnium aluminum oxide layer may include forming a first precursor layer on the silicon nitride layer by providing a first reaction material including hafnium on the substrate; Providing a second reactant material comprising aluminum to form a second precursor film on the first precursor film, and oxidizing the first and second precursor films to form the hafnium aluminum oxide film. can do.

According to an embodiment of the present disclosure, the forming of the hafnium aluminum oxide layer may include forming a precursor film on the substrate by providing a first reactant including hafnium and a second reactant including aluminum on the substrate. And oxidizing the precursor film to form the hafnium aluminum oxide film.

According to an embodiment of the present disclosure, the forming of the hafnium aluminum oxide layer may include forming a first precursor layer on the silicon nitride layer by providing a first reaction material including hafnium on the substrate. Oxidizing a precursor film to form a hafnium oxide film, providing a second reactant including aluminum on the substrate to form a second precursor film on the hafnium oxide film, and oxidizing the second precursor film. It may include the step of forming an aluminum oxide film.

According to an embodiment of the present disclosure, the forming of the charge trapping film may include forming a hafnium aluminum oxide film on the tunnel insulating film and forming a silicon nitride film on the hafnium aluminum oxide film. .

According to an embodiment of the present invention, the forming of the charge trapping film may include forming a first silicon nitride film on the tunnel insulating film, forming a hafnium aluminum oxide film on the first silicon nitride film, And forming a second silicon nitride film on the hafnium aluminum oxide film.

According to an embodiment of the present invention, the forming of the charge trapping film may include forming a first hafnium aluminum oxide film on the tunnel insulating film, and forming a silicon nitride film on the first hafnium aluminum oxide film; The method may include forming a second hafnium aluminum oxide film on the silicon nitride film.

According to one embodiment of the present invention, after the charge trapping film is formed, the substrate may further comprise the step of heat treatment at a temperature of 850 to 1200 ℃. The heat treatment may be performed in any one or a mixed gas atmosphere selected from the group consisting of N ₂ , O ₂ , NH ₃ and N ₂ O.

According to one embodiment of the present invention, after the dielectric film is formed, the substrate may further comprise the step of heat treatment at a temperature of 850 to 1200 ℃. The heat treatment may be performed in any one or a mixed gas atmosphere selected from the group consisting of N ₂ , O ₂ , NH ₃ and N ₂ O.

In example embodiments, the forming of the gate structure may include forming the control gate electrode by patterning the conductive layer, patterning the dielectric layer, the charge trapping layer, and the tunnel insulating layer to form the dielectric layer pattern; And forming a charge trapping film pattern and a tunnel insulating film pattern. The method may further include forming a spacer on side surfaces of the control gate electrode after forming the control gate electrode, wherein the dielectric layer, the charge trapping layer, and the tunnel insulation layer use the spacer as an etching mask. It can be patterned through an etching process.

According to an embodiment of the present invention, after the gate structure is formed, source / drain regions may be formed in surface portions of the substrate adjacent to the gate structure.

According to the embodiments of the present invention, the nonvolatile memory device includes a charge trapping film pattern including silicon nitride and hafnium aluminum oxide. Therefore, the threshold voltage window of the nonvolatile memory device can be increased, and the breakdown voltage characteristic can be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments and may be implemented in other forms. The embodiments introduced herein are provided to make the disclosure more complete and to fully convey the spirit and features of the invention to those skilled in the art. In the drawings, the thickness of each device or film (layer) and regions has been exaggerated for clarity of the invention, and each device may have a variety of additional devices not described herein. When (layer) is mentioned as being located on another film (layer) or substrate, an additional film (layer) may be formed directly on or between the other film (layer) or substrate.

1 to 5 are schematic cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

Referring to FIG. 1, an active region is defined by forming an isolation layer (not shown) on a surface portion of a semiconductor substrate 100 such as a silicon wafer. Specifically, the device isolation layer is formed on the surface portion of the semiconductor substrate 100 through a local oxidation of silicon (LOCOS) process or a shallow trench isolation (STI) process.

The tunnel insulating layer 102, the charge trapping layer 104, the dielectric layer 110, and the conductive layer 112 are sequentially formed on the semiconductor substrate 100.

The tunnel insulating layer 102 may be made of silicon oxide (SiO ₂ ), and may be formed to a thickness of about 20 to about 80 μs through a thermal oxidation process. For example, the tunnel insulating layer 102 may be formed on the semiconductor substrate 100 to a thickness of about 35 Å.

The charge trapping film 104 is formed to trap electrons from the channel region of the semiconductor substrate 100. The charge trapping film 104 may include silicon nitride and hafnium aluminum oxide, and may have a dual structure of the silicon nitride film 106 and the hafnium aluminum oxide film 108. The thickness ratio of the hafnium aluminum oxide layer to the silicon nitride layer may be about 1 to about 3.

The silicon nitride film 106 may be formed to a thickness of about 20 to about 100 Å on the tunnel insulating film 102 by low pressure chemical vapor deposition. For example, the silicon nitride layer 106 may be formed on the tunnel insulating layer 102 to a thickness of about 40 GPa.

The hafnium aluminum oxide film 108 may be formed by atomic layer deposition, and may be formed on the silicon nitride film 106 to a thickness of about 20 to about 300 kPa. For example, the hafnium aluminum oxide film 108 may be formed to a thickness of about 120 GPa. In particular, the hafnium aluminum oxide film 108 may be formed such that the equivalent oxide film thickness is about 10 to 30 kPa, for example, about 17 kPa.

Hereinafter, a method of forming the hafnium aluminum oxide film 108 will be described in detail.

The semiconductor substrate 100 on which the silicon nitride film 106 is formed is positioned in a chamber (not shown) for atomic layer deposition. In this case, the temperature inside the chamber may be maintained at about 150 to 400 ℃ degree, the pressure may be maintained at about 0.1 to 3.0 torr. For example, the temperature inside the chamber may be maintained at about 300 ° C., and the pressure may be maintained at about 1.0 torr.

Subsequently, a first reaction material including a hafnium precursor is provided on the semiconductor substrate 100 to form a first precursor film on the silicon nitride film 106. Specifically, a gaseous hafnium precursor may be used as the first reactant, and the gaseous hafnium precursor may be carried by a carrier gas such as nitrogen or argon. The gaseous hafnium precursor gas may be provided through a liquid delivery system (LDS) or a bubbler system.

The hafnium precursor is TDMAH (tetrakis dimethyl amino hafnium, Hf [N (CH ₃ ) ₂ ] ₄ ), TEMAH (tetrakis ethyl methyl amino hafnium, Hf [N (C ₂ H ₅ ) CH ₃ ] ₄ ), TDEAH (tetrakis) diethyl amino hafnium, Hf [N (C ₂ H ₅ ) ₂ ] ₄ ), Hf [OC (CH ₃ ) ₂ CH ₂ OCH ₃ ] ₄ , Hf [OC (CH ₃ ) ₃ ] ₄ , and the like. It can also be used in the form of a mixture.

The first reactant may be provided on the semiconductor substrate 100 for about 0.5 to 3 seconds. For example, the first reactant material may be provided on the semiconductor substrate 100 for about 2 seconds.

A portion of the first reactant material provided on the semiconductor substrate 100 as described above is chemisorbed on the silicon nitride film 106 to form a first precursor film, and the rest is physically adsorbed on the first precursor film or the chamber. Drift within.

After forming the first precursor film, the chamber is evacuated while providing a purge gas into the chamber. Nitrogen or argon may be used as the purge gas, and the purge gas may be supplied for about 0.5 to 5 seconds. For example, the purge gas may be supplied for about 2 seconds.

The first reactant physically adsorbed on the first precursor film and the first reactant drifting in the chamber are evacuated from the chamber together with the purge gas supplied into the chamber.

After purging the chamber, a second reaction material including an aluminum precursor is provided on the semiconductor substrate 100 to form a second precursor film on the first precursor film. Specifically, gaseous aluminum precursor is introduced into the upper portion of the semiconductor substrate 100 using nitrogen or argon as a carrier gas. Examples of the aluminum precursors include TMA (trimethyl aluminum, Al (CH ₃ ) ₃ ), TEA (triethyl aluminum, Al (C ₂ H ₅ ) ₃ ), and mixtures thereof. The second reactant may be introduced onto the semiconductor substrate 100 for about 0.5 to 3 seconds. For example, the second reactant may be introduced onto the semiconductor substrate 100 for about 2 seconds.

A portion of the second reactant material provided on the semiconductor substrate 100 as described above is chemisorbed on the first precursor film to form a second precursor film, and the rest is physically adsorbed on the second precursor film or in the chamber. Drift at.

After forming the second precursor film, the chamber is evacuated while providing a purge gas into the chamber. Nitrogen or argon may be used as the purge gas, and the purge gas may be supplied for about 0.5 to 5 seconds. For example, the purge gas may be supplied for about 2 seconds.

The second reactant material physically adsorbed on the second precursor film and the second reactant material drifting in the chamber are evacuated from the chamber together with the purge gas supplied into the chamber.

After purging the chamber, the hafnium aluminum oxide film 108 is formed on the silicon nitride film 106 by oxidizing the first and second precursor films by supplying an oxidant onto the semiconductor substrate 100.

Examples of the oxidant include O ₃ , O ₂ , H ₂ O, plasma O ₂ , and the like. These may be used alone or a mixture thereof may be used in some cases. For example, O ₃ may be supplied over the first and second precursor films for about 1 to 5 seconds. In particular, the oxidant may be supplied over the first and second precursor films for about 3 seconds.

After the hafnium aluminum oxide film 108 is formed, a purge gas is supplied into the chamber to remove reaction by-products and residual oxidants generated by the reaction between the first and second precursor films and the oxidant from the chamber. The purge gas may be supplied for about 1 second to 5 seconds. For example, the purge gas may be supplied for about 3 seconds.

As described above, the steps for forming the hafnium aluminum oxide film 108 may be repeatedly performed until the charge trapping film 104 having the desired thickness is formed.

According to another embodiment of the present invention, the first reactant and the second reactant may be supplied simultaneously. Specifically, the first reactant and the second reactant are simultaneously provided on the semiconductor substrate 100 to form a precursor film, and then an oxidant is supplied onto the precursor film to hafnium aluminum oxide film on the silicon nitride film 106. 108 can be formed.

According to another embodiment of the present invention, the hafnium oxide film and the aluminum oxide film may be repeatedly formed on the silicon nitride film 106. Specifically, the hafnium oxide film may be formed by supplying the first reactant material onto the silicon nitride film 106 to form a first precursor film and oxidizing the first precursor film. The aluminum oxide layer may be formed by providing the second reaction material on the hafnium oxide layer to form a second precursor layer and oxidizing the second precursor layer.

After the charge trapping film 104 is formed as described above, a heat treatment process is performed to crystallize and densify the charge trapping film 104 and to remove impurities in the charge trapping film 104. . The heat treatment process may be performed at a temperature of about 850 to 1200 ℃ degree, may be performed in a gas atmosphere such as N ₂ , O ₂ , NH ₃ , N ₂ O or a mixed gas atmosphere thereof. For example, the heat treatment process may be performed at a temperature of about 1080 ° C. for about 120 seconds, and may be performed by using a furnace.

After performing the heat treatment process, the dielectric film 110 is formed on the charge trapping film 104. The dielectric film 110 functions as a blocking film between the charge trapping film 104 and the conductive film 112 and provides electrical insulation between the charge trapping film 104 and the conductive film 112. to provide. The dielectric layer 110 may be made of aluminum oxide (Al ₂ O ₃ ), and may be formed by chemical vapor deposition or atomic layer deposition. For example, the dielectric layer 110 may be formed on the charge trapping layer 104 to a thickness of about 100 to 400 Å. In particular, the dielectric layer 110 may be formed on the charge trapping layer 104 to a thickness of about 200 Å.

According to another embodiment of the present invention, an additional heat treatment may be performed after the dielectric film 110 is formed. For example, the additional heat treatment process may be performed at a temperature of about 850 to 1200 ℃, may be performed in a gas atmosphere such as N ₂ , O ₂ , NH ₃ , N ₂ O or a mixed gas atmosphere thereof. . For example, the additional heat treatment process may be performed at a temperature of about 1080 ° C. for about 120 seconds, and may be performed using a furnace.

According to another embodiment of the present invention, when the heat treatment is performed after the dielectric film 110 is formed, the heat treatment performed after the charge trapping film 104 is formed may be omitted.

The conductive layer 112 may include a first metal nitride layer 114, a second metal nitride layer 116, and a metal layer 118.

The first metal nitride film 114 functions as a metal barrier film and may be made of tantalum nitride, titanium nitride, hafnium nitride, or the like. For example, the first metal nitride layer 114 may be formed of tantalum nitride, and may be formed to have a thickness of about 200 μm on the dielectric layer 110.

The second metal nitride film 116 functions as an adhesive film and may be made of tungsten nitride. For example, the second metal nitride layer 116 may be formed on the first metal nitride layer 114 to have a thickness of about 50 GPa.

The metal film 118 may be formed of tungsten, and may be formed on the second metal nitride film 116 to a thickness of about 300 GPa. Alternatively, the metal film 118 may be made of metal silicide. As the metal silicide, tungsten silicide, tantalum silicide, cobalt silicide, titanium silicide, or the like may be used.

Referring to FIG. 2, a photoresist pattern is formed on the conductive film 112. The photoresist pattern may be formed using a photolithography process that is well known in the art.

The conductive layer 112 is patterned to form a control gate electrode 120 including a first metal nitride layer pattern 122, a second metal nitride layer pattern 124, and a metal layer pattern 126 on the dielectric layer 110. Form. For example, the control gate electrode 120 may be formed by performing an anisotropic etching process using the photoresist pattern as an etching mask.

The first metal nitride layer pattern may function as a substantially gate electrode, and the metal layer pattern may function as a substantial word line.

The photoresist pattern may be removed through an ashing and stripping process after forming the control gate electrode 120.

Referring to FIG. 3, a spacer layer 128 is formed on the control gate electrode 120 and the dielectric layer 110. The spacer layer 128 may include a silicon oxide layer 130 and a silicon nitride layer 132. In detail, after the silicon oxide layer 130 is formed on the control gate electrode 120 and the dielectric layer 110, the silicon nitride layer 132 is formed on the silicon oxide layer 130. The silicon oxide layer 130 and the silicon nitride layer 132 may be formed using a chemical vapor deposition process, respectively. According to another embodiment of the present invention, the silicon nitride film 130 may be formed in-situ after the silicon oxide film 132 is formed.

Referring to FIG. 4, the spacer layer 128 is anisotropically etched to form a double spacer 134 on side surfaces of the control gate electrode 120. The double spacer 134 includes a silicon oxide spacer 136 and a silicon nitride spacer 138.

Referring to FIG. 5, the dielectric layer 110, the charge trapping layer 104, and the tunnel insulation layer 102 may be formed by performing anisotropic etching using the control gate electrode 120 and the double spacer 134 as an etching mask. ), A dielectric film pattern 140, a charge trapping film pattern 142, and a tunnel insulation film pattern 144 are formed. The charge trapping film pattern 142 includes a silicon nitride film 146 pattern and a hafnium aluminum oxide film pattern 148.

As a result, the gate electrode 120, the double spacer 134, the dielectric film pattern 140, the charge trapping film pattern 142, and the tunnel insulating film pattern 144 on the channel region 100a of the semiconductor substrate 100. The gate structure 150 is formed to include.

Subsequently, a reoxidation process is performed to heal etch damage of the semiconductor substrate 100 and the gate structure 150 generated during the formation of the gate structure 150.

Source / drain regions 152a and 152b are formed in surface portions of the semiconductor substrate 100 adjacent to the gate structure 150. The source / drain regions 152a and 152b may be formed by an ion implantation process and a heat treatment process using the gate structure 150 as an ion implantation mask.

6 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device in accordance with another embodiment of the present invention.

Referring to FIG. 6, a tunnel insulating film 202, a charge trapping film 204, a dielectric film 210, and a conductive film 212 are sequentially formed on the semiconductor substrate 200.

The charge trapping layer 204 may include a hafnium aluminum oxide layer 206 and a silicon nitride layer 208. Specifically, after the tunnel insulating film 202 is formed on the semiconductor substrate 200, the hafnium aluminum oxide film 206 is formed on the tunnel insulating film 202 to a thickness of about 20 to about 300 kPa. Subsequently, a silicon nitride film 208 is formed on the hafnium aluminum oxide film 206 to a thickness of about 20 to about 100 GPa.

The hafnium aluminum oxide layer 206 may be formed using atomic layer deposition, and the silicon nitride layer 208 may be formed using low pressure chemical vapor deposition. A detailed description of the method of forming the hafnium aluminum oxide film 206 will be omitted since it is similar to that described with reference to FIG. 1.

The conductive layer 212 may include a first metal nitride layer 214, a second metal nitride layer 216, and a metal layer 218.

After the conductive film 212 is formed as described above, a control gate electrode and a spacer are formed, and the dielectric film, the charge trapping film, and the tunnel insulating film are patterned to complete a gate structure. Subsequently, source / drain regions are formed in surface portions of the semiconductor substrate 200 adjacent to the gate structure.

A detailed description of the method of forming the gate structure and the source / drain regions is similar to that described above with reference to FIGS.

7 is a cross-sectional view for describing a method of manufacturing a nonvolatile memory device according to still another embodiment of the present invention.

Referring to FIG. 7, the tunnel insulating film 302, the charge trapping film 304, the dielectric film 312 and the conductive film 314 are sequentially formed on the semiconductor substrate 300.

The charge trapping film 304 may include a first hafnium aluminum oxide film 306, a silicon nitride film 308, and a second hafnium aluminum oxide film 310. Specifically, after the tunnel insulating film 302 is formed on the semiconductor substrate 300, the first hafnium aluminum oxide film 306 is formed on the tunnel insulating film 302 to a thickness of about 10 to 150 kPa. Subsequently, a silicon nitride film 308 is formed on the first hafnium aluminum oxide film 306 to a thickness of about 20 to about 100 microseconds, and a second hafnium aluminum oxide film 310 is about 10 to about 100 on the silicon nitride film 308. It is formed to a thickness of about 150Å.

The first and second hafnium aluminum oxide layers 306 and 310 may be formed using atomic layer deposition, and the silicon nitride layer 308 may be formed using low pressure chemical vapor deposition. A detailed description of the method of forming the first and second hafnium aluminum oxide layers 306 and 310 is similar to that described above with reference to FIG. 1 and will be omitted.

The conductive layer 314 may include a first metal nitride layer 316, a second metal nitride layer 318, and a metal layer 320.

After the conductive film 314 is formed as described above, a control gate electrode and a spacer are formed, and the dielectric film, the charge trapping film, and the tunnel insulating film are patterned to complete a gate structure. Subsequently, source / drain regions are formed in surface portions of the semiconductor substrate 300 adjacent to the gate structure.

A detailed description of the method of forming the gate structure and the source / drain regions is similar to that described above with reference to FIGS. 2 to 5 and thus will be omitted.

8 is a cross-sectional view for describing a method of manufacturing a nonvolatile memory device according to still another embodiment of the present invention.

Referring to FIG. 8, a tunnel insulating film 402, a charge trapping film 404, a dielectric film 412, and a conductive film 414 are sequentially formed on the semiconductor substrate 400.

The charge trapping layer 404 may include a first silicon nitride layer 406, a hafnium aluminum oxide layer 408, and a second silicon nitride layer 410. In detail, after the tunnel insulating film 402 is formed on the semiconductor substrate 400, the first silicon nitride film 406 is formed on the tunnel insulating film 402 to a thickness of about 10 to about 50 kPa. Subsequently, a hafnium aluminum oxide film 408 is formed on the first silicon nitride film 406 to a thickness of about 20 to about 300 microseconds, and a second silicon nitride film 410 is about 10 to about 300 on the hafnium aluminum oxide film 408. Form 50mm thick.

The hafnium aluminum oxide layer 408 may be formed using atomic layer deposition, and the first and second silicon nitride layers 406 and 410 may be formed using low pressure chemical vapor deposition. A detailed description of the method of forming the hafnium aluminum oxide film 408 is similar to that described above with reference to FIG. 1 and will be omitted.

The conductive layer 414 may include a first metal nitride layer 416, a second metal nitride layer 418, and a metal layer 420.

After forming the conductive film 414 as described above, a control gate electrode and a spacer are formed, and the dielectric film, the charge trapping film, and the tunnel insulating film are patterned to complete a gate structure. Subsequently, source / drain regions are formed in surface portions of the semiconductor substrate 400 adjacent to the gate structure.

A detailed description of the method of forming the gate structure and the source / drain regions is similar to that described above with reference to FIGS. 2 to 5 and thus will be omitted.

9 is a cross-sectional view for describing a method of manufacturing a nonvolatile memory device according to still another embodiment of the present invention.

Referring to FIG. 9, a tunnel insulating film 502, a charge trapping film 504, a dielectric film 510, and a conductive film 512 are sequentially formed on a semiconductor substrate 500.

The charge trapping layer 504 may have a laminate structure in which silicon nitride layers 506 and hafnium aluminum oxide layers 508 are alternately stacked. Specifically, after the tunnel insulating film 502 is formed on the semiconductor substrate 500, the silicon nitride films 506 and the aluminum oxide films 508 are repeatedly formed on the tunnel insulating film 502. Each of the silicon nitride layers 506 may have a thickness of about 10 to about 20 GPa, and each of the hafnium aluminum oxide layers 508 may have a thickness of about 10 to about 60 GPa.

The hafnium aluminum oxide layers 508 may be formed using atomic layer deposition, and the silicon nitride layers 506 may be formed using low pressure chemical vapor deposition. A detailed description of the method of forming the hafnium aluminum oxide films 508 is similar to that described above with reference to FIG. 1 and will be omitted.

The conductive layer 512 may include a first metal nitride layer 514, a second metal nitride layer 516, and a metal layer 518.

After the conductive layer 512 is formed as described above, a control gate electrode and a spacer are formed, and the dielectric layer, the charge trapping layer, and the tunnel insulation layer are patterned to complete a gate structure. Subsequently, source / drain regions are formed in surface portions of the semiconductor substrate 500 adjacent to the gate structure.

A detailed description of the method of forming the gate structure and the source / drain regions is similar to that described above with reference to FIGS. 2 to 5 and thus will be omitted.

Referring back to FIG. 5, the nonvolatile memory device 10 manufactured according to an embodiment of the present invention may be used as a single level cell (SLC) or a multi level cell (MLC). In addition, data programming and erasing may be performed electrically using FN tunneling or channel hot electron injection.

When the nonvolatile memory device 10 is used as a single level cell, one bit of information may be stored in the charge trapping film pattern 142. For example, a logic state of '0' or '1' may be stored in the charge trapping film pattern 142.

Specifically, when a programming voltage of about 5 to 18V is applied to the control gate electrode 120, electrons from the channel region 100a of the semiconductor substrate 100 are tunneled by the FN tunneling pattern 142 by FN tunneling. Traps at trap sites. Accordingly, a logic state of '1' is stored in the charge trapping film pattern 142. That is, the threshold voltage in the channel region 100a is changed according to the logic state stored in the charge trapping film pattern 142, and the logic state is in the control gate electrode 120 and the drain region 152b. It may be determined by detecting different currents in the channel region 100a by applying different read voltages, respectively.

When the nonvolatile memory device 10 is used as a multi-level cell, a logic state of '00', '01', '10', or '11' may be stored in the charge trapping film pattern 142. .

Specifically, the nonvolatile memory device 10 may have different threshold voltages according to the number of electrons trapped in the charge trapping film pattern 142, and the nonvolatile memory device 10 according to the threshold voltages. ) May store logic states of '00', '01', '10' or '11'.

In particular, when the nonvolatile memory device 10 is used as a multi-level cell, the threshold voltage window is preferably about 6V or more. In order to secure a wide range of threshold voltage windows as described above, improved high temperature stress characteristics are required.

Meanwhile, electrons may be trapped in the charge trapping film pattern 142 by channel hot electron injection. Specifically, when programming voltages are applied to the control gate electrode 120 and the drain region 152b and the source region 152a is grounded, electrons are transferred from the source region 152a to the drain region 152b. To move through the channel region 100a. In this case, some of the electrons may obtain sufficient energy to overcome the potential barrier of the tunnel insulation pattern 144 and may be trapped at the trap sites of the charge trapping layer pattern 142. . As a result, the threshold voltage of the nonvolatile memory device 10 is increased, so that one bit of information may be stored in the nonvolatile memory device 10.

High Temperature Stress Characteristics of Nonvolatile Memory Devices

FIG. 10 is a graph illustrating capacitance of a nonvolatile memory device formed by a conventional method, and FIG. 11 is a graph illustrating capacitance of a nonvolatile memory device formed according to an embodiment of the present invention.

First, a first nonvolatile memory device was manufactured on a semiconductor substrate according to a conventional method. Specifically, the first nonvolatile memory device has a thickness of about 35 GPa, a first tunnel insulating film made of silicon oxide, a thickness of about 70 GPa, a first charge trapping film of silicon nitride, and a thickness of about 200 GPa. And a first dielectric layer and a first control gate electrode made of aluminum oxide. The first control gate electrode includes a first tantalum nitride film having a thickness of about 200 GPa, a first tungsten nitride film having a thickness of about 50 GPa, and a first tungsten film having a thickness of about 300 GPa.

In addition, a second nonvolatile memory device is fabricated on a semiconductor substrate according to an embodiment of the present invention. Specifically, the second nonvolatile memory device may have a thickness of about 35 GPa, a second tunnel insulating film made of silicon oxide, a second charge trapping film, a second dielectric film made of aluminum oxide, and a thickness of about 200 GPa. 2 control gate electrodes. The second control gate electrode includes a second tantalum nitride film having a thickness of about 200 GPa, a second tungsten nitride film having a thickness of about 50 GPa, and a second tungsten film having a thickness of about 300 GPa. In particular, the second charge trapping film includes a silicon nitride film and a hafnium aluminum oxide film formed on the second tunnel insulating film. Specifically, after the second tunnel insulating film is formed, the silicon nitride film having a thickness of about 40 GPa is formed on the second tunnel insulating film through low pressure chemical vapor deposition. Subsequently, the hafnium aluminum oxide film was formed on the silicon nitride film through atomic layer deposition so that an equivalent oxide film thickness was about 17 kPa. Specifically, the hafnium aluminum oxide film was formed on the silicon nitride film to a thickness of about 120 GPa. After forming the second charge trapping film, heat treatment was performed at a temperature of about 1080 ° C. for about 120 seconds.

Subsequently, the high temperature stress characteristic test was performed such that the threshold voltage windows of the first and second nonvolatile memory devices were about 6.1V.

1) After the formation of the first nonvolatile memory device, the capacitance was measured, and the result (1; initial value) is shown in FIG. 10.

2) Capacitance was measured after the programming operation of the first nonvolatile memory device, and the result (2) is shown in FIG. 10.

3) After performing the erase operation of the first nonvolatile memory device, the capacitance was measured, and the result 3 is shown in FIG. 10.

4) The programming and erasing operations of the first nonvolatile memory device were repeatedly performed 1200 times. Here, a programming voltage of about + 16.0V is applied to the first nonvolatile memory device and an erase voltage of about -18.7V is applied to the first nonvolatile memory device during the operations. In addition, the programming voltage was applied for 100 kV while the erase voltage was applied for 10 kV while performing the operations. After performing the above operations, the capacitance was measured, and the result (4) is shown in FIG.

5) After performing the operations, the first nonvolatile memory device is baked at a temperature of about 200 ° C. for about 2 hours. After performing the bake process, the capacitance of the first nonvolatile memory device was measured, and the result 5 is shown in FIG. 10.

6) Capacitance was measured after forming the second nonvolatile memory device, and the result (6; initial value) is shown in FIG. 11.

7) Capacitance was measured after the programming operation of the second nonvolatile memory device, and the result 7 is shown in FIG. 11.

8) Capacitance was measured after performing the erase operation of the second nonvolatile memory device, and the result 8 is shown in FIG. 11.

9) The programming and erasing operations of the second nonvolatile memory device are repeatedly performed 1200 times. Here, a programming voltage of about + 15.7V is applied to the second nonvolatile memory device and an erase voltage of about -17.2V is applied to the second nonvolatile memory device during the operations. In addition, the programming voltage was applied for 100 kV while the erase voltage was applied for 10 kV while performing the operations. After performing the above operations, the capacitance was measured, and the result 9 is shown in FIG.

10) After performing the operations, the second nonvolatile memory device is baked at a temperature of about 200 ° C. for about 2 hours. After performing the bake process, the capacitance of the second nonvolatile memory device was measured, and the result 10 is illustrated in FIG. 11.

10 and 11, the second nonvolatile memory device has a similar high temperature stress characteristic as compared with the first nonvolatile memory device. That is, after the high temperature thermal stress is applied to both of the first and second nonvolatile memory devices, a threshold voltage decrease of about 0.5V occurs. However, through the evaluation of the high temperature stress characteristic as described above, it is confirmed that the target threshold window can be secured when the programming voltage and the erase voltage applied to the second nonvolatile memory device are adjusted.

Threshold Voltage Characteristics of Nonvolatile Memory Devices

12 is a graph illustrating threshold voltages of a nonvolatile memory device formed by a conventional method, and FIG. 13 is a graph illustrating threshold voltages of a nonvolatile memory device formed according to an embodiment of the present invention.

First, a third nonvolatile memory device is manufactured by a method substantially the same as a method of manufacturing the first nonvolatile memory device, and a fourth nonvolatile memory device is substantially the same as a method of manufacturing the second nonvolatile memory device. Was prepared.

11) Capacitance was measured after fabricating the third nonvolatile memory device, and the result (11; initial value) is shown in FIG. 12.

12) After performing the programming operation of the third nonvolatile memory device, the capacitance was measured, and the result 12 is shown in FIG. 12. In this programming operation, a programming voltage of + 17.0V was applied for 100 kV.

13) After performing the erase operation of the third nonvolatile memory device, the capacitance was measured, and the result 13 is shown in FIG. 12. In the erase operation, an erase voltage of -19.0 V was applied for 10 kV.

14) Capacitance was measured after fabricating the fourth nonvolatile memory device, and the result 14 (initial value) is shown in FIG. 13.

15) Capacitance was measured after the programming operation of the fourth nonvolatile memory device, and the result 15 is shown in FIG. 13. In this programming operation, a programming voltage of + 17.0V was applied for 100 kV.

16) The capacitance was measured after performing the erase operation of the fourth nonvolatile memory device, and the result 16 is shown in FIG. In the erase operation, an erase voltage of -19.0 V was applied for 10 kV.

12 and 13, the threshold voltage window of the third nonvolatile memory device is measured about 7.3V, and the threshold voltage window of the fourth nonvolatile memory device is measured about 8.5V. That is, when the same programming voltage and the erase voltage are applied to the third and fourth nonvolatile memory devices, it is confirmed that the fourth nonvolatile memory device has an improved threshold voltage window.

Breakdown Voltage Characteristics of Nonvolatile Memory Devices

14 is a graph illustrating a leakage current of a nonvolatile memory device formed by a conventional method and a leakage current of a nonvolatile memory device formed according to an embodiment of the present invention.

The leakage currents of the third and fourth nonvolatile memory devices were measured, and the results are shown in FIG. 14.

Referring to FIG. 14, an insulation breakdown occurs at + 18.6MV / cm and -19.0MV / cm in the third nonvolatile memory device, and + 21.9MV / cm in the fourth nonvolatile memory device. And dielectric breakdown occurred at -21.6 MV / cm. That is, compared to the third nonvolatile memory device, the fourth nonvolatile memory device has improved insulation breakdown voltage characteristics of about 3.3 MV / cm in the positive voltage region and about 2.6 MV / cm in the negative voltage region. It was confirmed that the degree of dielectric breakdown voltage characteristics was improved.

According to the embodiments of the present invention, the nonvolatile memory device includes a charge trapping film pattern including silicon nitride and hafnium aluminum oxide. Therefore, the threshold voltage window of the nonvolatile memory device can be increased, and the breakdown voltage characteristic can be improved.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (17)

Forming a tunnel insulating film on a substrate having a channel region; Forming a charge trapping film comprising silicon nitride and hafnium aluminum oxide on the tunnel insulating film for trapping electrons from the channel region; Forming a dielectric film on the charge trapping film; Forming a conductive film on the dielectric film; And Patterning the conductive film, the dielectric film, the charge trapping film, and the tunnel insulating film to form a gate structure including a control gate electrode, a dielectric film pattern, a charge trapping film pattern, and a tunnel insulating film pattern on the channel region. Method of manufacturing volatile memory device. The method of claim 1, wherein the forming of the charge trapping film comprises: Forming a silicon nitride film on the tunnel insulating film; And And forming a hafnium aluminum oxide film on the silicon nitride film. The method of claim 2, wherein the hafnium aluminum oxide film is formed using atomic layer deposition. The method of claim 2, wherein the forming of the hafnium aluminum oxide film, Providing a first reaction material comprising hafnium on the substrate to form a first precursor film on the silicon nitride film; Providing a second reactant material comprising aluminum on the substrate to form a second precursor film on the first precursor film; And And oxidizing the first and second precursor films to form the hafnium aluminum oxide film. The method of claim 2, wherein the forming of the hafnium aluminum oxide film, Providing a first reactant comprising hafnium and a second reactant comprising aluminum on the substrate to form a precursor film on the substrate; And And oxidizing the precursor film to form the hafnium aluminum oxide film. The method of claim 2, wherein the forming of the hafnium aluminum oxide film, Providing a first reaction material comprising hafnium on the substrate to form a first precursor film on the silicon nitride film; Oxidizing the first precursor film to form a hafnium oxide film; Providing a second reactive material comprising aluminum on the substrate to form a second precursor film on the hafnium oxide film; And And oxidizing the second precursor film to form an aluminum oxide film. The method of claim 1, wherein the forming of the charge trapping film comprises: Forming a hafnium aluminum oxide film on the tunnel insulating film; And And forming a silicon nitride film on the hafnium aluminum oxide film. The method of claim 1, wherein the forming of the charge trapping film comprises: Forming a first silicon nitride film on the tunnel insulating film; Forming a hafnium aluminum oxide film on the first silicon nitride film; And And forming a second silicon nitride film on the hafnium aluminum oxide film. The method of claim 1, wherein the forming of the charge trapping film comprises: Forming a first hafnium aluminum oxide film on the tunnel insulating film; Forming a silicon nitride film on the first hafnium aluminum oxide film; And And forming a second hafnium aluminum oxide film on the silicon nitride film. The method of claim 1, further comprising heat treating the substrate at a temperature of 850 to 1200 ° C. after forming the charge trapping film. The method of claim 10, wherein the heat treatment is performed in any one selected from the group consisting of N ₂ , O ₂ , NH _3, and N ₂ O, or a mixed gas atmosphere thereof. The method of claim 1, further comprising heat treating the substrate at a temperature of 850 to 1200 ° C. after forming the dielectric layer. The method of claim 12, wherein the heat treatment is performed in any one selected from the group consisting of N ₂ , O ₂ , NH _3, and N ₂ O, or a mixed gas atmosphere thereof. The method of claim 1, wherein the forming of the gate structure comprises: Patterning the conductive layer to form the control gate electrode; And Patterning the dielectric film, the charge trapping film, and the tunnel insulation film to form the dielectric film pattern, the charge trapping film pattern, and the tunnel insulation film pattern. The method of claim 14, further comprising forming a spacer on side surfaces of the control gate electrode, wherein the dielectric layer, the charge trapping layer, and the tunnel insulation layer are patterned through an etching process using the spacer as an etching mask. A method of manufacturing a nonvolatile memory device. The method of claim 1, further comprising forming source / drain regions in surface portions of the substrate adjacent to the gate structure after forming the gate structure. The nonvolatile memory as claimed in claim 1, wherein the charge trapping film comprises at least one silicon nitride film and at least one hafnium aluminum oxide film, wherein a thickness ratio of the hafnium aluminum oxide film to the silicon nitride film is 1 to 3. Method of manufacturing the device.

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