KR100814374B1 - Method of manufacturing a non-volatile memory device - Google Patents

Abstract

A method for fabricating an NVM(non-volatile memory) device is provided to increase a threshold voltage window of an NVM device by sufficiently avoiding formation of an undesired layer between a charge trapping layer and a blocking layer by a heat treatment. A tunnel insulation layer(102) is formed on a substrate(100) having a channel region. A charge trapping layer for trapping electrons from the channel region is formed on the tunnel insulation layer, including silicon nitride. A heat treatment is performed on the charge trapping layer at a temperature of 1000-1250 ‹C to densify the charge trapping layer. A blocking layer(108) is formed on the heat-treated charge trapping layer(106). A conductive layer is formed on the blocking layer. The conductive layer, the blocking layer, the charge trapping layer and the tunnel insulation layer are patterned to form a gate structure on the channel region. The blocking layer can include an oxide. The blocking layer can include a metal oxide having a higher dielectric constant than that of a silicon nitride.

Description

Method of manufacturing a non-volatile memory device

1 to 7 are schematic cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

8 is a graph illustrating a threshold voltage of a nonvolatile memory device formed by a conventional method and a threshold voltage of a nonvolatile memory device formed according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10 nonvolatile memory device 100 semiconductor substrate

102 tunnel insulating film 104 charge trapping film

106 heat treated charge trapping film 108 blocking film

110 conductive film 120 gate electrode structure

134: double spacer 150: gate structure

152a, 152b: source drain region

The present invention relates to a method of manufacturing a nonvolatile memory device. More particularly, the present invention relates to a method of manufacturing a nonvolatile memory device including a charge trapping film.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), have relatively fast data input and output, while volatile memory devices lose data over time, and ROM Although data input and output is relatively slow, such as read only memory, it can be classified as a non-volatile memory device that can store data permanently. In the case of the nonvolatile memory device, there is an increasing demand for an electrically erasable programmable read only memory (EEPROM) or a flash EEPROM memory capable of electrically inputting / outputting data. The flash EEPROM memory device electrically performs programming and erasing of data using F-N tunneling or channel hot electron injection. The flash memory device may be classified into a nonvolatile memory device of a floating gate type and a nonvolatile memory device of a silicon oxide nitride oxide semiconductor (SONOS) or a metal oxide nitride oxide semiconductor (MONOS) type.

The SONOS or MONOS type nonvolatile memory device includes a tunnel insulating film formed on a semiconductor substrate, a charge trapping film for trapping electrons moving through the channel region, a blocking film formed on the charge trapping film, and the blocking. It may include a gate electrode formed on the film, a spacer formed on the side surfaces of the gate electrode.

The SONOS or MONOS type nonvolatile memory device may be used as a single level cell (SLC) or a multi level cell (MLC).

When the nonvolatile memory device is used as a single level cell, a logic state of '0' or '1' may be stored in the charge trapping layer.

When the nonvolatile memory device 10 is used as a multi-level cell, a logic state of '00', '01', '10', or '11' may be stored in the charge trapping layer.

When the nonvolatile memory device is used as a multi-level cell, more thermal stress or electrical stress may be applied to the nonvolatile memory device as compared with the case where the nonvolatile memory device is used as a single level cell. Thus, when the nonvolatile memory device is used as a multi-level cell, a threshold voltage window of about 6.0V or more is required.

A metal oxide film having a higher dielectric constant than silicon nitride may be used as the blocking film to increase the threshold voltage window of the nonvolatile memory device. For example, an aluminum oxide film may be used as the blocking film.

However, during the formation of the aluminum oxide film, an unwanted film may be formed between the silicon nitride film used as the charge trapping film and the aluminum oxide film. For example, a silicon oxynitride layer may be formed between the silicon nitride layer and the aluminum oxide layer, and the silicon oxynitride layer may reduce the threshold voltage window of the nonvolatile memory device. That is, the electric field applied to the tunnel insulating layer during the programming or erasing operation may be reduced by the silicon oxynitride layer, and thus the threshold voltage window may be reduced.

An object of the present invention for solving the above problems is to provide a method of manufacturing a nonvolatile memory device that can prevent the threshold voltage window is reduced.

According to an aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, the method including forming a tunnel insulating film on a substrate having a channel region, and including silicon nitride on the tunnel insulating layer, wherein the channel region is formed. Forming a charge trapping film for trapping electrons therefrom, heat treating the charge trapping film at a temperature of 1000 to 1250 ° C. to densify the charge trapping film, and on the heat treated charge trapping film Forming a blocking film, forming a conductive film on the blocking film, and patterning the conductive film, the blocking film, the charge trapping film, and the tunnel insulating film to form a gate structure on the channel region. Can be.

According to an embodiment of the present invention, the blocking film may include an oxide. In particular, the blocking film may include a metal oxide having a higher dielectric constant than silicon oxide or silicon nitride. The metal oxide is hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and the like. In addition, the metal oxide may further include silicon.

According to an embodiment of the present invention, the heat treatment may be performed in a gas atmosphere containing nitrogen. In addition, the heat treatment may be performed in an inert gas atmosphere.

According to an embodiment of the present invention, the heat treatment may be performed in a gas atmosphere having an oxygen partial pressure of 1 × 10 ⁻⁶ to 1 × 10 ⁻⁴ torr. In addition, the heat treatment may be performed in a gas atmosphere having an oxygen partial pressure of 1 × 10 ⁻⁶ torr or less.

According to an embodiment of the present invention, the forming of the gate structure may include forming the gate electrode structure by patterning the conductive layer, and patterning the blocking layer, the charge trapping layer, and the tunnel insulating layer to form the blocking layer. Forming a pattern, a charge trapping film pattern, and a tunnel insulating film pattern. Spacers may be formed on side surfaces of the gate electrode structure, and the blocking layer, the charge trapping layer, and the tunnel insulating layer may be patterned through an etching process using the spacer as an etching mask.

According to an embodiment of the present invention, source / drain regions may be formed in surface portions of the substrate adjacent to the gate structure after the gate structure is formed.

According to another aspect of the present invention, there is provided a method of fabricating a nonvolatile memory device, the method including forming a tunnel insulating film on a substrate having a channel region, and including silicon nitride on the tunnel insulating film. Forming a charge trapping film for trapping electrons therefrom, heat treating the charge trapping film to densify the charge trapping film, and applying a dielectric constant higher than silicon nitride on the heat treated charge trapping film. Forming a blocking film including a metal oxide having a metal oxide, forming a conductive film on the blocking film, and patterning the conductive film, the blocking film, the charge trapping film, and the tunnel insulating film to form a gate structure on the channel region. It may comprise the step of forming.

According to one embodiment of the invention, the heat treatment may be carried out at a temperature of 1150 to 1250 ℃.

According to one embodiment of the present invention, the metal oxide is hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium ( Nd, samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium ( Lu) and the like. In addition, the metal oxide may further include silicon.

According to an embodiment of the present invention, the heat treatment may be performed in a gas atmosphere containing nitrogen. In addition, the heat treatment may be performed in an inert gas atmosphere.

According to an embodiment of the present invention, the heat treatment may be performed in a gas atmosphere having an oxygen partial pressure of 1 × 10 ⁻⁴ torr or less.

According to the embodiments of the present invention as described above, the charge trapping film may be densified by the heat treatment. Accordingly, an unwanted film may be prevented from being formed on the charge trapping film while the blocking film is formed, thereby improving the threshold voltage window characteristic of the nonvolatile memory device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments and may be implemented in other forms. The embodiments introduced herein are provided to make the disclosure more complete and to fully convey the spirit and features of the invention to those skilled in the art. In the drawings, the thickness of each device or film (layer) and regions has been exaggerated for clarity of the invention, and each device may have a variety of additional devices not described herein. When (layer) is mentioned as being located on another film (layer) or substrate, an additional film (layer) may be formed directly on or between the other film (layer) or substrate.

1 to 7 are schematic cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

1 to 3, an active region is defined by forming an isolation layer (not shown) on a surface portion of a semiconductor substrate 100 such as a silicon wafer. Specifically, the device isolation layer is formed on the surface portion of the semiconductor substrate 100 through a local oxidation of silicon (LOCOS) process or a shallow trench isolation (STI) process.

The tunnel insulating layer 102, the charge trapping layer 104, the blocking layer 108, and the conductive layer 110 are sequentially formed on the semiconductor substrate 100.

The tunnel insulating layer 102 may be made of silicon oxide (SiO ₂ ), and may be formed by a thermal oxidation process. The tunnel insulating layer 102 may have a thickness of about 30 to about 100 μs. For example, the tunnel insulating layer 102 may be formed on the semiconductor substrate 100 to have a thickness of about 40 GPa.

The charge trapping film 104 is formed to trap electrons from the channel region of the semiconductor substrate 100. The charge trapping film 104 may include silicon nitride (eg, Si ₃ N ₄ ).

The charge trapping film 104 may be formed to a thickness of about 20 to about 100 kHz on the tunnel insulating film 102 by low pressure chemical vapor deposition. For example, the charge trapping film 104 may be formed on the tunnel insulating film 102 to a thickness of about 60 μs.

After the charge trapping film 104 is formed, heat treatment is performed at a temperature of about 1000 to 1250 ° C. to densify the charge trapping film 104. The heat treatment is performed to prevent the formation of an unwanted film on the charge trapping film 104 in a subsequent process for forming the blocking film 108 by densifying the charge trapping film 104.

In particular, the heat treatment may be performed at a temperature of about 1150 to 1250 ℃. For example, the heat treatment may be performed at a temperature of about 1200 ℃.

In addition, the heat treatment may be performed in a gas atmosphere containing nitrogen. For example, it may be performed in a nitrogen (N ₂ ) gas atmosphere or in an ammonia (NH ₃ ) gas atmosphere.

According to another embodiment of the present invention, the heat treatment may be performed in an inert gas atmosphere such as argon (Ar) or helium (He).

In order to prevent the surface portion of the charge trapping film 104 from being oxidized during the heat treatment, the heat treatment may be performed in a gas atmosphere having an oxygen partial pressure of about 1 × 10 ⁻⁴ torr or less. desirable. For example, the heat treatment may be performed in a gas atmosphere having an oxygen partial pressure of about 1 × 10 ⁻⁶ to 1 × 10 ⁻⁴ torr. In particular, the heat treatment is preferably performed in a gas atmosphere having an oxygen partial pressure of about 1 × 10 ⁻⁶ torr or less. Therefore, it is possible to prevent the silicon oxynitride film from being formed on the charge trapping film 104 during the heat treatment.

The blocking film 108 is formed on the heat treated charge trapping film 106. The blocking film 108 provides electrical insulation between the charge trapping film 106 and the conductive film 110. The blocking film 108 may be formed of a high dielectric constant material having a higher dielectric constant than silicon oxide, silicon oxynitride, or silicon nitride, and may be formed by chemical vapor deposition or atomic layer deposition. For example, the blocking film 108 may include aluminum oxide, and may be formed on the charge trapping film 106 to a thickness of about 100 to about 400 kPa. In particular, the blocking layer 108 may be formed on the charge trapping layer 106 to a thickness of about 200 μs.

According to one embodiment of the present invention, the metal oxide is hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium ( Nd, samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium ( Lu) and the like. In particular, the blocking layer 108 may include hafnium aluminum oxide (HfAlO), lanthanum oxide (La ₂ O ₃ ), aluminum lanthanum oxide (AlLaO), hafnium lanthanum oxide (HfLaO), and the like.

According to another embodiment of the present invention, the blocking film 108 may include metal oxynitride, metal silicon oxide, metal silicon oxynitride, and the like, and the metal may be hafnium (Hf), zirconium (Zr), or tantalum ( Ta, aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium ( Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and the like.

While forming the blocking film 108, since the charge trapping film 106 is sufficiently compacted by the heat treatment, an unwanted reaction byproduct film can be prevented from being formed on the charge trapping film 106. Can be. Specifically, the oxidation reaction between the oxidant provided to form the blocking film 108 and the surface portion of the charge trapping film 106 can be sufficiently suppressed, thus the charge trapping film 106 Formation of a reaction byproduct film such as a silicon oxynitride film on the phase can be prevented.

Hereinafter, a method of forming an aluminum oxide film serving as the blocking film 108 on the heat treated charge trapping film 106 through atomic layer deposition will be described in detail.

First, the semiconductor substrate 100 on which the charge trapping film 106 is formed is positioned in a chamber (not shown) for atomic layer deposition. In this case, the temperature inside the chamber may be maintained at about 150 to 400 ℃ degree, the pressure may be maintained at about 0.1 to 3.0 torr. For example, the temperature inside the chamber may be maintained at about 300 ° C., and the pressure may be maintained at about 1.0 torr.

A first reactant including an aluminum precursor is provided on the charge trapping film 106 to form an aluminum precursor film on the charge trapping film 106. A gaseous aluminum precursor may be used as the first reactant, and the gaseous aluminum precursor may be carried by a carrier gas such as nitrogen or argon. The vapor phase aluminum precursor may also be provided through a liquid delivery system (LDS) or a bubbler system.

Examples of the aluminum precursors include TMA (trimethyl aluminum, Al (CH ₃ ) ₃ ), TEA (triethyl aluminum, Al (C ₂ H ₅ ) ₃ ), and mixtures thereof. The first reactant may be introduced onto the semiconductor substrate 100 for about 0.5 to 3 seconds. For example, the first reactant may be introduced onto the semiconductor substrate 100 for about 2 seconds.

A portion of the first reactant material provided on the semiconductor substrate 100 as described above is chemisorbed on the charge trapping film 106 to form the aluminum precursor film, and the rest is physically adsorbed on the aluminum precursor film or the Drift in the chamber.

After the aluminum precursor film is formed, the chamber is evacuated while providing a purge gas into the chamber. Nitrogen or argon may be used as the purge gas, and the purge gas may be supplied for about 0.5 to 5 seconds. For example, the purge gas may be supplied for about 2 seconds.

The first reactant physically adsorbed on the aluminum precursor film and the first reactant drifting in the chamber are evacuated from the chamber together with the purge gas supplied into the chamber.

After the chamber has been purged, a blocking film including the aluminum oxide on the charge trapping film 106 is provided by oxidizing the aluminum precursor film by supplying a second reactive material containing oxygen onto the semiconductor substrate 100. Form (108).

Examples of the second reactive material containing oxygen include O ₃ , O ₂ , H ₂ O, plasma O ₂ , and the like. These may be used alone or in the form of mixtures as the case may be. For example, O ₃ gas may be supplied for about 1 to 5 seconds onto the aluminum precursor film. In particular, the second reactant may be supplied over the aluminum precursor film for about 3 seconds.

Since the charge trapping film 106 is sufficiently compacted by the heat treatment, the reaction between the second reactant and the charge trapping film 106 may be sufficiently suppressed while the second reactant is supplied. have. As a result, formation of an unwanted reaction byproduct film such as silicon oxynitride between the charge trapping film 106 and the blocking film 108 can be sufficiently prevented.

After the blocking film 108 is formed, a purge gas is supplied into the chamber to remove the reaction by-products generated by the reaction of the aluminum precursor film and the second reactant and the remaining second reactant from the chamber. The purge gas may be supplied for about 1 second to 5 seconds. For example, the purge gas may be supplied for about 3 seconds.

Steps for forming the blocking film 108 may be repeatedly performed until the blocking film 108 has a desired thickness.

Subsequently, a conductive film 110 is formed on the blocking film 108. The conductive layer 110 may include a first conductive layer 112, an adhesive layer 114, and a second conductive layer 116.

The first conductive layer 112 is formed on the blocking layer 108 to a thickness of about 100 to about 400 microns. For example, the first conductive layer 112 may be formed to a thickness of about 200 kW using chemical vapor deposition, atomic layer deposition, physical vapor deposition, and the like.

The first conductive layer 112 may be formed of a material having a work function of about 4 eV or more. For example, the first conductive layer 112 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and hafnium (Hf). , Niobium (Nb), molybdenum (Mo), molybdenum nitride (Mo ₂ N), ruthenium monoxide (RuO), ruthenium dioxide (RuO ₂ ), iridium (Ir), iridium oxide (IrO ₂ ), platinum (Pt), cobalt (Co), chromium (Cr), titanium aluminide (Ti ₃ Al), titanium aluminum nitride (Ti ₂ AlN), palladium (Pd), tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi), Tantalum silicide (TaSi) and the like.

According to another embodiment of the present invention, subsequent processing for increasing the work function of the first conductive layer 112 may be additionally performed. For example, after the first conductive layer 112 is formed, a heat treatment, a plasma treatment, or an ion implantation process may be additionally performed. The subsequent processing may be performed using a material element different from the material element forming the first conductive layer 112. In particular, the subsequent treatment may be performed using a gas containing a Group 2 to Group 8 element. For example, the subsequent treatment is performed using a gas containing elements of N, O, F, Ne, He, P, S, Cl, Ar, As, Se, Br, Kr, Sb, Te, I or Xe. Can be.

After the first conductive film 112 is formed, an adhesive film 114 is formed on the first conductive film 112 to a thickness of about 50 GPa. A metal nitride film may be used as the adhesive layer 114, and a tungsten nitride film, a titanium nitride film, a tantalum nitride film, or the like may be used as the metal nitride film.

A second conductive film 116 is formed on the adhesive film 114. The second conductive layer 116 may be made of tungsten, and may be formed on the adhesive layer 114 to a thickness of about 300 μs. Alternatively, the second conductive layer 116 may be made of metal silicide. As the metal silicide, tungsten silicide, tantalum silicide, cobalt silicide, titanium silicide, or the like may be used.

Referring to FIG. 4, a photoresist pattern is formed on the conductive layer 110. The photoresist pattern may be formed using a photolithography process that is well known in the art.

The gate electrode structure 120 including the first conductive layer pattern 122, the adhesive layer pattern 124, and the second conductive layer pattern 126 on the blocking layer 108 by patterning the conductive layer 110. To form. For example, the gate electrode structure 120 may be formed by performing an anisotropic etching process using the photoresist pattern as an etching mask. The first conductive layer pattern 122 may function as a gate electrode, and the second conductive layer pattern 126 may function as a word line.

The photoresist pattern may be removed through an ashing and stripping process after forming the gate electrode structure 120.

Referring to FIG. 5, a spacer layer 128 is formed on the gate electrode structure 120 and the blocking layer 108. The spacer layer 128 may include a silicon oxide layer 130 and a silicon nitride layer 132. Specifically, after the silicon oxide layer 130 is formed on the gate electrode structure 120 and the blocking layer 108, a silicon nitride layer 132 is formed on the silicon oxide layer 130. The silicon oxide layer 130 and the silicon nitride layer 132 may be formed using a chemical vapor deposition process, respectively. According to another embodiment of the present invention, the silicon nitride film 130 may be formed in-situ after the silicon oxide film 132 is formed.

Referring to FIG. 6, the spacer layer 128 is anisotropically etched to form a double spacer 134 on side surfaces of the gate electrode structure 120. The double spacer 134 includes a silicon oxide spacer 136 and a silicon nitride spacer 138.

According to another embodiment of the present invention, the spacer layer may have a single layer structure including silicon oxide or silicon nitride, and a single layer spacer may be formed on side surfaces of the gate electrode structure 120.

Referring to FIG. 7, the blocking film 108, the charge trapping film 106, and the tunnel insulating film 102 are performed by performing anisotropic etching using the gate electrode structure 120 and the double spacer 134 as an etching mask. ), A blocking film pattern 140, a charge trapping film pattern 142, and a tunnel insulating film pattern 146 are formed.

As a result, the gate electrode structure 120, the double spacer 134, the blocking film pattern 140, the charge trapping film pattern 142, and the tunnel insulating layer are formed on the channel region 100a of the semiconductor substrate 100. A gate structure 150 is formed that includes the pattern 144.

According to another exemplary embodiment of the present disclosure, an reoxidation process may be performed to etch damage of the semiconductor substrate 100 and the gate structure 150 generated during the formation of the gate structure 150.

In addition, according to another embodiment of the present invention, the gate structure may be formed by sequentially patterning the conductive layer 110, the blocking layer 108, the charge trapping layer 106, and the tunnel insulating layer 102. The gate structure formed as described above may include a conductive layer pattern, a blocking layer pattern, a charge trapping layer pattern, and a tunnel insulation layer pattern, and spacers may be formed on side surfaces of the gate structure.

Subsequently, source / drain regions 152a and 152b are formed in surface portions of the semiconductor substrate 100 adjacent to the gate structure 150. The source / drain regions 152a and 152b may be formed by an ion implantation process and a heat treatment process using the gate structure 150 as an ion implantation mask.

As described above, the nonvolatile memory device 10 manufactured according to an embodiment of the present invention may be used as a single level cell (SLC) or a multi level cell (MLC), and may be used for FN tunneling. Alternatively, channel hot electron injection can be used to program and erase data electrically.

When the nonvolatile memory device 10 is used as a single level cell, one bit of information may be stored in the charge trapping film pattern 142. For example, a logic state of '0' or '1' may be stored in the charge trapping film pattern 142.

Specifically, when a programming voltage of about 5 to 18V is applied to the gate electrode structure 120, electrons from the channel region 100a of the semiconductor substrate 100 are tunneled by the FN tunneling pattern 142 by FN tunneling. Trapped at trap sites. Accordingly, a logic state of '1' is stored in the charge trapping film pattern 142. That is, the threshold voltage in the channel region 100a is changed according to the logic state stored in the charge trapping film pattern 142, and the logic state is in the gate electrode structure 120 and the drain region 152b. It may be determined by detecting different currents in the channel region 100a by applying different read voltages, respectively.

When the nonvolatile memory device 10 is used as a multi-level cell, a logic state of '00', '01', '10', or '11' may be stored in the charge trapping film pattern 142. .

Specifically, the nonvolatile memory device 10 may have different threshold voltages according to the number of electrons trapped in the charge trapping film pattern 142, and the nonvolatile memory device 10 according to the threshold voltages. ) May store logic states of '00', '01', '10' or '11'.

Meanwhile, electrons may be trapped in the charge trapping film pattern 142 by channel hot electron injection. Specifically, when programming voltages are applied to the gate electrode structure 120 and the drain region 152b and the source region 152a is grounded, electrons are transferred from the source region 152a to the drain region 152b. It moves through the channel region 100a. In this case, some of the electrons may obtain sufficient energy to overcome the potential barrier of the tunnel insulation pattern 144 and may be trapped at the trap sites of the charge trapping layer pattern 142. . As a result, the threshold voltage of the nonvolatile memory device 10 is increased, so that one bit of information may be stored in the nonvolatile memory device 10.

Threshold Voltage Window for Nonvolatile Memory Devices

8 is a graph illustrating a threshold voltage of a nonvolatile memory device formed by a conventional method and a threshold voltage of a nonvolatile memory device formed according to an embodiment of the present invention.

First, a first nonvolatile memory device was manufactured on a semiconductor substrate according to a conventional method. Specifically, the first nonvolatile memory device has a thickness of about 40 GPa, a silicon oxide film serving as a tunnel insulating film, a thickness of about 70 GPa, a silicon nitride film serving as a charge trapping film, and a thickness of about 200 GPa. An aluminum oxide film serving as a blocking film, a tantalum nitride film having a thickness of about 200 GPa and serving as a gate electrode, a tungsten nitride film having a thickness of about 50 GPa and serving as an adhesive or barrier film, and a thickness of about 300 GPa And a tungsten film that functions as a line.

In addition, a second nonvolatile memory device is fabricated on a semiconductor substrate according to an embodiment of the present invention. Specifically, the second nonvolatile memory device has a thickness of about 40 GPa, a silicon oxide film serving as a tunnel insulating film, a thickness of about 70 GPa, a silicon nitride film serving as a charge trapping film, and a thickness of about 200 GPa. An aluminum oxide film serving as a blocking film, a tantalum nitride film having a thickness of about 200 GPa and serving as a gate electrode, a tungsten nitride film having a thickness of about 50 GPa and serving as an adhesive or barrier film, and a thickness of about 300 GPa And a tungsten film that functions as a line. In the fabrication of the second nonvolatile memory device, after the silicon nitride film is formed, a rapid thermal annealing (RTA) process is performed at a temperature of about 1200 ° C. for about 3 minutes. The rapid heat treatment was performed in a gas atmosphere containing nitrogen, wherein the partial pressure of oxygen in the rapid heat treatment chamber was measured at about 5 × 10 ⁻⁶ torr.

Subsequently, threshold voltages of the first and second nonvolatile memory devices were measured. The results are shown in FIG. In Figure 6, the horizontal axis represents the application time of the programming voltage and the erase voltage.

1) A programming voltage of about 17.0 V was applied to the first nonvolatile memory device, thereby measuring the threshold voltage of the programmed first nonvolatile memory device.

2) An erase voltage of about −19.0 V was applied to the first nonvolatile memory device, and thus the threshold voltage of the erased first nonvolatile memory device was measured.

3) A programming voltage of about 17.0 V was applied to the second nonvolatile memory device, thereby measuring the threshold voltage of the programmed second nonvolatile memory device.

4) An erase voltage of about −19.0 V was applied to the second nonvolatile memory device, and thus the threshold voltage of the erased second nonvolatile memory device was measured.

Referring to FIG. 8, in a program operation of applying the programming voltage for about 100 mA, the threshold voltage of the second nonvolatile memory device is reduced by about 0.4V compared to the first nonvolatile memory device.

In addition, in an erase operation in which the erase voltage is applied for about 10 ms, the threshold voltage of the second nonvolatile memory device is reduced by about 2.7 V compared to the first nonvolatile memory device.

As a result, it was confirmed that the threshold voltage window of the second nonvolatile memory device was improved by about 2.3V compared to the first nonvolatile memory device.

According to the embodiments of the present invention as described above, an unwanted film can be sufficiently prevented from being formed between the charge trapping film and the blocking film by the heat treatment, and thus a threshold voltage window of the nonvolatile memory device. Can be increased sufficiently.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (20)

Forming a tunnel insulating film on a substrate having a channel region; Forming a charge trapping film comprising silicon nitride on the tunnel insulating film for trapping electrons from the channel region; Heat treating the charge trapping film at a temperature of 1000 to 1250 ° C. to densify the charge trapping film; Forming a blocking film on the heat treated charge trapping film; Forming a conductive film on the blocking film; And Patterning the conductive film, the blocking film, the charge trapping film, and the tunnel insulating film to form a gate structure on the channel region. The method of claim 1, wherein the blocking layer comprises an oxide. The method of claim 2, wherein the blocking layer comprises silicon oxide. The method of claim 2, wherein the blocking layer comprises a metal oxide having a higher dielectric constant than silicon nitride. The method of claim 4, wherein the metal oxide is hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), With samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu) At least one selected from the group consisting of a method for manufacturing a nonvolatile memory device. The method of claim 5, wherein the metal oxide further comprises silicon. The method of claim 1, wherein the heat treatment is performed in a gas atmosphere containing nitrogen. The method of claim 1, wherein the heat treatment is performed in an inert gas atmosphere. The method of claim 1, wherein the heat treatment is performed in a gas atmosphere having an oxygen partial pressure of 1 × 10 ⁻⁶ to 1 × 10 ⁻⁴ torr. The method of claim 1, wherein the heat treatment is performed in a gas atmosphere having an oxygen partial pressure of 1 × 10 ⁻⁶ torr or less. The method of claim 1, wherein the forming of the gate structure comprises: Patterning the conductive film to form a gate electrode structure; And Patterning the blocking film, the charge trapping film, and the tunnel insulating film to form a blocking film pattern, a charge trapping film pattern, and a tunnel insulating film pattern. The method of claim 11, further comprising forming a spacer on side surfaces of the gate electrode structure, wherein the blocking film, the charge trapping film, and the tunnel insulating film are patterned through an etching process using the spacer as an etching mask. A method of manufacturing a nonvolatile memory device, characterized in that. The method of claim 1, further comprising forming source / drain regions in surface portions of the substrate adjacent to the gate structure after forming the gate structure. Forming a tunnel insulating film on a substrate having a channel region; Forming a charge trapping film comprising silicon nitride on the tunnel insulating film for trapping electrons from the channel region; Heat treating the charge trapping film to densify the charge trapping film; Forming a blocking film on the heat treated charge trapping film, the blocking film comprising a metal oxide having a higher dielectric constant than silicon nitride; Forming a conductive film on the blocking film; And Patterning the conductive film, the blocking film, the charge trapping film, and the tunnel insulating film to form a gate structure on the channel region. The method of claim 14, wherein the heat treatment is performed at a temperature of 1150 to 1250 ° C. 16. The method of claim 14, wherein the metal oxide is hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), With samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu) A method of manufacturing a nonvolatile memory device, characterized in that it comprises at least one selected from the group consisting of. 17. The method of claim 16, wherein the metal oxide further comprises silicon. 15. The method of claim 14, wherein the heat treatment is performed in a gas atmosphere containing nitrogen. 15. The method of claim 14, wherein the heat treatment is performed in an inert gas atmosphere. The method of claim 14, wherein the heat treatment is performed in a gas atmosphere having an oxygen partial pressure of 1 × 10 ⁻⁴ torr or less.

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