KR20090010604A - Method of manufacturing a non-volatile memory device - Google Patents

Abstract

A method for manufacturing a non-volatile memory device is provided to improve data maintaining characteristic and reliability of the device by removing defective sites inside a charge trapping layer through a thermal process and preventing the generation of an unwanted layer on the charge trapping layer when forming a blocking layer. A tunnel insulating layer is formed on a substrate(100) having a channel region. A charge trapping layer for trapping electrons from the channel region is formed. The charge trapping layer is compacted by a thermal process using the first gas including nitride and the second gas including oxygen. A blocking layer is formed on the charge trapping layer to perform the thermal process. A conductive layer is formed on the blocking layer. A gate structure(150) is formed on the channel region by patterning the conductive layer, the blocking layer, the charge trapping layer, and the tunnel insulating layer.

Description

Method of manufacturing a non-volatile memory device

The present invention relates to a method of manufacturing a nonvolatile memory device. More particularly, the present invention relates to a method of manufacturing a nonvolatile memory device including a charge trapping film.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), have relatively fast data input and output, while volatile memory devices lose data over time, and ROM Although data input and output is relatively slow, such as read only memory, it can be classified as a non-volatile memory device that can store data permanently. In the case of the nonvolatile memory device, there is an increasing demand for an electrically erasable programmable read only memory (EEPROM) or a flash EEPROM memory capable of electrically inputting / outputting data. The flash EEPROM memory device electrically performs programming and erasing of data using F-N tunneling or channel hot electron injection. The flash memory device may be classified into a nonvolatile memory device of a floating gate type and a nonvolatile memory device of a silicon oxide nitride oxide semiconductor (SONOS) or a metal oxide nitride oxide semiconductor (MONOS) type.

The SONOS or MONOS type nonvolatile memory device includes a tunnel insulating film formed on a semiconductor substrate, a charge trapping film for trapping electrons moving through the channel region, a blocking film formed on the charge trapping film, and the blocking. It may include a gate electrode formed on the film, a spacer formed on the side surfaces of the gate electrode.

A silicon nitride film may be used as the charge trapping film. However, defect sites such as silicon dangling bonds, silicon hydrogen bonds, and the like in the silicon nitride film may cause lateral charge diffusion, thereby greatly reducing data retention and reliability of the nonvolatile memory device. .

The SONOS or MONOS type nonvolatile memory device may be used as a single level cell (SLC) or a multi level cell (MLC).

When the nonvolatile memory device is used as a single level cell, a logic state of '0' or '1' may be stored in the charge trapping layer.

When the nonvolatile memory device 10 is used as a multi-level cell, a logic state of '00', '01', '10', or '11' may be stored in the charge trapping layer.

When the nonvolatile memory device is used as a multi-level cell, more thermal stress or electrical stress may be applied to the nonvolatile memory device as compared with the case where the nonvolatile memory device is used as a single level cell. Thus, when the nonvolatile memory device is used as a multi-level cell, a threshold voltage window of about 6.0V or more is required.

A metal oxide film having a higher dielectric constant than silicon nitride may be used as the blocking film to increase the threshold voltage window of the nonvolatile memory device. For example, an aluminum oxide film may be used as the blocking film.

However, during the formation of the aluminum oxide film, an unwanted film may be formed between the silicon nitride film used as the charge trapping film and the aluminum oxide film. For example, an aluminum silicon oxynitride layer may be formed between the silicon nitride layer and the aluminum oxide layer, and the aluminum silicon oxynitride layer may reduce the threshold voltage window of the nonvolatile memory device. That is, the electric field applied to the tunnel insulating layer during the programming or erasing operation may be reduced by the aluminum silicon oxynitride layer, and thus the threshold voltage window may be reduced. As a result, the reliability of the nonvolatile memory device may be lowered.

An object of the present invention for solving the above problems is to provide a nonvolatile memory device with improved data retention characteristics and reliability.

According to an aspect of the present invention for achieving the above object, a tunnel insulating film is formed on a substrate having a channel region, a charge trapping film containing silicon nitride on the tunnel insulating film for trapping electrons from the channel region Is formed. The charge trapping film may be heat-treated using a first gas containing nitrogen and a second gas containing oxygen, thereby eliminating defect sites in the charge trapping film, thereby preventing the charge trapping film from being Can be sufficiently compacted.

A blocking film and a conductive film are sequentially formed on the heat-treated charge trapping film, and the conductive film, blocking film, charge trapping film, and tunnel insulating film may be patterned to form a gate structure on the channel region.

According to one embodiment of the present invention, the heat treatment may be performed at a temperature of about 900 ℃ to 1250 ℃.

According to one embodiment of the present invention, the heat treatment may be performed at a temperature of about 1150 ℃ to 1250 ℃.

According to an embodiment of the present invention, the blocking film may include a metal oxide having a higher dielectric constant than silicon nitride.

According to one embodiment of the present invention, the metal oxide is hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium ( Nd, samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium ( Lu), and the like, which may be used alone or in the form of a mixture.

According to an embodiment of the present invention, the metal oxide may further include silicon.

According to an embodiment of the present invention, the first gas may include nitrogen (N ₂ ), ammonia (NH ₃ ), or the like, which may be used alone or in a mixed form.

According to an embodiment of the present invention, the second gas may include oxygen (O ₂ ), ozone (O ₃ ), nitrogen monoxide (NO), and the like, which may be used alone or in a mixed form. .

According to an embodiment of the present invention, the heat treatment may be performed using a mixed gas of the first gas and the second gas.

According to an embodiment of the present invention, the mixed gas may include about 90% to about 99% nitrogen and about 1% to about 10% nitrogen monoxide.

According to one embodiment of the present invention, the mixed gas may include about 95% to 98% nitrogen and about 2% to 5% nitrogen monoxide.

According to one embodiment of the present invention, the mixed gas may include about 95% to 99% nitrogen and about 1% to 5% oxygen.

According to one embodiment of the present invention, the mixed gas may include about 97% to 99% nitrogen and about 1% to 3% ozone.

According to an embodiment of the present invention, the first heat treatment using the first gas and the second heat treatment using the second gas may be sequentially performed.

According to an embodiment of the present invention, a densified silicon oxynitride film may be formed on the charge trapping film by the heat treatment.

According to an embodiment of the present invention, the conductive layer may be patterned to form a gate electrode structure, and then the blocking layer, the charge trapping layer, and the tunnel insulation layer may include a blocking layer pattern, a charge trapping layer pattern, and a tunnel insulation layer pattern. It can be patterned to form.

In example embodiments, a spacer may be formed on side surfaces of the gate electrode structure, and the blocking layer, the charge trapping layer, and the tunnel insulating layer may be patterned through an etching process using the spacer as an etching mask. have.

According to an embodiment of the present invention, source / drain regions may be formed in surface portions of the substrate adjacent to the gate structure after the gate structure is formed.

According to embodiments of the present invention, defect sites in the charge trapping film can be sufficiently removed by the heat treatment. In addition, the charge trapping film can be sufficiently densified by the heat treatment so that an unwanted film can be prevented from being generated on the charge trapping film while forming the blocking film. As a result, data retention characteristics and reliability of the nonvolatile memory device can be greatly improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments and may be implemented in other forms. The embodiments introduced herein are provided to make the disclosure more complete and to fully convey the spirit and features of the invention to those skilled in the art. In the drawings, the thickness of each device or film (layer) and regions has been exaggerated for clarity of the invention, and each device may have a variety of additional devices not described herein. When (layer) is mentioned as being located on another film (layer) or substrate, an additional film (layer) may be formed directly on or between the other film (layer) or substrate.

1 to 7 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

1 and 2, an active region is defined by forming an isolation layer (not shown) on a surface portion of a semiconductor substrate 100 such as a silicon wafer. Specifically, the device isolation layer is formed on the surface portion of the semiconductor substrate 100 through a local oxidation of silicon (LOCOS) process or a shallow trench isolation (STI) process.

The tunnel insulating layer 102, the charge trapping layer 104, the blocking layer 108, and the conductive layer 110 are sequentially formed on the semiconductor substrate 100.

The tunnel insulating layer 102 may be made of silicon oxide (SiO ₂ ), and may be formed by a thermal oxidation process. The tunnel insulating layer 102 may have a thickness of about 30 to about 100 μs. For example, the tunnel insulating layer 102 may be formed on the semiconductor substrate 100 to have a thickness of about 40 GPa.

The charge trapping film 104 is formed to trap electrons from the channel region of the semiconductor substrate 100. The charge trapping film 104 may include silicon nitride (eg, Si ₃ N ₄ ).

The charge trapping film 104 may be formed to a thickness of about 20 to about 100 kHz on the tunnel insulating film 102 by low pressure chemical vapor deposition. For example, the charge trapping film 104 may be formed on the tunnel insulating film 102 to a thickness of about 60 μs.

After the charge trapping film 104 is formed, heat treatment is performed at a temperature of about 900 ° C to 1250 ° C to densify the charge trapping film 104. The heat treatment may be performed to prevent unwanted film formation on the charge trapping film 104 in a subsequent process for forming the blocking film 108 by densifying the charge trapping film 104. . In particular, the heat treatment may be performed at a temperature of about 1150 ℃ to 1250 ℃ to increase the densification effect of the charge trapping film 104.

In addition, the heat treatment may be performed to remove defect sites in the charge trapping film 104. In particular, defect sites such as silicon dangling bonds, silicon hydrogen bonds, and the like are present in the charge trapping film 104, and electrical characteristics of the charge trapping film 104 may be degraded by the defect sites. . For example, the defect sites may cause lateral diffusion of electrons in the charge trapping film 104, thus the data retention characteristics and reliability of a nonvolatile memory device including the charge trapping film 104. This can be degraded.

The heat treatment may be performed using a mixed gas of a first gas containing nitrogen and a second gas containing oxygen to remove the defect sites. During the heat treatment, hydrogen and oxygen in the charge trapping film 104 may be replaced, and silicon dangling bonds may be removed. As a result, the surface portion of the charge trapping film 104 may be formed of a densified silicon oxynitride film (SiON).

In addition, by performing the heat treatment, the nitrogen concentration of the interface portion between the tunnel insulating film 102 and the substrate 100 may be increased, and thus the dielectric constant of the tunnel insulating film 102 may be increased and the tunnel may be increased. The leakage current through the insulating film 102 can be reduced. As a result, the reliability of the nonvolatile memory device can be improved.

Nitrogen (N ₂ ) or ammonia (NH ₃ ) may be used as the first gas, and these may be used in the form of a mixed gas. Nitrogen monoxide (NO), oxygen (O ₂ ) or ozone (O ₃ ) may be used as the second gas, and they may be used in the form of a mixed gas. The mixed gas may be provided at a flow rate of about 0.5 to 1.0 l / min.

For example, the heat treatment may be performed using a mixed gas of nitrogen and nitrogen monoxide. The mixed gas may include about 90% to about 99% nitrogen and about 1% to about 10% nitrogen monoxide. In particular, the mixed gas may include about 95% to 98% nitrogen and about 2% to 5% nitrogen monoxide.

Meanwhile, although nitrous oxide (N 2 O) may be used as the second gas, the nitrous oxide is not suitable for use as the second gas because the oxidizing power is relatively higher than that of nitrogen monoxide.

According to another embodiment of the present invention, the mixed gas may include about 95% to about 99% nitrogen gas and about 1% to about 5% oxygen gas.

According to another embodiment of the present invention, the mixed gas may include about 97% to 99% nitrogen gas and about 1% to 3% ozone gas.

According to another embodiment of the present invention, the charge trapping film 104 may be densified by the first heat treatment and the second heat treatment. For example, a first heat treatment using the first gas and a second heat treatment using the second gas may be sequentially performed. In particular, the second heat treatment may be performed by a rapid thermal process (RTP) facility using oxygen or ozone. For example, the second heat treatment may be performed for about 1 to 5 minutes in an oxygen gas atmosphere using the rapid heat treatment process equipment. In addition, the second heat treatment may be performed for about 1 minute to 3 minutes in an ozone gas atmosphere using the rapid heat treatment process equipment.

According to another embodiment of the present invention, the heat treatment may be performed at a temperature of about 1000 ℃ to 1250 ℃ using the first gas. In particular, the heat treatment may be performed at a temperature of about 1150 to 1250 ℃. For example, the heat treatment may be performed at a temperature of about 1200 ° C. in a nitrogen gas atmosphere.

According to another embodiment of the present invention, the heat treatment may be performed in an inert gas atmosphere such as argon (Ar) or helium (He).

이하의 산소 분압(partial pressure)을 갖는 가스 분위기에서 수행될 수 있다. 예를 들면, 상기 열처리는 약

내지

정도의 산소 분압을 갖는 가스 분위기에서 수행될 수 있다. 특히, 상기 열처리는 약

이하의 산소 분압을 갖는 가스 분위기에서 수행되는 것이 바람직하다.The heat treatment is about to prevent oxidation of the surface portion of the charge trapping film 104 during the heat treatment using the first gas.

It may be performed in a gas atmosphere having the following oxygen partial pressure. For example, the heat treatment is about

To

It may be performed in a gas atmosphere having a degree of oxygen partial pressure. In particular, the heat treatment is about

It is preferably carried out in a gas atmosphere having the following oxygen partial pressure.

A heat treatment using the first gas may be performed to densify the charge trapping film 104 and remove defect sites in the charge trapping film 104.

Referring to FIG. 3, the blocking film 108 is formed on the heat treated charge trapping film 106. The blocking film 108 provides electrical insulation between the charge trapping film 106 and the conductive film 110. The blocking film 108 may be made of a high dielectric constant material having a higher dielectric constant than silicon oxide or silicon nitride, and may be formed by chemical vapor deposition or atomic layer deposition. For example, the blocking film 108 may include aluminum oxide, and may be formed on the charge trapping film 106 to a thickness of about 100 to about 400 kPa. In particular, the blocking layer 108 may be formed on the charge trapping layer 106 to a thickness of about 200 μs.

According to one embodiment of the present invention, the metal oxide is hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium ( Nd, samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium ( Lu) and the like. In particular, the blocking layer 108 may include hafnium aluminum oxide (HfAlO), lanthanum oxide (La ₂ O ₃ ), aluminum lanthanum oxide (AlLaO), hafnium lanthanum oxide (HfLaO), and the like.

According to another embodiment of the present invention, the blocking film 108 may include metal oxynitride, metal silicon oxide, metal silicon oxynitride, and the like, and the metal may be hafnium (Hf), zirconium (Zr), or tantalum ( Ta, aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium ( Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and the like.

While forming the blocking film 108, the charge trapping film 106 is sufficiently compacted by the heat treatment, so that an unwanted reaction byproduct film, for example, on the charge trapping film 106 is Formation of the metal silicon oxynitride film can be prevented. Specifically, the reaction between the metal precursor provided to form the blocking film 108 and the oxidant and the surface portion of the charge trapping film 106 can be sufficiently suppressed, and thus the charge trapping film ( The formation of a metal silicon oxide film, eg, aluminum silicon oxide film, on 106 can be prevented.

Hereinafter, a method of forming an aluminum oxide film serving as the blocking film 108 on the heat treated charge trapping film 106 through atomic layer deposition will be described in detail.

First, the semiconductor substrate 100 on which the charge trapping film 106 is formed is positioned in a chamber (not shown) for atomic layer deposition. In this case, the temperature inside the chamber may be maintained at about 150 to 400 ℃ degree, the pressure may be maintained at about 0.1 to 3.0 torr. For example, the temperature inside the chamber may be maintained at about 300 ° C., and the pressure may be maintained at about 1.0 torr.

A first reactant including an aluminum precursor is provided on the charge trapping film 106 to form an aluminum precursor film on the charge trapping film 106. A gaseous aluminum precursor may be used as the first reactant, and the gaseous aluminum precursor may be carried by a carrier gas such as nitrogen or argon. The vapor phase aluminum precursor may also be provided through a liquid delivery system (LDS) or a bubbler system.

Examples of the aluminum precursors include TMA (trimethyl aluminum, Al (CH ₃ ) ₃ ), TEA (triethyl aluminum, Al (C ₂ H ₅ ) ₃ ), and mixtures thereof. The first reactant may be introduced onto the semiconductor substrate 100 for about 0.5 to 3 seconds. For example, the first reactant may be introduced onto the semiconductor substrate 100 for about 2 seconds.

A portion of the first reactant material provided on the semiconductor substrate 100 as described above is chemisorbed on the charge trapping film 106 to form the aluminum precursor film, and the rest is physically adsorbed on the aluminum precursor film or the Drift in the chamber.

After the aluminum precursor film is formed, the chamber is evacuated while providing a purge gas into the chamber. Nitrogen or argon may be used as the purge gas, and the purge gas may be supplied for about 0.5 to 5 seconds. For example, the purge gas may be supplied for about 2 seconds.

The first reactant physically adsorbed on the aluminum precursor film and the first reactant drifting in the chamber are evacuated from the chamber together with the purge gas supplied into the chamber.

After the chamber has been purged, a blocking film including the aluminum oxide on the charge trapping film 106 is provided by oxidizing the aluminum precursor film by supplying a second reactive material containing oxygen onto the semiconductor substrate 100. Form 108.

Examples of the second reactive material containing oxygen include O ₃ , O ₂ , H ₂ O, plasma O ₂ , and the like. These may be used alone or in the form of mixtures as the case may be. For example, O ₃ gas may be supplied for about 1 to 5 seconds onto the aluminum precursor film. In particular, the second reactant may be supplied over the aluminum precursor film for about 3 seconds.

Since the charge trapping film 106 is sufficiently densified by the heat treatment, the reaction between the aluminum precursor film and the second reactant material and the charge trapping film 106 is prevented while the second reactant material is supplied. It can be sufficiently suppressed. As a result, formation of an unwanted reaction byproduct film such as aluminum silicon oxynitride between the charge trapping film 106 and the blocking film 108 can be sufficiently prevented.

After the blocking film 108 is formed, a purge gas is supplied into the chamber to remove the reaction by-products generated by the reaction of the aluminum precursor film and the second reactant and the remaining second reactant from the chamber. The purge gas may be supplied for about 1 second to 5 seconds. For example, the purge gas may be supplied for about 3 seconds.

Steps for forming the blocking film 108 may be repeatedly performed until the blocking film 108 has a desired thickness.

Subsequently, a conductive film 110 is formed on the blocking film 108. The conductive layer 110 may include a first conductive layer 112, an adhesive layer 114, and a second conductive layer 116.

The first conductive layer 112 is formed on the blocking layer 108 to a thickness of about 100 to about 400 microns. For example, the first conductive layer 112 may be formed to a thickness of about 200 kW using chemical vapor deposition, atomic layer deposition, physical vapor deposition, and the like.

The first conductive layer 112 may be formed of a material having a work function of about 4 eV or more. For example, the first conductive layer 112 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and hafnium (Hf). , Niobium (Nb), molybdenum (Mo), molybdenum nitride (Mo ₂ N), ruthenium monoxide (RuO), ruthenium dioxide (RuO ₂ ), iridium (Ir), iridium oxide (IrO ₂ ), platinum (Pt), cobalt (Co), chromium (Cr), titanium aluminide (Ti ₃ Al), titanium aluminum nitride (Ti ₂ AlN), palladium (Pd), tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi), Tantalum silicide (TaSi) and the like.

According to another embodiment of the present invention, subsequent processing for increasing the work function of the first conductive layer 112 may be additionally performed. For example, after the first conductive layer 112 is formed, a heat treatment, a plasma treatment, or an ion implantation process may be additionally performed. The subsequent processing may be performed using a material element different from the material element forming the first conductive layer 112. In particular, the subsequent treatment may be performed using a gas containing a Group 2 to Group 8 element. For example, the subsequent treatment is performed using a gas containing elements of N, O, F, Ne, He, P, S, Cl, Ar, As, Se, Br, Kr, Sb, Te, I or Xe. Can be.

After the first conductive film 112 is formed, an adhesive film 114 is formed on the first conductive film 112 to a thickness of about 50 GPa. A metal nitride film may be used as the adhesive layer 114, and a tungsten nitride film, a titanium nitride film, a tantalum nitride film, or the like may be used as the metal nitride film.

A second conductive film 116 is formed on the adhesive film 114. The second conductive layer 116 may be made of tungsten, and may be formed on the adhesive layer 114 to a thickness of about 300 μs. Alternatively, the second conductive layer 116 may be made of metal silicide. As the metal silicide, tungsten silicide, tantalum silicide, cobalt silicide, titanium silicide, or the like may be used.

Referring to FIG. 4, a photoresist pattern is formed on the conductive layer 110. The photoresist pattern may be formed using a photolithography process that is well known in the art.

The gate electrode structure 120 including the first conductive layer pattern 122, the adhesive layer pattern 124, and the second conductive layer pattern 126 on the blocking layer 108 by patterning the conductive layer 110. To form. For example, the gate electrode structure 120 may be formed by performing an anisotropic etching process using the photoresist pattern as an etching mask. The first conductive layer pattern 122 may function as a gate electrode, and the second conductive layer pattern 126 may function as a word line.

The photoresist pattern may be removed through an ashing and stripping process after forming the gate electrode structure 120.

Referring to FIG. 5, a spacer layer 128 is formed on the gate electrode structure 120 and the blocking layer 108. The spacer layer 128 may include a silicon oxide layer 130 and a silicon nitride layer 132. Specifically, after the silicon oxide layer 130 is formed on the gate electrode structure 120 and the blocking layer 108, a silicon nitride layer 132 is formed on the silicon oxide layer 130. The silicon oxide layer 130 and the silicon nitride layer 132 may be formed using a chemical vapor deposition process, respectively. According to another embodiment of the present invention, the silicon nitride film 130 may be formed in-situ after the silicon oxide film 132 is formed.

Referring to FIG. 6, the spacer layer 128 is anisotropically etched to form a double spacer 134 on side surfaces of the gate electrode structure 120. The double spacer 134 includes a silicon oxide spacer 136 and a silicon nitride spacer 138.

According to another embodiment of the present invention, the spacer layer may have a single layer structure including silicon oxide or silicon nitride, and a single layer spacer may be formed on side surfaces of the gate electrode structure 120.

Referring to FIG. 7, the blocking film 108, the charge trapping film 106, and the tunnel insulating film 102 are performed by performing anisotropic etching using the gate electrode structure 120 and the double spacer 134 as an etching mask. The blocking film pattern 140, the charge trapping film pattern 142, and the tunnel insulating film pattern 146 are formed from the.

As a result, the gate electrode structure 120, the double spacer 134, the blocking film pattern 140, the charge trapping film pattern 142, and the tunnel insulating film pattern on the channel region 100a of the semiconductor substrate 100. A gate structure 150 is formed that includes 144.

According to another exemplary embodiment of the present disclosure, an reoxidation process may be performed to etch damage of the semiconductor substrate 100 and the gate structure 150 generated during the formation of the gate structure 150.

In addition, according to another embodiment of the present invention, the gate structure may be formed by sequentially patterning the conductive layer 110, the blocking layer 108, the charge trapping layer 106, and the tunnel insulating layer 102. The gate structure formed as described above may include a conductive layer pattern, a blocking layer pattern, a charge trapping layer pattern, and a tunnel insulation layer pattern, and spacers may be formed on side surfaces of the gate structure.

Subsequently, source / drain regions 152a and 152b are formed in surface portions of the semiconductor substrate 100 adjacent to the gate structure 150. The source / drain regions 152a and 152b may be formed by an ion implantation process and a heat treatment process using the gate structure 150 as an ion implantation mask.

As described above, the nonvolatile memory device 10 manufactured according to an embodiment of the present invention may be used as a single level cell (SLC) or a multi level cell (MLC), and may be used for FN tunneling. Alternatively, channel hot electron injection can be used to program and erase data electrically.

When the nonvolatile memory device 10 is used as a single level cell, one bit of information may be stored in the charge trapping film pattern 142. For example, a logic state of '0' or '1' may be stored in the charge trapping film pattern 142.

Specifically, when a programming voltage of about 5 to 18V is applied to the gate electrode structure 120, electrons from the channel region 100a of the semiconductor substrate 100 are tunneled by the FN tunneling pattern 142 by FN tunneling. Trapped at trap sites. Accordingly, a logic state of '1' is stored in the charge trapping film pattern 142. That is, the threshold voltage in the channel region 100a is changed according to the logic state stored in the charge trapping film pattern 142, and the logic state is in the gate electrode structure 120 and the drain region 152b. It may be determined by detecting different currents in the channel region 100a by applying different read voltages, respectively.

When the nonvolatile memory device 10 is used as a multi-level cell, a logic state of '00', '01', '10', or '11' may be stored in the charge trapping film pattern 142. .

Specifically, the nonvolatile memory device 10 may have different threshold voltages according to the number of electrons trapped in the charge trapping film pattern 142, and the nonvolatile memory device 10 according to the threshold voltages. ) May store logic states of '00', '01', '10' or '11'.

Meanwhile, electrons may be trapped in the charge trapping film pattern 142 by channel hot electron injection. Specifically, when programming voltages are applied to the gate electrode structure 120 and the drain region 152b and the source region 152a is grounded, electrons are transferred from the source region 152a to the drain region 152b. To move through the channel region 100a. In this case, some of the electrons may obtain sufficient energy to overcome the potential barrier of the tunnel insulation pattern 144 and may be trapped at the trap sites of the charge trapping layer pattern 142. . As a result, the threshold voltage of the nonvolatile memory device 10 is increased, so that one bit of information may be stored in the nonvolatile memory device 10.

Analysis of charge trapping membrane

According to the conventional method, a silicon oxide film having a thickness of about 40 GPa and functioning as a first tunnel insulating film was formed on a semiconductor substrate. Subsequently, a silicon nitride film capable of functioning as a first charge trapping film was formed on the first tunnel insulating film to a thickness of about 70 kPa.

According to an embodiment of the present invention, a silicon oxide film having a thickness of about 40 GPa is formed on a semiconductor substrate and can function as a second tunnel insulating film, and functions as a second charge trapping film on the second tunnel insulating film. Silicon nitride film was formed to a thickness of about 70 kHz. Subsequently, heat treatment was performed at a temperature of about 950 ° C. for about 30 minutes using a mixed gas of about 98% nitrogen gas and about 2% nitrogen monoxide gas. At this time, the mixed gas was supplied at a flow rate of about 1 l / min. For example, nitrogen gas was supplied into the chamber where the heat treatment was performed at a flow rate of about 0.98 l / min, and nitrogen monoxide gas was supplied at a flow rate of about 0.02 l / min.

According to an embodiment of the present invention, a silicon oxide film having a thickness of about 40 GPa is formed on a semiconductor substrate and may function as a third tunnel insulating film, and may function as a third charge trapping film on the third tunnel insulating film. Silicon nitride film was formed to a thickness of about 70 kHz. Subsequently, heat treatment was performed for about 30 minutes at a temperature of about 1000 ° C. using nitrogen gas.

8 illustrates hydrogen concentration in a first tunnel insulating film and a first charge trapping film formed by a conventional technique, and second and third tunnel insulating films and second and third charge trapping formed by embodiments of the present invention. It is a graph showing the hydrogen concentration in the membranes.

Secondary ion mass spectrometry (SIMS) Hydrogen concentrations in the first, second and third tunnel insulating films and the first, second and third charge trapping films were measured. As shown in FIG. 8, hydrogen concentrations in the second and third tunnel insulating layers and the second and third charge trapping layers are significantly reduced compared to the first tunnel insulating layer and the first charge trapping layer. Able to know. This means that the silicon hydrogen bonds in the second and third tunnel insulating films and the second and third charge trapping films are removed by the heat treatment using the mixed gas and the heat treatment using the nitrogen gas.

9 is a graph showing the oxygen concentration in the first charge trapping film formed by the prior art and the oxygen concentration in the second charge trapping film formed by the embodiment of the present invention.

In addition, the oxygen concentration in the first charge trapping film and the second charge trapping film was measured using a secondary ion mass spectrometer. As shown in FIG. 9, it can be seen that the oxygen concentration in the second charge trapping film is increased compared to the first charge trapping film. This means that the silicon dangling bonds in the second charge trapping film were removed by heat treatment using the mixed gas.

High Temperature Stress Characteristics of Nonvolatile Memory Devices

According to a conventional method, a first nonvolatile memory device is manufactured on a semiconductor substrate. Specifically, the first nonvolatile memory device has a thickness of about 40 GPa, a silicon oxide film serving as a tunnel insulating film, a thickness of about 70 GPa, a silicon nitride film serving as a charge trapping film, and a thickness of about 200 GPa. An aluminum oxide film serving as a blocking film, a tantalum nitride film having a thickness of about 200 GPa and serving as a gate electrode, a tungsten nitride film having a thickness of about 50 GPa and serving as an adhesive or barrier film, and a thickness of about 300 GPa And a tungsten film that functions as a line.

A second nonvolatile memory device is manufactured on a semiconductor substrate according to an embodiment of the present invention. Specifically, the second nonvolatile memory device has a thickness of about 40 GPa, a silicon oxide film serving as a tunnel insulating film, a thickness of about 70 GPa, a silicon nitride film serving as a charge trapping film, and a thickness of about 200 GPa. An aluminum oxide film serving as a blocking film, a tantalum nitride film having a thickness of about 200 GPa and a gate electrode, a tungsten nitride film having a thickness of about 50 GPa and serving as an adhesive or barrier film, and a thickness of about 300 GPa; And a tungsten film that functions as a word line. In the manufacturing of the second nonvolatile memory device, after forming the silicon nitride layer, about 60 minutes at a temperature of about 950 ° C. using a mixed gas of about 90% nitrogen gas and about 10% nitrogen monoxide gas. Was performed. The mixed gas was supplied at a flow rate of about 1 l / min. For example, nitrogen gas was supplied at a flow rate of about 0.9 l / min and nitrogen monoxide gas was supplied at a flow rate of about 0.1 l / min into the chamber where the heat treatment is performed.

In accordance with an embodiment of the present invention, a third nonvolatile memory device is manufactured on a semiconductor substrate. Specifically, the third nonvolatile memory device has a thickness of about 40 GPa, a silicon oxide film serving as a tunnel insulating film, a thickness of about 70 GPa, a silicon nitride film serving as a charge trapping film, and a thickness of about 200 GPa. An aluminum oxide film serving as a blocking film, a tantalum nitride film having a thickness of about 200 GPa and serving as a gate electrode, a tungsten nitride film having a thickness of about 50 GPa and serving as an adhesive or barrier film, and a thickness of about 300 GPa And a tungsten film that functions as a line. In the manufacturing of the third nonvolatile memory device, after forming the silicon nitride film, about 120 minutes at a temperature of about 950 ° C. using a mixed gas of about 90% nitrogen gas and about 10% nitrogen monoxide gas. Was performed. The mixed gas was supplied at a flow rate of about 1 l / min. For example, nitrogen gas was supplied at a flow rate of about 0.9 l / min and nitrogen monoxide gas was supplied at a flow rate of about 0.1 l / min into the chamber where the heat treatment is performed.

In accordance with an embodiment of the present invention, a fourth nonvolatile memory device is manufactured on a semiconductor substrate. Specifically, the fourth nonvolatile memory device has a thickness of about 40 GPa, a silicon oxide film serving as a tunnel insulating film, a thickness of about 70 GPa, a silicon nitride film serving as a charge trapping film, and a thickness of about 200 GPa. An aluminum oxide film serving as a blocking film, a tantalum nitride film having a thickness of about 200 GPa and serving as a gate electrode, a tungsten nitride film having a thickness of about 50 GPa and serving as an adhesive or barrier film, and a thickness of about 300 GPa And a tungsten film that functions as a line. In the manufacturing of the fourth nonvolatile memory device, after the silicon nitride film is formed, 60 minutes at a temperature of about 950 ° C. using a mixed gas of about 95% nitrogen gas and about 5% nitrogen monoxide gas. Was performed. The mixed gas was supplied at a flow rate of about 1 l / min. For example, nitrogen gas was supplied into the chamber where the heat treatment was performed at a flow rate of about 0.95 l / min, and nitrogen monoxide gas was supplied at a flow rate of about 0.05 l / min.

Subsequently, high temperature stress characteristic tests were performed on the first, second, third and fourth nonvolatile memory devices.

Specifically, after performing programming operations of each of the first, second, third, and fourth nonvolatile memory devices, threshold voltages of each of the first, second, third, and fourth nonvolatile memory devices are determined. Measured. A programming voltage of about 17.0V was applied for about 100 Hz to perform the programming operations.

The programming and erasing operations were repeatedly performed 1200 times for each of the first, second, third and fourth nonvolatile memory devices. Here, a programming voltage of about 17.0V is applied to the first, second, third, and fourth nonvolatile memory devices, and an erase voltage of about -19.0V is applied to the first, second, third, and fourth nonvolatile memory devices. In addition, the programming voltage was applied for 100 kV while the erase voltage was applied for 10 kV while performing the operations.

After repeatedly performing the programming and erase operations, the first, second, third and fourth nonvolatile memory devices were baked at a temperature of about 200 ° C. for about 2 hours. After performing the bake process, threshold voltages of the first, second, third and fourth nonvolatile memory devices were measured.

FIG. 10 is a graph illustrating threshold voltage changes of a first nonvolatile memory device formed by a conventional technology and threshold voltage changes of second, third, and fourth nonvolatile memory devices formed by embodiments of the present invention.

Referring to FIG. 10, it can be seen that the threshold voltage variation of the second, third, and fourth nonvolatile memory devices is greatly reduced compared to the first nonvolatile memory device. In particular, it can be seen that the threshold voltage change amount of the fourth nonvolatile memory device is the smallest, which means that the threshold voltage change amount of the nonvolatile memory devices depends on the flow rate of nitrogen monoxide. As a result, it was confirmed that the heat treatment of the charge trapping film is most preferably performed using a mixed gas of nitrogen gas of about 95% to 98% and nitrogen monoxide gas of about 2% to 5%.

Threshold Voltage Window for Nonvolatile Memory Devices

In accordance with an embodiment of the present invention, a fifth nonvolatile memory device is manufactured on a semiconductor substrate. Specifically, the fifth nonvolatile memory device has a thickness of about 40 GPa, a silicon oxide film serving as a tunnel insulating film, a thickness of about 70 GPa, a silicon nitride film serving as a charge trapping film, and a thickness of about 200 GPa. An aluminum oxide film serving as a blocking film, a tantalum nitride film having a thickness of about 200 GPa and serving as a gate electrode, a tungsten nitride film having a thickness of about 50 GPa and serving as an adhesive or barrier film, and a thickness of about 300 GPa And a tungsten film that functions as a line. In the manufacture of the second nonvolatile memory device, after the silicon nitride film was formed, a rapid heat treatment process was performed at a temperature of about 1200 ° C. for about 3 minutes. The rapid heat treatment was performed in a gas atmosphere containing nitrogen, wherein the partial pressure of oxygen in the chamber in which the rapid heat treatment process is performed was measured at about 5 × 10 ⁻⁶ torr.

Subsequently, threshold voltages of the first and fifth nonvolatile memory devices were measured. The results are shown in FIG. In Figure 6, the horizontal axis represents the application time of the programming voltage and the erase voltage.

A programming voltage of about 17.0 V was applied to the first nonvolatile memory device, thereby measuring the threshold voltage of the programmed first nonvolatile memory device.

An erase voltage of about −19.0 V was applied to the first nonvolatile memory device, and thus the threshold voltage of the erased first nonvolatile memory device was measured.

A programming voltage of about 17.0 V was applied to the fifth nonvolatile memory device, thereby measuring the threshold voltage of the programmed fifth nonvolatile memory device.

An erase voltage of about −19.0 V was applied to the fifth nonvolatile memory device, and thus the threshold voltage of the erased fifth nonvolatile memory device was measured.

FIG. 11 is a graph illustrating a threshold voltage of a first nonvolatile memory device formed by a conventional technology and a threshold voltage of a fifth nonvolatile memory device formed by an embodiment of the present invention.

Referring to FIG. 11, in a program operation of applying the programming voltage for about 100 mA, the threshold voltage of the fifth nonvolatile memory device is reduced by about 0.4V compared to the first nonvolatile memory device.

In addition, in an erase operation in which the erase voltage is applied for about 10 ms, the threshold voltage of the fifth nonvolatile memory device is reduced by about 2.7 V compared to the first nonvolatile memory device.

As a result, it was confirmed that the threshold voltage window of the fifth nonvolatile memory device was improved by about 2.3V compared to the first nonvolatile memory device.

According to the embodiments of the present invention as described above, the charge trapping film of the nonvolatile memory device can be sufficiently densified by high temperature heat treatment, thereby improving data retention characteristics and reliability of the nonvolatile memory device.

In particular, the charge trapping film may be sufficiently densified by a heat treatment using a mixed gas of a first gas containing nitrogen and a second gas containing oxygen, and a densified silicon oxynitride film may be formed on the charge trapping film. Can be. In addition, the heat treatment of the charge trapping film may be performed in a gas atmosphere containing nitrogen.

Defect sites within the charge trapping film can be sufficiently removed by the heat treatment, and the charge trapping film is sufficiently densified by the heat treatment, so that a reaction byproduct film such as a metal silicon oxynitride film is formed in a subsequent blocking film deposition process. Can be prevented.

As a result, charge side diffusion in the charge trapping film and reduction of the threshold voltage window of the nonvolatile memory device can be prevented.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

1 to 7 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

8 illustrates hydrogen concentration in a first tunnel insulating film and a first charge trapping film formed by a conventional technique, and second and third tunnel insulating films and second and third charge trapping formed by embodiments of the present invention. It is a graph showing the hydrogen concentration in the membranes.

9 is a graph showing the oxygen concentration in the first charge trapping film formed by the prior art and the oxygen concentration in the second charge trapping film formed by the embodiment of the present invention.

FIG. 10 is a graph illustrating threshold voltage changes of a first nonvolatile memory device formed by a conventional technology and threshold voltage changes of second, third, and fourth nonvolatile memory devices formed by embodiments of the present invention.

FIG. 11 is a graph illustrating a threshold voltage of a first nonvolatile memory device formed by a conventional technology and a threshold voltage of a fifth nonvolatile memory device formed by an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10 nonvolatile memory device 100 semiconductor substrate

102 tunnel insulating film 104 charge trapping film

106 heat treated charge trapping film 108 blocking film

110 conductive film 120 gate electrode structure

134: double spacer 150: gate structure

152a, 152b: source drain region

Claims (18)

Forming a tunnel insulating film on a substrate having a channel region; Forming a charge trapping film comprising silicon nitride on the tunnel insulating film for trapping electrons from the channel region; Performing heat treatment using a first gas comprising nitrogen and a second gas comprising oxygen to remove defect sites in the charge trapping film and to densify the charge trapping film; Forming a blocking film on the heat treated charge trapping film; Forming a conductive film on the blocking film; And Patterning the conductive film, the blocking film, the charge trapping film, and the tunnel insulating film to form a gate structure on the channel region. The method of claim 1, wherein the heat treatment is performed at a temperature of 900 ° C. to 1250 ° C. 6. The method of claim 2, wherein the heat treatment is performed at a temperature of 1150 ° C. to 1250 ° C. 4. The method of claim 1, wherein the blocking layer comprises a metal oxide having a dielectric constant higher than that of silicon nitride. The method of claim 4, wherein the metal oxide is hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), With samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu) At least one selected from the group consisting of a method for manufacturing a nonvolatile memory device. The method of claim 5, wherein the metal oxide further comprises silicon. The method of claim 1, wherein the first gas comprises at least one selected from the group consisting of nitrogen (N ₂ ) and ammonia (NH ₃ ). The method of claim 1, wherein the second gas comprises at least one selected from the group consisting of oxygen (O ₂ ), ozone (O ₃ ), and nitrogen monoxide (NO). The method of claim 1, wherein the heat treatment is performed using a mixed gas of the first gas and the second gas. 10. The method of claim 9, wherein the mixed gas comprises 90% to 99% nitrogen and 1% to 10% nitrogen monoxide. The method of claim 10, wherein the mixed gas comprises 95% to 98% nitrogen and 2% to 5% nitrogen monoxide. 10. The method of claim 9, wherein the mixed gas comprises 95% to 99% nitrogen and 1% to 5% oxygen. 10. The method of claim 9, wherein the mixed gas comprises 97% to 99% nitrogen and 1% to 3% ozone. The method of claim 1, wherein the first heat treatment using the first gas and the second heat treatment using the second gas are sequentially performed. The method of claim 1, wherein a densified silicon oxynitride film is formed on the charge trapping film by the heat treatment. The method of claim 1, wherein the forming of the gate structure comprises: Patterning the conductive film to form a gate electrode structure; And Patterning the blocking film, the charge trapping film, and the tunnel insulating film to form a blocking film pattern, a charge trapping film pattern, and a tunnel insulating film pattern. The method of claim 16, further comprising forming a spacer on side surfaces of the gate electrode structure, wherein the blocking film, the charge trapping film, and the tunnel insulating film are patterned through an etching process using the spacer as an etching mask. A method of manufacturing a nonvolatile memory device, characterized in that. The method of claim 1, further comprising forming source / drain regions in surface portions of the substrate adjacent to the gate structure after forming the gate structure.

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