JP2004158810A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory having high data retention capability of a trap insulating film and high data reliability. <P>SOLUTION: In a single gate type nonvolatile semiconductor memory, a gate insulating film 41 between a substrate 20 and a gate electrode 42 is formed to a three-layer structure of a silicon oxide film 41a (tunnel insulating film), an Al<SB>2</SB>O<SB>2</SB>film 41b (trap insulating film) and a silicon oxide film 41c (top insulating film), starting from the substrate 20 side. The trap insulating film can be formed of an insulating film, which is mainly composed of an oxide comprising Al, Hf, Zr or Ln (lanthanoids). The tunnel insulating film can be formed of a material whose barrier height is smaller than that of the silicon oxide film. The top insulating film can be formed of a material whose specific inductive capacity is higher than that of the silicon oxide film. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention has a gate insulating film formed by stacking a tunnel insulating film, a trap insulating film, and a top insulating film, and writes and erases data by transferring electric charges to and from the trap insulating film through the tunnel insulating film. And a nonvolatile semiconductor memory that performs
[0002]
[Prior art]
2. Description of the Related Art In a conventional nonvolatile semiconductor memory, a floating gate type memory having a double gate structure having two gate electrodes, a floating gate and a control gate, is generally used (for example, Japanese Patent Application Laid-Open No. 2-26072). However, in recent years, a complicated manufacturing process having a double gate structure has become prominent as an obstacle to miniaturization.
[0003]
For this reason, a single-gate nonvolatile semiconductor memory having one gate electrode has attracted attention. In a single-gate nonvolatile semiconductor memory, a material capable of storing electric charge is used in a gate insulating film between a semiconductor substrate and a gate electrode, and the threshold voltage changes due to the electric charge stored in the gate insulating film. This is used to store data. Such single-gate nonvolatile semiconductor memories include a SONOS (Silicon Oxide Nitride Oxide Silicon) type memory and a MONOS (Metal Oxide Nitride Oxide Silicon) type memory.
[0004]
FIG. 1 is a schematic sectional view showing a memory cell structure of a conventional SONOS type memory (Japanese Patent Application Laid-Open No. 2001-358237). In the SONOS type memory, one memory cell is constituted by one FET (Field Effect Transistor).
[0005]
In the silicon semiconductor substrate 10, a pair of impurity diffusion regions 11 serving as a source / drain are formed separately from each other. A gate insulating film 12 is formed on a region between the pair of impurity diffusion regions 11. The gate insulating film 12 is formed by silicon oxide (SiO 2) from the substrate 10 side. ₂ ) A film 12a, a silicon nitride (SiN) film 12b, and a silicon oxide film 12c are sequentially laminated. A gate electrode 13 made of polysilicon is formed on the gate insulating film 12.
Further, sidewalls 14 made of a silicon oxide film are formed on both sides of the gate electrode 13 and the gate insulating film 12.
[0006]
When writing data in the SONOS memory configured as described above, a sufficiently high voltage is applied to the gate electrode 13 and a predetermined voltage is applied between the pair of impurity diffusion regions 11. As a result, hot electrons generated near the impurity diffusion region 11 on the drain side are tunneled through the silicon oxide film 12a and injected into the silicon nitride layer 12b, and as a result, the threshold voltage of the memory cell (FET) changes. Since the silicon oxide film 12c is formed on the silicon nitride film 12b, the electrons injected into the silicon nitride film 12b are prevented from flowing to the gate electrode 13.
[0007]
On the other hand, when erasing data written in the memory cell, a positive voltage is applied to both the pair of impurity diffusion regions 11 and a negative voltage is applied to the gate electrode 13. As a result, the electrons accumulated in the silicon nitride film 12b tunnel through the silicon oxide film 12a and are eliminated toward the substrate 10.
[0008]
An insulating film that traps electric charges, such as the silicon nitride film 12b, is called a trap insulating film, an insulating film between the semiconductor substrate and the trap insulating film is called a tunnel insulating film, and an insulating film between the trap insulating film and the gate electrode is formed. The insulating film is called a top insulating film.
[0009]
It should be noted, Boaz Eitan said the like of the literature ( "Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?", Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999 ) Describes the structure of a SONOS type NROM. Japanese Patent Application Laid-Open No. 2000-58831 describes a nonvolatile semiconductor memory in which a trap insulating film is formed of a titanium oxide film.
[0010]
[Patent Document 1]
JP-A-2-26072
[Patent Document 2]
JP 2001-358237 A (FIG. 2)
[Patent Document 3]
JP-A-2000-58831 (FIG. 31)
[Non-patent document 1]
See Boaz Eitan et al. "Can NROM, a2 Bit, Trapping Storage NVM Cell, Givea Real Challenge to Floating Gate Cells?"
[0011]
[Problems to be solved by the invention]
However, the present inventors consider that the above-mentioned conventional SONOS type memory has the following problems. That is, in a conventional SONOS type memory, a silicon nitride film is used as a trap insulating film. However, the charge holding ability of the silicon nitride film is not sufficient, and it cannot be said that data reliability is sufficiently ensured.
[0012]
In a conventional SONOS memory, a silicon oxide film is used as a top insulating film. However, since the dielectric constant of the silicon oxide film is low, the ratio of the electric field from the gate electrode acting on the tunnel insulating film is small due to the coupling ratio. Therefore, if the voltage applied to the gate electrode is not increased, the time required for writing / erasing data becomes longer. In order to increase the voltage applied to the gate electrode, it is necessary to increase the element size of the memory cell and the peripheral circuit to increase the breakdown voltage, which hinders high integration of the semiconductor device.
[0013]
Further, in the conventional SONOS type memory, since a silicon oxide film is used as a tunnel insulating film, the barrier height is high, and the time required for writing / erasing data is lengthened.
[0014]
In view of the above, an object of the present invention is to provide a nonvolatile semiconductor memory in which a trap insulating film has a high data holding capability and high data reliability.
[0015]
Another object of the present invention is to provide a nonvolatile semiconductor memory which can perform data writing / erasing in a short time.
[0016]
[Means for Solving the Problems]
The above object is achieved by providing a semiconductor substrate, a pair of impurity diffusion regions formed in the semiconductor substrate, a tunnel insulating film formed on a region between the pair of impurity diffusion regions, ₂ O ₃ , HfO ₂ , ZrO ₂ And Ln ₂ O ₃ (Where Ln is a lanthanoid element) a trap insulating film formed on the tunnel insulating film by at least one oxide selected from the group consisting of: a top insulating film formed on the trap insulating film; And a gate electrode formed on the top insulating film.
[0017]
Further, the above-mentioned problem is solved by a semiconductor substrate, a pair of impurity diffusion regions formed in the semiconductor substrate, a tunnel insulating film formed on a region between the pair of impurity diffusion regions, Al, Hf, Zr And Ln (where Ln is a lanthanoid element), a trap insulating film formed on the tunnel insulating film by an oxide mainly containing one element selected from the group consisting of: The problem is solved by a nonvolatile semiconductor memory including a formed top insulating film and a gate electrode formed on the top insulating film.
[0018]
Note that the lanthanoid elements refer to 15 elements from La (lanthanum) having an atomic number of 57 to Lu (lutetium) having an atomic number of 71.
[0019]
Further, in the present application, for example, when an oxide containing Al as a main component is described, it means that the number of Al atoms is the largest, or that it is the second largest after oxygen. The same applies to an oxide containing Hf as a main component, an oxide containing Zr as a main component, and an oxide containing Ln as a main component. Furthermore, AlHfO ₂ Is an oxide containing Al as a main component and HfAlO ₂ When it is described, it means that it is an oxide containing Hf as a main component.
[0020]
The present inventors have conducted various experimental studies to improve the data reliability of the single-gate nonvolatile semiconductor memory. As a result, the trap insulating film was formed of alumina (Al). ₂ O ₃ ) Or other oxides containing Al (aluminum) have been found to significantly improve data retention. The present invention has been made based on such experimental results.
[0021]
Alumina (Al) ₂ O ₃ ) Or other oxides containing aluminum improve the data retention ability, but the trap level of these oxides is deeper than the trap level of the silicon nitride film, and the This is probably because the accumulated charge is difficult to escape.
[0022]
Therefore, in the present invention, the trap insulating film is formed of an insulator mainly containing an oxide containing aluminum. Examples of oxides containing aluminum include, for example, Al ₂ O ₃ , AlHfO, AlZrO, AlTaO, AlTiO and ZrAlO. Also, Al ₂ O ₃ The trap insulating film may be formed of a silicate or aluminate of at least one compound of AlHfO, AlZrO, AlTaO, AlTiO and ZrAlO.
[0023]
In addition, according to experiments performed by the present inventors, HfO ₂ And an oxide containing Hf as a main component, ZrO ₂ And an oxide containing Zr as a main component, and Ln ₂ O ₃ Also, it has been found that the data retention ability can be improved even when any one of the oxides containing Ln as a main component is used as the trap insulating film. Therefore, a trap insulating film may be formed using these compounds.
[0024]
Al ₂ O ₃ Has a deep trap level and can stably trap charges. On the other hand, HfO ₂ And Ln ₂ O ₃ Is not so deep, the HfO ₂ And Ln ₂ O ₃ Is Al ₂ O ₃ It is considered that it is harder to hold the electric charge in the same place (trap) as compared with However, Al ₂ O ₃ Has a high barrier height and the difference from the oxide film is as small as about 0.5 to 0.8 eV. Therefore, there is no problem if electrons can be held in the same trap. However, when the charge is separated from the trap, the electrons easily leak from the upper and lower oxide films. In contrast, HfO ₂ And Ln ₂ O ₃ Has a low barrier height and a large difference from an oxide film of 2 to 2.5 eV, so that even if charges escape from one trap, charges rarely leak due to the high barrier of the upper and lower oxide films.
[0025]
There are two types of MONOS type memories: a method of trapping charges in the entire insulating film and a method of selectively trapping charges in a local portion in the insulating film. When the present invention is applied to a MONOS memory, ₂ O ₃ (Or an oxide containing Al as a main component) is preferably used for a local trapping method. ₂ And Ln ₂ O ₃ (Or, an oxide containing Hf or Ln as a main component) is preferably used in a method in which it is trapped in the entire insulating film.
[0026]
When the tunnel insulating film is formed of a material having a lower barrier height than a conventionally used silicon oxide film, the efficiency of hot electron injection into the trap insulating film is improved, and the data read / write time is reduced. Therefore, it is preferable that the tunnel insulating film be formed of a material having a lower barrier height than the silicon oxide film. Materials having a lower barrier height than the silicon oxide film include, for example, SiN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , SrTiO ₂ , BaSrTiO ₃ , TiO ₂ , AlN, Ta ₂ O ₅ , TaN, HfAlO and ZrAlO. Also, SiN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , SrTiO ₂ , BaSrTiO ₃ , TiO ₂ , AlN, Ta ₂ O ₅ , TaN, HfAlO and ZrAlO, the tunnel insulating film may be formed of a silicate or aluminate of any one compound.
[0027]
If the top insulating film is formed of a material having a higher dielectric constant than the conventionally used silicon oxide film, the electric field from the gate electrode can effectively act on the tunnel insulating film, and as a result, the driving voltage can be increased. The data write / erase time can be shortened without performing. Therefore, it is preferable that the top insulating film be formed of a material having a higher dielectric constant than the silicon oxide film. The relative permittivity of the silicon oxide film is usually 4 or less, and materials having a higher relative permittivity include, for example, SiN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , SrTiO ₂ , BaSrTiO ₃ , TiO ₂ , AlN, Ta ₂ O ₅ , TaN, HfAlO and ZrAlO. Also, SiN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , SrTiO ₂ , BaSrTiO ₃ , TiO ₂ , AlN, Ta ₂ O ₅ , TaN, HfAlO and ZrAlO, the top insulating film may be formed of a silicate or aluminate of one of the compounds.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0029]
(Nonvolatile semiconductor memory)
2 is a plan view of a nonvolatile semiconductor memory to which the present invention is applied, FIG. 3A is a cross-sectional view taken along line II of FIG. 2, FIG. 3B is a cross-sectional view taken along line II-II of FIG. FIG. 3C is a sectional view taken along line III-III in FIG.
[0030]
On the surface of p-type silicon semiconductor substrate 20, a local insulating film 22 for defining an active region is formed. This local insulating film 22 extends in a direction perpendicular to the paper surface of FIG. On the active region of the silicon semiconductor substrate 20, a laminated gate insulating film 23 is formed. The laminated gate insulating film 23 has a three-layer structure in which a tunnel insulating film 23a, a trap insulating film 23b, and a top insulating film 23c are sequentially stacked from the substrate 20 side.
[0031]
Below the local insulating film 22, a bit line 21 composed of an impurity diffusion region formed by introducing As (arsenic) into the silicon semiconductor substrate 20 is arranged. A word line 24 extending in the lateral direction of FIG. 3A is formed on the local insulating film 22 and the stacked gate insulating film 23. This word line 24 is formed of, for example, polysilicon or amorphous silicon.
[0032]
The bit line 21 and the word line 24 are insulated at a crossing point by a local insulating film 22 existing therebetween. However, in this structure, the local insulating film 22 is not essential, and may be provided as needed. The memory cell (FET) 25 is formed at a portion where a pair of bit lines 21 adjacent to each other and one word line 24 intersect, the pair of bit lines 21 are used as a source and a drain, and the word line 24 is used as a gate. It is configured as an electrode.
[0033]
A channel stopper region 26 formed by introducing a p-type impurity into the silicon semiconductor substrate 20 is provided between channel regions of two memory cells 25 adjacent to each other in the direction in which the bit line 21 extends.
[0034]
FIG. 4 is a block diagram showing an example of a circuit configuration of the nonvolatile semiconductor memory of the present invention. The source and the drain of the memory cell 25 are respectively connected to two adjacent bit lines 21, and the gate electrode is connected to the word line 24.
[0035]
A plurality of memory cells 25 are arranged in a matrix to form a memory cell array. Each memory cell 25 is assigned a unique address. The memory cell array is divided into a plurality of blocks, and each memory cell 25 belongs to any one block.
[0036]
The bit line 21 is connected to the sense amplifier unit 31 and the word line 24 is connected to a word line driver 32. The control circuit 30 controls the sense amplifier unit 21 and the word line driver 32. Here, the bit lines 21 are represented by BL1, BL2, BL3, BL4... In order from the left side of FIG. 4, and the word lines 24 are represented by WL1, WL2, WL3, WL4.
[0037]
The control circuit 30 has an address counter (not shown). Specific bit lines 21 and word lines 24 are selected based on the address set in the address counter, and a desired memory cell 25 can be accessed.
[0038]
The control circuit 30 is controlled by an external CPU 33. The RAM 33 is connected to the CPU 33. In the RAM 34, data to be written to the memory cell 25 is temporarily stored.
[0039]
Hereinafter, the operation of the above-described nonvolatile semiconductor memory will be described. The operation described below is executed by the control circuit 20 in accordance with an instruction from the CPU 30.
[0040]
(Data write operation)
At the time of data writing, a write voltage Vdp (for example, 6 V) is applied to the bit line 21 connected to the drain of the selected memory cell, the bit line 21 connected to the source is set to 0 V, and the voltage Vwp (for example, , 10 V). At this time, the bit line 21 and the word line 24 of the non-selected cell are floated to avoid writing data.
[0041]
When the above-described data write operation is performed, hot electrons are generated near the drain in the selected memory cell. Hot electrons are trapped in the trap insulating film 23b over the barrier of the tunnel insulating film 23a. Thereby, the threshold voltage of the selected memory cell (FET) 25 shifts in the positive direction. This state is defined as a state in which data is written, that is, “0”.
[0042]
(Data erase operation)
The data erase operation is performed on all the memory cells of the selected block at once. At the time of data erasing, the voltage Vwe (for example, −6 V) is applied to all of the word lines 24 of the selected block, and the voltage Vbe (for example, 6 V) is applied to all of the bit lines 21. As a result, the electrons trapped in the trap insulating film 23b are eliminated toward the substrate 20, and the threshold voltage of the memory cell (FET) 25 shifts in the negative direction. This state is defined as a state where data is erased, that is, “1”.
[0043]
(Data read operation)
When reading data, a voltage Vwr (for example, 4 V) is applied to the word line 24 connected to the selected memory cell, and a read voltage Vbr (for example, 1.4 V) is applied to the bit line 21 connected to the drain. A voltage of 0 V is applied to the bit line 21 connected to the source. Then, the current flowing through the memory cell (FET) 25 is compared with a reference current to determine whether the current is “1” or “0”.
[0044]
However, at the time of reading, the impurity diffusion layer used as the source at the time of data writing is used as the drain, and the impurity diffusion layer used as the drain at the time of data writing is used as the source. This is because electrons are trapped in the vicinity of the impurity diffusion region used as the drain during data writing, and the threshold value can be shifted more by inverting the drain and source during reading. is there.
[0045]
(First Embodiment)
FIG. 5 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the first embodiment of the present invention.
[0046]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment has a laminated gate insulating film 41 formed on p-type silicon semiconductor substrate 20 and a gate electrode made of polysilicon formed on laminated gate insulating film 41. 42. The laminated gate insulating film 41 includes a silicon oxide film 41a, alumina (Al ₂ O ₃ ) A film 41b and a silicon oxide film 41c are laminated. The gate electrode 42, the silicon oxide film 41a, the alumina film 41b, and the silicon oxide film 41c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively. In addition, alumina (Al ₂ O ₃ ) Has a relative dielectric constant of about 9 to 10.
[0047]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0048]
The silicon oxide film 41a serving as a tunnel insulating film is formed by a thermal oxidation method. For example, after a mask of a silicon nitride film is formed on the surface of the silicon semiconductor substrate 20 in a predetermined pattern, the surface of the silicon semiconductor substrate 20 is thermally oxidized at a temperature of 1000 ° C. in a dry atmosphere to have a thickness of about 7 nm. A silicon oxide film 41a is formed. After that, the silicon nitride film is removed. The silicon oxide film 41a may have a thickness of 2 to 10 nm, and may be formed by a method other than the thermal oxidation method.
[0049]
The alumina film 41b serving as a trap insulating film is formed by an ALCVD (Atomic Layer Chemical Vapor Deposition) method. For example, Al (CH ₃ ) ₃ And the raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas. ₃ ) ₃ And ozone (O ₃ ) Are alternately supplied to form the alumina film 41b to a thickness of 10 nm. The alumina film 41b may be formed by a MOCVD (Metal Organic Chemical Vapor Deposition) method or a PVD (Physical Vapor Deposition) method. Further, the alumina film 41b may be formed to a thickness of 1 to 40 nm.
[0050]
The silicon oxide film 41c serving as the top insulating film is formed by an LPCVD (Low Pressure Chemical Vapor Deposition) method. For example, the pressure in the chamber of the LPCVD apparatus is 133 Pa, the substrate temperature is 800 ° C., and the SiH ₄ And N ₂ By reacting with O, a silicon oxide film (HTO: high temperature oxide film) is formed to a thickness of 10 nm. The silicon oxide film 41c may be formed by a CVD method using a TEOS source, an MOCVD method, or a plasma CVD method. Further, the silicon oxide film 41c may be formed to a thickness of 3 to 20 nm.
[0051]
The gate electrode 42 is formed of polysilicon or amorphous silicon doped with an impurity such as phosphorus or boron. For example, a silicon film is formed to a thickness of 100 nm by LPCVD at a pressure in the chamber of 26 Pa and a substrate temperature of 600 ° C., and the silicon film is patterned by photolithography to form a gate electrode 42. The gate electrode 42 may be formed to a thickness of 50 to 200 nm. Further, after forming a non-doped silicon film, an impurity such as phosphorus or boron may be doped, or a silicon film doped with an impurity such as phosphorus or boron by a CVD method may be directly formed on the gate insulating film. Good.
[0052]
In this embodiment mode, an alumina film having higher charge holding ability than a silicon nitride film is used as the trap insulating film. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0053]
After the silicon oxide film 41a, the alumina film 41b, and the silicon oxide film 41c are formed, it is preferable to perform annealing at a temperature of 600 to 1000C.
It is expected that the quality of each film will be increased by this annealing treatment, and that good electrical characteristics will be obtained. Annealing may be performed each time one of these films 41a, 41b, 41c is formed, or may be performed only once after all three films 41a, 41b, 41c are formed.
[0054]
Also, an AlHfO film may be formed instead of the alumina film 41b. The AlHfO film is made of Al (CH ₃ ) ₃ And Hf (C ₂ H ₅ ) ₃ And can be formed by an ALCVD method. Also in this case, since the AlHfO film has a higher charge holding ability than the silicon nitride film, the effect of improving data reliability as compared with the conventional SONOS type memory can be obtained.
[0055]
Hereinafter, a result of actually manufacturing the nonvolatile semiconductor memory of the present embodiment and examining its characteristics will be described.
[0056]
As shown in FIG. 25A, on a p-type silicon semiconductor substrate 20, a silicon oxide film 41a having a thickness of 7 nm as a tunnel insulating film, and alumina (Al) having a thickness of 10 nm as a trap insulating film. ₂ O ₃ ) A film 41b and a silicon oxide film 41c having a thickness of 10 nm were sequentially formed as a top insulating film. Then, a gate electrode 42 made of polysilicon was formed on the laminated gate insulating film 41 having a three-layer structure of the silicon oxide film 41a, the alumina film 41b, and the silicon oxide film 41c. Thereafter, an n-type impurity was introduced into the silicon semiconductor substrate 20 using the gate electrode 42 as a mask to form impurity diffusion regions 40a and 40b serving as source / drain. Note that the gate length L of this nonvolatile semiconductor memory (FET) is 0.35 μm.
[0057]
Data was written to the nonvolatile semiconductor memory manufactured as described above with the drain voltage Vd set to 5 V and the gate voltage Vg set to 9 V, 10 V, and 12 V.
[0058]
FIG. 25B shows the relationship between the write time and the threshold voltage when the gate voltage Vg is 9 V, 10 V, and 12 V (write characteristics), with the horizontal axis representing the write time and the vertical axis representing the threshold voltage Vth. FIG. However, the drain voltage Vd is set to 1.2 V when reading data. From FIG. 25B, it is clear that data is normally written in the nonvolatile semiconductor memory of this embodiment, and it is understood that electric charges are held in the trap insulating film (alumina film 41b). .
[0059]
FIG. 26A shows the time change of the threshold voltage Vth when electric charge is injected only into the Bit 1 side in FIG. 25A by taking time on the horizontal axis and the threshold voltage on the vertical axis. FIG. 11 is a diagram showing the results (data retention characteristics). FIG. 26B is a diagram showing a result (data retention characteristic) of examining a temporal change of the threshold voltage Vth when charges are injected into both the Bit 1 side and the Bit 2 side in FIG. 25A. is there. However, when data is written on the Bit 1 side, the impurity diffusion region 40a is used as a drain and the impurity diffusion region 40b is used as a source. When data is written on the Bit 2 side, the impurity diffusion region 40b is used as a drain and the impurity diffusion region 40a is used as a source. When reading data, the source and the drain are opposite to those at the time of writing data.
[0060]
From FIGS. 26A and 26B, it can be seen that in the nonvolatile semiconductor memory of this embodiment, individual data can be recorded on the Bit1 side and the Bit2 side, respectively.
[0061]
FIG. 27 is a diagram showing erase characteristics when the gate voltage is -7 V and the drain voltage is 6 V, with the erase time taken on the horizontal axis and the threshold voltage Vth taken on the vertical axis. From this figure, it can be seen that the written data is completely erased in about 0.3 seconds.
[0062]
From these results, it was confirmed that the nonvolatile semiconductor memory of this embodiment had good data writing, holding, and erasing characteristics. Further, the nonvolatile semiconductor memory according to the present embodiment can store different data on the Bit 1 side and the Bit 2 side, respectively, which enables further higher integration of the semiconductor device.
[0063]
(Second embodiment)
FIG. 6 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a second embodiment of the present invention.
[0064]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 51 formed on the p-type silicon semiconductor substrate 20 and a polysilicon or amorphous silicon formed on the stacked gate insulating film 51. The stacked gate insulating film 51 constituted by the gate electrode 52 is formed by sequentially stacking a silicon nitride film 51a, an AlHfO film 51b, and a silicon oxide film 51c from the substrate 20 side. The gate electrode 52, the silicon nitride film 51a, the AlHfO film 51b, and the silicon oxide film 51c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively.
[0065]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0066]
The silicon nitride film 51a serving as a tunnel insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is 25 Pa, the substrate temperature is 780 ° C., and the silicon nitride film 51 a is formed to a thickness of 10 nm. The silicon nitride film 51a may be formed by MOCVD or plasma CVD. The silicon nitride film 51a may be formed to a thickness of 2 to 15 nm.
[0067]
The AlHfO film 51b serving as a trap insulating film is formed by an ALCVD method.
For example, Al (CH ₃ ) ₃ And Hf (C ₂ H ₅ ) ₃ The source solution is vaporized by nitrogen bubbling to obtain a source gas, and the source gas and the ozone gas are alternately supplied onto the substrate 20 heated to 300 ° C. to form the AlHfO film 51b to a thickness of 10 nm. . The AlHfO film 51b may be formed by MOCVD or PVD. The AlHfO film 51b may be formed to a thickness of 1 to 40 nm.
[0068]
The silicon oxide film 51c as a top insulating film is formed by an LPCVD method.
For example, the pressure in the chamber of the LPCVD apparatus is 133 Pa, the substrate temperature is 800 ° C., and the SiH ₄ And N ₂ By reacting with O, a high-temperature oxide (HTO) film is formed to a thickness of 10 nm. The silicon oxide film 51c can also be formed by a CVD method using a TEOS source, an MOCVD method, or a plasma CVD method. Further, the silicon oxide film 41c may be formed to a thickness of 3 to 20 nm.
[0069]
After the silicon nitride film 51a, the AlHfO film 51b, and the silicon oxide film 51c are formed, it is preferable to perform an annealing process at a temperature of 600 to 1000C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0070]
Since the method of forming the gate electrode 52 is the same as that of the first embodiment, the description is omitted here.
[0071]
In the present embodiment, an AlHfO film having higher charge holding ability than a silicon nitride film is used as a trap insulating film. As a result, data reliability is improved as compared with the conventional SONOS type memory.
[0072]
In the present invention, a silicon nitride film having a lower barrier height than a silicon oxide film is used as the tunnel insulating film. As a result, the efficiency of hot electron injection into the trap insulating film is improved as compared with the conventional SONOS memory, and the data write / erase time can be reduced.
[0073]
(Third embodiment)
FIG. 7 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a third embodiment of the present invention.
[0074]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 61 formed on the p-type silicon semiconductor substrate 20 and a polysilicon or amorphous silicon formed on the stacked gate insulating film 61. The laminated gate insulating film 61 constituted by the gate electrode 62 is formed by sequentially laminating a silicon oxide film 61a, an AlHfO film 61b, and a silicon nitride film 61c from the substrate 20 side. The gate electrode 62, the silicon oxide film 61a, the AlHfO film 61b, and the silicon nitride film 61c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively.
[0075]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0076]
The silicon oxide film 61a serving as a tunnel insulating film is formed by a thermal oxidation method. For example, after a mask of a silicon nitride film is formed on the surface of the silicon semiconductor substrate 20 in a predetermined pattern, the surface of the silicon semiconductor substrate 20 is thermally oxidized at a temperature of 1000 ° C. in a dry atmosphere to have a thickness of about 7 nm. A silicon oxide film 61a is formed. After that, the silicon nitride film is removed. The silicon oxide film 61a may be formed to a thickness of 2 to 10 nm, and may be formed by a method other than the thermal oxidation method.
[0077]
The AlHfO film 61b serving as a trap insulating film is formed by an ALCVD method.
For example, Al (CH ₃ ) ₃ And Hf (C ₂ H ₅ ) ₃ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied on a substrate having a temperature of 300 ° C. to form the AlHfO film 61b to a thickness of 10 nm. The AlHfO film 61b may be formed by MOCVD or PVD. The AlHfO film 61b may be formed to a thickness of 1 to 40 nm.
[0078]
The silicon nitride film 61c as a top insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is set to 25 Pa, the substrate temperature is set to 780 ° C., and the silicon nitride film 61c is formed to a thickness of 10 nm. The dielectric constant of the silicon nitride film changes depending on the film forming conditions. However, the dielectric constant becomes higher than that of the silicon oxide film in the range of the normal film forming conditions, and the silicon nitride film formed under the above conditions also has the normal film forming condition. The dielectric constant is higher than the silicon oxide film formed under the conditions. The silicon nitride film 61c may be formed by MOCVD or plasma CVD. Further, the silicon nitride film 61c may be formed to a thickness of 2 to 15 nm.
[0079]
After the silicon oxide film 61a, the AlHfO film 61b, and the silicon nitride film 61c are formed, it is preferable to perform annealing at a temperature of 600 to 1000C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0080]
Since the method of forming the gate electrode 62 is the same as that of the first embodiment, the description is omitted here.
[0081]
In the present embodiment, the reliability of data is improved as compared with the conventional SONOS type memory because the trap insulating film is made of the AlHfO film having higher charge holding ability than the silicon nitride film.
[0082]
Further, in the present embodiment, since the silicon nitride film having a higher dielectric constant than the silicon oxide film is used as the top insulating film, the electric field from the gate electrode can effectively act on the tunnel insulating film, As a result, the data write / erase time can be reduced without increasing the drive voltage.
[0083]
(Fourth embodiment)
FIG. 8 is a schematic diagram showing the configuration of the stacked gate insulating film of the nonvolatile semiconductor memory according to the fourth embodiment of the present invention.
[0084]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 71 formed on the p-type silicon semiconductor substrate 20 and a polysilicon or amorphous silicon formed on the stacked gate insulating film 71. The stacked gate insulating film 71 composed of the gate electrode 72 formed of the silicon nitride film 71a, the AlHfO film 71b, and the HfO ₂ The films 71c are formed by sequentially stacking the films 71c. Gate electrode 72, silicon nitride film 71a, AlHfO film 71b and HfO ₂ The film 71c corresponds to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG.
[0085]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0086]
The silicon nitride film 71a as a tunnel insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is 25 Pa, the substrate temperature is 780 ° C., and the silicon nitride film 71 a is formed to a thickness of 10 nm. The silicon nitride film 71a may be formed by MOCVD or plasma CVD. The silicon nitride film 71a may be formed to a thickness of 2 to 15 nm.
[0087]
The AlHfO film 71b serving as a trap insulating film is formed by an ALCVD method.
For example, Al (CH ₃ ) ₃ And Hf (C ₂ H ₅ ) ₃ Is used to vaporize the raw material solution by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto the substrate heated to 300 ° C. to form the AlHfO film 71b to a thickness of 10 nm. . The AlHfO film 71b may be formed by MOCVD or PVD. Further, the AlHfO film 71b may be formed to a thickness of 1 to 40 nm.
[0088]
HfO as the top insulating film ₂ The film 71c is formed by a CVD method. For example, when the pressure in the chamber of the CVD apparatus is set to 65 Pa and the temperature to 500 ° C., HfO ₂ The film 71c is formed to a thickness of 10 nm. HfO ₂ Although the dielectric constant of the film changes depending on the film forming conditions, the dielectric constant becomes higher than that of the silicon oxide film in the range of the normal film forming conditions, and the HfO film formed under the above conditions is formed. ₂ The film also has a higher dielectric constant than a silicon oxide film formed under normal film forming conditions. HfO ₂ The film 71c may be formed by ALCVD, MOCVD, ALD, MBE, or PVD. In addition, HfO ₂ The film 71c may be formed to a thickness of 1 to 20 nm.
[0089]
Note that the silicon nitride film 71a, the AlHfO film 71b, and the HfO ₂ After forming the film 71c, it is preferable to perform annealing at a temperature of 600 to 1000C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0090]
Since the method for forming the gate electrode is the same as that of the first embodiment, the description is omitted here.
[0091]
In the present embodiment, since the trap insulating film is formed of an AlHfO film having higher charge holding ability than the silicon nitride film, data reliability is improved as compared with the conventional SONOS type memory.
[0092]
In this embodiment, a silicon nitride film having a lower barrier height than a silicon oxide film is used as the tunnel insulating film. As a result, the efficiency of hot electron injection into the trap insulating film is improved as compared with the conventional SONOS memory, and the data write / erase time can be reduced.
[0093]
Further, in the present embodiment, HfO having a higher dielectric constant than the silicon oxide film is used as the top insulating film. ₂ Since the film is used, the electric field from the gate electrode can effectively act on the tunnel insulating film, and as a result, the data write / erase time can be reduced without increasing the driving voltage.
[0094]
(Fifth embodiment)
FIG. 9 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the fifth embodiment of the present invention.
[0095]
In the present embodiment, the tunnel insulating film 81 is formed with the silicon oxide film 81a and La ₂ O ₅ It is configured by laminating the film 81b. Further, the trap insulating film 82 is formed by laminating a silicon nitride film 82a and an alumina film 82b. Further, the top insulating film 83 is made of HfO ₂ A film 83a and an alumina film 83b are laminated.
[0096]
As described above, even when any one or more of the tunnel insulating film 81, the trap insulating film 82, and the top insulating film 83 have a laminated structure of a plurality of layers having different compositions, the first to fourth embodiments The same effect as described above can be obtained.
[0097]
(Sixth embodiment)
FIG. 10 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the sixth embodiment of the present invention.
[0098]
The memory cell of the nonvolatile semiconductor memory of the present embodiment has a gate electrode made of polysilicon formed on a stacked gate insulating film 101 formed on a p-type silicon semiconductor substrate 20 and a stacked gate insulating film 104. 102. The laminated gate insulating film 101 includes a silicon oxide film 101a, HfO ₂ It is formed by laminating a film 101b and a silicon oxide film 101c. Gate electrode 102, silicon oxide film 101a, HfO ₂ The film 101b and the silicon oxide film 101c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively.
[0099]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0100]
The silicon oxide film 101a serving as a tunnel insulating film is formed by a thermal oxidation method.
For example, after a mask of a silicon nitride film is formed on the surface of the silicon semiconductor substrate 20 in a predetermined pattern, the surface of the silicon semiconductor substrate 20 is thermally oxidized at a temperature of 1000 ° C. in a dry atmosphere to have a thickness of about 7 nm. A silicon oxide film 101a is formed. After that, the silicon nitride film is removed. The silicon oxide film 101a may have a thickness of 2 to 10 nm, and may be formed by a method other than the thermal oxidation method.
[0101]
HfO as a trap insulating film ₂ The film 101b is formed by an ALCVD method. For example, Hf (C ₂ H ₅ ) ₃ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and Hf (C ₂ H ₅ ) ₃ And ozone (O ₃ ) And HfO ₂ The film 101b is formed to a thickness of 10 nm. HfO ₂ The film 101b may be formed by a MOCVD method or a PVD method. In addition, HfO ₂ The film 101b may be formed to a thickness of 1 to 40 nm.
[0102]
The silicon oxide film 101c as a top insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is 133 Pa, the substrate temperature is 800 ° C., and the SiH ₄ And N ₂ By reacting with O, a silicon oxide film (HTO: high temperature oxide film) is formed to a thickness of 10 nm. The silicon oxide film 101c may be formed by a CVD method using a TEOS source, an MOCVD method, or a plasma CVD method. Further, the silicon oxide film 101c may be formed to a thickness of 3 to 20 nm.
[0103]
The silicon oxide film 101a, HfO ₂ After forming the film 101b and the silicon oxide film 101c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. It is expected that the quality of each film will be increased by this annealing treatment, and that good electrical characteristics will be obtained. Annealing may be performed each time one of these films 101a, 101b, 101c is formed, or may be performed only once after all three films 101a, 101b, 101c are formed.
[0104]
Since the method for forming the gate electrode 102 is the same as that of the first embodiment, the description is omitted here.
[0105]
In this embodiment, as the trap insulating film, HfO having higher charge holding ability than the silicon nitride film is used. ₂ Uses a membrane. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0106]
Hereinafter, a result of actually manufacturing the nonvolatile semiconductor memory of the present embodiment and examining its characteristics will be described.
[0107]
As shown in FIG. 28A, a silicon oxide film 101a having a thickness of 7 nm as a tunnel insulating film and a HfO film having a thickness of 10 nm as a trap insulating film are formed on a p-type silicon semiconductor substrate 20. ₂ A film 101b and a silicon oxide film 101c having a thickness of 10 nm were sequentially formed as a top insulating film. Then, these silicon oxide films 101a, HfO ₂ A gate electrode 102 made of polysilicon was formed on the laminated gate insulating film 101 having a three-layer structure of the film 101b and the silicon oxide film 101c. Thereafter, an n-type impurity was introduced into the silicon semiconductor substrate 20 using the gate electrode 102 as a mask to form impurity diffusion layers 100a and 100b serving as source / drain. Note that the gate length L of this nonvolatile semiconductor memory (FET) is 0.35 μm.
[0108]
Data was written to the nonvolatile semiconductor memory manufactured as described above with the drain voltage Vd set to 5.5 V and the gate voltage Vg set to 11 V.
[0109]
FIG. 28B is a diagram showing the relationship (writing characteristics) between the writing time and the threshold voltage, with the writing time on the horizontal axis and the threshold voltage Vth on the vertical axis. However, the drain voltage Vd is set to 1.2 V when reading data. From FIG. 28B, it is clear that data is normally written in the nonvolatile semiconductor memory of this embodiment, and the trap insulating film (HfO ₂ It can be seen that charges are held in the film 101b).
[0110]
FIG. 29 shows the time change of the threshold voltage Vth when the charge is injected only to the Bit 1 side in FIG. 28A (data holding characteristic), with the horizontal axis indicating time and the vertical axis indicating threshold voltage. It is a figure which shows the result of having investigated. However, when data is written to Bit 1, the impurity diffusion region 100a is used as a source and the impurity diffusion region 100b is used as a drain.
[0111]
From FIG. 29, it has been confirmed that the nonvolatile memory of the present embodiment reliably holds the written data.
[0112]
FIG. 30 is a diagram showing the erase characteristics when the gate voltage is -7 V and the drain voltage is 5 V, with the erase time taken along the horizontal axis and the threshold voltage Vth taken along the vertical axis. From this figure, it can be seen that the written data can be erased.
[0113]
From these results, it was confirmed that the nonvolatile semiconductor memory of this embodiment had good data writing, holding, and erasing characteristics. Further, the nonvolatile semiconductor memory according to the present embodiment can store different data on the Bit 1 side and the Bit 2 side, respectively, which enables further higher integration of the semiconductor device.
[0114]
(Seventh embodiment)
FIG. 11 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the seventh embodiment of the present invention.
[0115]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 111 formed on the p-type silicon semiconductor substrate 20 and a polysilicon or amorphous silicon formed on the stacked gate insulating film 111. And a gate electrode 112. The laminated gate insulating film 111 is formed by laminating a silicon oxide film 111a, an HfAlO film 111b, and a silicon oxide film 111c in this order from the substrate 20 side. The gate electrode 112, the silicon oxide film 111a, the HfAlO film 111b, and the silicon oxide film 111c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG.
[0116]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0117]
The silicon oxide film 111a serving as a tunnel insulating film is formed by a thermal oxidation method.
For example, after a mask of a silicon nitride film is formed on the surface of the silicon semiconductor substrate 20 in a predetermined pattern, the surface of the silicon semiconductor substrate 20 is thermally oxidized at a temperature of 1000 ° C. in a dry atmosphere to have a thickness of about 7 nm. A silicon oxide film 111a is formed. After that, the silicon nitride film is removed. The silicon oxide film 111a may have a thickness of 2 to 10 nm, and may be formed by a method other than the thermal oxidation method.
[0118]
The HfAlO film 111b serving as a trap insulating film is formed by an ALCVD method. For example, Al (CH ₃ ) ₃ And Hf (C ₂ H ₅ ) ₃ The HfAlO film 111b is formed to a thickness of 10 nm by alternately supplying a source gas and an ozone gas onto a substrate heated to 300 ° C. by vaporizing the source solution by nitrogen bubbling to obtain a source gas. The HfAlO film 111b may be formed by MOCVD or PVD. Further, the HfAlO film 111b may be formed to a thickness of 1 to 40 nm.
[0119]
The silicon oxide film 111c as a top insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is 133 Pa, the substrate temperature is 800 ° C., and the SiH ₄ And N ₂ By reacting with O, a silicon oxide film (HTO) is formed to a thickness of 10 nm. The silicon oxide film 111c may be formed by a CVD method using a TEOS source, an MOCVD method, or a plasma CVD method. The silicon oxide film 111c may be formed to a thickness of 3 to 20 nm.
[0120]
After the silicon oxide film 111a, the HfAlO film 111b, and the silicon oxide film 111c are formed, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. It is expected that the quality of each film will be increased by this annealing treatment, and that good electrical characteristics will be obtained.
[0121]
The method for forming the gate electrode 112 is the same as that in the first embodiment, and a description thereof will not be repeated.
[0122]
In this embodiment mode, an HfAlO film having higher charge holding ability than a silicon nitride film is used as the trap insulating film. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0123]
(Eighth embodiment)
FIG. 12 is a schematic diagram showing the configuration of the stacked gate insulating film of the nonvolatile semiconductor memory according to the eighth embodiment of the present invention.
[0124]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 121 formed on a p-type silicon semiconductor substrate 20 and polysilicon or amorphous silicon formed on the stacked gate insulating film 121. And a gate electrode 122. The laminated gate insulating film 121 includes a silicon nitride film 121a, an HfO ₂ It is formed by laminating a film 121b and a silicon oxide film 121c. Gate electrode 122, silicon nitride film 121a, HfO ₂ The film 121b and the silicon oxide film 121c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively.
[0125]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0126]
The silicon nitride film 121a serving as a tunnel insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is set to 25 Pa, the substrate temperature is set to 780 ° C., and the silicon nitride film 121 a is formed to a thickness of 10 nm on the silicon semiconductor substrate 20. The silicon nitride film 121a may be formed by MOCVD or plasma CVD. Further, the silicon nitride film 121a may be formed to a thickness of 2 to 15 nm.
[0127]
HfO as a trap insulating film ₂ The film 121b is formed by an ALCVD method.
For example, Al (CH ₃ ) ₃ And Hf (C ₂ H ₅ ) ₃ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto a substrate heated to 300 ° C. ₂ The film 121b is formed to a thickness of 10 nm. HfO ₂ The film 121b may be formed by a MOCVD method or a PVD method. In addition, HfO ₂ The film 121b may be formed to a thickness of 1 to 40 nm.
[0128]
The silicon oxide film 121c as a top insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is 133 Pa, the substrate temperature is 800 ° C., and the SiH ₄ And N ₂ By reacting with O, a silicon oxide film (HTO) is formed to a thickness of 10 nm. The silicon oxide film 121c may be formed by a CVD method using a TEOS source, an MOCVD method, or a plasma CVD method. Further, the silicon oxide film 121c may be formed to a thickness of 3 to 20 nm.
[0129]
Note that the silicon nitride film 121a, HfO ₂ After forming the film 121b and the silicon oxide film 121c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0130]
Since the method for forming the gate electrode 122 is the same as that of the first embodiment, the description is omitted here.
[0131]
In this embodiment, HfO having a higher charge holding capacity than a silicon nitride film is used as a trap insulating film. ₂ Uses a membrane. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0132]
In the present invention, a silicon nitride film having a lower barrier height than a silicon oxide film is used as the tunnel insulating film. As a result, the efficiency of hot electron injection into the trap insulating film is improved as compared with the conventional SONOS memory, and the data write / erase time can be reduced.
[0133]
(Ninth embodiment)
FIG. 13 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the ninth embodiment of the present invention.
[0134]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 131 formed on the p-type silicon semiconductor substrate 20 and polysilicon or amorphous silicon formed on the stacked gate insulating film 131. And a gate electrode 132. The laminated gate insulating film 131 includes a silicon oxide film 131a, HfO ₂ It is formed by laminating a film 131b and a silicon nitride film 131c. Gate electrode 132, silicon oxide film 131a, HfO ₂ The film 131b and the silicon nitride film 131c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively.
[0135]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0136]
The silicon oxide film 131a serving as a tunnel insulating film is formed by a thermal oxidation method.
For example, after a mask of a silicon nitride film is formed on the surface of the silicon semiconductor substrate 20 in a predetermined pattern, the surface of the silicon semiconductor substrate 20 is thermally oxidized at a temperature of 1000 ° C. in a dry atmosphere to have a thickness of about 7 nm. A silicon oxide film 131a is formed. After that, the silicon nitride film is removed. The silicon oxide film 131a may be formed to a thickness of 2 to 10 nm, and may be formed by a method other than the thermal oxidation method.
[0137]
HfO as a trap insulating film ₂ The film 131b is formed by an ALCVD method.
For example, Hf (C ₂ H ₅ ) ₃ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto a substrate heated to 300 ° C. ₂ The film 131b is formed to a thickness of 10 nm. HfO ₂ The film 131b may be formed by a MOCVD method or a PVD method. In addition, HfO ₂ The film 131b may be formed to a thickness of 1 to 40 nm.
[0138]
The silicon nitride film 131c as a top insulating film is formed by an LPCVD method.
For example, the pressure in the chamber of the LPCVD apparatus is 25 Pa, the substrate temperature is 780 ° C., and the silicon nitride film 131c is formed to a thickness of 10 nm. The silicon nitride film 131c may be formed by MOCVD or plasma CVD. Further, the silicon nitride film 131c may be formed to a thickness of 2 to 15 nm.
[0139]
Note that the silicon oxide film 131a, HfO ₂ After forming the film 131b and the silicon nitride film 131c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0140]
Since the method of forming the gate electrode 132 is the same as that of the first embodiment, the description is omitted here.
[0141]
In this embodiment, HfO having a higher charge holding capacity than a silicon nitride film is used as a trap insulating film. ₂ Uses a membrane. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0142]
Further, in the present invention, since the silicon nitride film having a higher dielectric constant than the silicon oxide film is used as the top insulating film, the electric field from the gate electrode can effectively act on the tunnel insulating film. In addition, the data write / erase time can be reduced without increasing the drive voltage.
[0143]
(Tenth embodiment)
FIG. 14 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the tenth embodiment of the present invention.
[0144]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 141 formed on the p-type silicon semiconductor substrate 20 and polysilicon or amorphous silicon formed on the stacked gate insulating film 141. And a gate electrode 142. The laminated gate insulating film 141 includes a silicon nitride film 141a, an HfAlO film 141b, and a HfO ₂ It is formed by laminating the films 141c. Gate electrode 142, silicon nitride film 141a, HfAlO film 141b and HfO ₂ The film 141c corresponds to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG.
[0145]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0146]
The silicon nitride film 141a serving as a tunnel insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is set to 25 Pa, the substrate temperature is set to 780 ° C., and the silicon nitride film 141 a is formed to a thickness of 10 nm on the silicon semiconductor substrate 20. The silicon nitride film 141a may be formed by MOCVD or plasma CVD. Further, the silicon nitride film 141a may be formed to a thickness of 2 to 15 nm.
[0147]
The HfAlO film 141b serving as a trap insulating film is formed by an ALCVD method. For example, Al (CH ₃ ) ₃ And Hf (C ₂ H ₅ ) ₃ The HfAlO film 141b is formed to a thickness of 10 nm by alternately supplying the source gas and the ozone gas onto the substrate heated at 300 ° C. The HfAlO film 141b may be formed by MOCVD or PVD. Further, the HfAlO film 141b may be formed to a thickness of 1 to 40 nm.
[0148]
HfO as the top insulating film ₂ The film 141c is formed by an ALCVD method. For example, Hf (C ₂ H ₅ ) ₃ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto a substrate heated to 300 ° C. ₂ The film 141c is formed to a thickness of 10 nm. HfO ₂ The film 141c may be formed by a MOCVD method or a PVD method. In addition, HfO ₂ The film 141c may be formed to a thickness of 1 to 40 nm.
[0149]
Since the method for forming the gate electrode 142 is the same as that of the first embodiment, the description is omitted here.
[0150]
Note that the silicon nitride film 141a, the HfAlO film 141b, and the HfO ₂ After forming the film 141c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0151]
In the present embodiment, an HfAlO film having higher charge holding ability than a silicon nitride film is used as a trap insulating film. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0152]
In the present invention, a silicon nitride film having a lower barrier height than a silicon oxide film is used as the tunnel insulating film. As a result, the efficiency of hot electron injection into the trap insulating film is improved as compared with the conventional SONOS memory, and the data write / erase time can be reduced.
[0153]
Further, in the present invention, HfO having a higher dielectric constant than a silicon oxide film is used as a top insulating film. ₂ Since the film is used, the electric field from the gate electrode can be effectively applied to the tunnel insulating film, and as a result, the data write / erase time can be reduced without increasing the drive voltage.
[0154]
In the sixth to tenth embodiments, as shown in FIG. 9, at least one of the tunnel insulating film, the trap insulating film, and the top insulating film may have a multilayer structure.
[0155]
(Eleventh embodiment)
FIG. 15 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the eleventh embodiment of the present invention.
[0156]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 151 formed on p-type silicon semiconductor substrate 20 and polysilicon or amorphous silicon formed on stacked gate insulating film 151. And a gate electrode 152. The laminated gate insulating film 151 includes a silicon oxide film 151a, a ZrO ₂ It is formed by laminating a film 151b and a silicon oxide film 151c. Gate electrode 152, silicon oxide film 151a, ZrO ₂ The film 151b and the silicon oxide film 151c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively.
[0157]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0158]
The silicon oxide film 151a serving as a tunnel insulating film is formed by a thermal oxidation method.
For example, after a mask of a silicon nitride film is formed on the surface of the silicon semiconductor substrate 20 in a predetermined pattern, the surface of the silicon semiconductor substrate 20 is thermally oxidized at a temperature of 1000 ° C. in a dry atmosphere to have a thickness of about 7 nm. A silicon oxide film 151a is formed. After that, the silicon nitride film is removed. The silicon oxide film 151a may have a thickness of 2 to 10 nm, and may be formed by a method other than the thermal oxidation method.
[0159]
ZrO as a trap insulating film ₂ The film 151b is formed by an ALCVD method.
For example, Zr (C ₂ H ₅ ) ₄ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto the substrate heated to 300 ° C. ₂ The film 151b is formed to a thickness of 10 nm. ZrO ₂ The film 151b may be formed by MOCVD or PVD. Also, ZrO ₂ The film 151b may be formed to a thickness of 1 to 40 nm.
[0160]
The silicon oxide film 151c as a top insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is 133 Pa, the substrate temperature is 800 ° C., and the SiH ₄ And N ₂ By reacting with O, a silicon oxide film (HTO) is formed to a thickness of 10 nm. The silicon oxide film 151c may be formed by a CVD method using a TEOS source, an MOCVD method, or a plasma CVD method. Further, the silicon oxide film 151c may be formed to a thickness of 3 to 20 nm.
[0161]
Note that the silicon oxide film 151a, ZrO ₂ After forming the film 151b and the silicon oxide film 151c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. It is expected that the quality of each film will be increased by this annealing treatment, and that good electrical characteristics will be obtained.
[0162]
Since the method for forming the gate electrode 152 is the same as that of the first embodiment, the description is omitted here.
[0163]
In this embodiment, as the trap insulating film, ZrO having higher charge holding ability than the silicon nitride film is used. ₂ Uses a membrane. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0164]
(Twelfth embodiment)
FIG. 16 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a twelfth embodiment of the present invention.
[0165]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 161 formed on the p-type silicon semiconductor substrate 20 and a polysilicon or amorphous silicon formed on the stacked gate insulating film 161. And a gate electrode 162. The laminated gate insulating film 161 is formed by sequentially laminating a silicon oxide film 161a, a ZrAlO film 161b, and a silicon oxide film 161c from the substrate 20 side. The gate electrode 162, the silicon oxide film 161a, the ZrAlO film 161b, and the silicon oxide film 161c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively.
[0166]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0167]
The silicon oxide film 161a serving as a tunnel insulating film is formed by a thermal oxidation method.
For example, after a mask of a silicon nitride film is formed on the surface of the silicon semiconductor substrate 20 in a predetermined pattern, the surface of the silicon semiconductor substrate 20 is thermally oxidized at a temperature of 1000 ° C. in a dry atmosphere to have a thickness of about 7 nm. A silicon oxide film 41a is formed.
After that, the silicon nitride film is removed. The silicon oxide film 161a may have a thickness of 2 to 10 nm, and may be formed by a method other than the thermal oxidation method.
[0168]
The ZrAlO film 161b serving as a trap insulating film is formed by an ALCVD method. For example, Al (CH ₃ ) ₃ And Zr (C ₂ H ₅ ) ₄ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto the substrate heated to 300 ° C. to form the ZrAlO film 161b to a thickness of 10 nm. The ZrAlO film 161b may be formed by MOCVD or PVD. Further, the ZrAlO film 161b may be formed to a thickness of 1 to 40 nm.
[0169]
The silicon oxide film 161c as a top insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is 133 Pa, the substrate temperature is 800 ° C., and the SiH ₄ And N ₂ By reacting with O, a silicon oxide film (HTO) is formed to a thickness of 10 nm. The silicon oxide film 161c may be formed by a CVD method using a TEOS source, an MOCVD method, or a plasma CVD method. Further, the silicon oxide film 161c may be formed to a thickness of 3 to 20 nm.
[0170]
After the silicon oxide film 161a, the ZrAlO film 161b, and the silicon oxide film 161c are formed, it is preferable to perform annealing at a temperature of 600 to 1000C. It is expected that the quality of each film will be increased by this annealing treatment, and that good electrical characteristics will be obtained.
[0171]
Since the method for forming the gate electrode 162 is the same as that of the first embodiment, the description is omitted here.
[0172]
In this embodiment, a ZrAlO film having a higher charge holding ability than a silicon nitride film is used as the trap insulating film. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0173]
(Thirteenth embodiment)
FIG. 17 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the thirteenth embodiment of the present invention.
[0174]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 171 formed on the p-type silicon semiconductor substrate 20 and polysilicon or amorphous silicon formed on the stacked gate insulating film 171. And a gate electrode 172. The laminated gate insulating film 171 is composed of a silicon nitride film 171a, a ZrO ₂ It is formed by laminating a film 171b and a silicon oxide film 171c. Gate electrode 172, silicon nitride film 171a, ZrO ₂ The film 171b and the silicon oxide film 171c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively.
[0175]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0176]
The silicon nitride film 171a serving as a tunnel insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is set to 25 Pa, the substrate temperature is set to 780 ° C., and the silicon nitride film 171 a is formed to a thickness of 10 nm on the silicon semiconductor substrate 20. The silicon nitride film 171a may be formed by MOCVD or plasma CVD. Further, the silicon nitride film 171a may be formed to a thickness of 2 to 15 nm.
[0177]
ZrO as a trap insulating film ₂ The film 171b is formed by an ALCVD method.
For example, Zr (C ₂ H ₅ ) ₄ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto the substrate heated to 300 ° C. ₂ The film 171b is formed to a thickness of 10 nm. ZrO ₂ The film 171b may be formed by a MOCVD method or a PVD method. Also, ZrO ₂ The film 171b may be formed to a thickness of 1 to 40 nm.
[0178]
The silicon oxide film 171c as a top insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is 133 Pa, the substrate temperature is 800 ° C., and the SiH ₄ And N ₂ By reacting with O, a silicon oxide film (HTO) is formed to a thickness of 10 nm. The silicon oxide film 171c may be formed by a CVD method using a TEOS source, an MOCVD method, or a plasma CVD method. Further, the silicon oxide film 171c may be formed to a thickness of 3 to 20 nm.
[0179]
Note that the silicon nitride film 171a, ZrO ₂ After forming the film 171b and the silicon oxide film 171c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0180]
Since the method for forming the gate electrode 172 is the same as that of the first embodiment, the description is omitted here.
[0181]
In the present embodiment, as the trap insulating film, ZrO having higher charge holding ability than the silicon nitride film is used. ₂ Uses a membrane. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0182]
In the present invention, a silicon nitride film having a lower barrier height than a silicon oxide film is used as the tunnel insulating film. As a result, the efficiency of hot electron injection into the trap insulating film is improved as compared with the conventional SONOS memory, and the data write / erase time can be reduced.
[0183]
(14th embodiment)
FIG. 18 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a fourteenth embodiment of the present invention.
[0184]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 181 formed on the p-type silicon semiconductor substrate 20 and a polysilicon or amorphous silicon formed on the stacked gate insulating film 181. And a gate electrode 182. The laminated gate insulating film 181 is composed of a silicon oxide film 181a, a ZrO ₂ It is formed by laminating a film 181b and a silicon nitride film 181c. Gate electrode 182, silicon oxide film 181a, ZrO ₂ The film 181b and the silicon nitride film 181c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG.
[0185]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0186]
The silicon oxide film 181a serving as a tunnel insulating film is formed by a thermal oxidation method.
For example, after a mask of a silicon nitride film is formed on the surface of the silicon semiconductor substrate 20 in a predetermined pattern, the surface of the silicon semiconductor substrate 20 is thermally oxidized at a temperature of 1000 ° C. in a dry atmosphere to have a thickness of about 7 nm. A silicon oxide film 181a is formed. After that, the silicon nitride film is removed. The silicon oxide film 181a may be formed to a thickness of 2 to 10 nm, and may be formed by a method other than the thermal oxidation method.
[0187]
ZrO as a trap insulating film ₂ The film 181b is formed by an ALCVD method.
For example, Zr (C ₂ H ₅ ) ₄ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto the substrate heated to 300 ° C. ₂ The film 181b is formed to a thickness of 10 nm. ZrO ₂ The film 181b may be formed by a MOCVD method or a PVD method. Also, ZrO ₂ The film 181b may be formed to a thickness of 1 to 40 nm.
[0188]
The silicon nitride film 181c as a top insulating film is formed by an LPCVD method.
For example, the pressure in the chamber of the LPCVD apparatus is set to 25 Pa, the substrate temperature is set to 780 ° C., and the silicon nitride film 181c is formed to a thickness of 10 nm. The silicon nitride film 181c may be formed by MOCVD or plasma CVD. Further, the silicon nitride film 181c may be formed to a thickness of 2 to 15 nm.
[0189]
Note that the silicon oxide film 181a, ZrO ₂ After forming the film 181b and the silicon nitride film 181c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0190]
The method of forming the gate electrode 182 is the same as that of the first embodiment, and thus the description is omitted here.
[0191]
In the present embodiment, as the trap insulating film, ZrO having higher charge holding ability than the silicon nitride film is used. ₂ Uses a membrane. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0192]
Further, in the present invention, since the silicon nitride film having a higher dielectric constant than the silicon oxide film is used as the top insulating film, the electric field from the gate electrode can effectively act on the tunnel insulating film. In addition, the data write / erase time can be reduced without increasing the drive voltage.
[0193]
(Fifteenth embodiment)
FIG. 19 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the fifteenth embodiment of the present invention.
[0194]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 191 formed on the p-type silicon semiconductor substrate 20 and polysilicon or amorphous silicon formed on the stacked gate insulating film 191. And a gate electrode 192. The laminated gate insulating film 191 includes a silicon nitride film 191a, a ZrAlO film 191b, and a HfO ₂ It is formed by laminating the films 191c. Gate electrode 192, silicon nitride film 191a, ZrAlO film 191b and HfO ₂ The film 191c corresponds to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG.
[0195]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0196]
The silicon nitride film 191a serving as a tunnel insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is set to 25 Pa, the substrate temperature is set to 780 ° C., and a silicon nitride film 191 a is formed to a thickness of 10 nm on the silicon semiconductor substrate 20. The silicon nitride film 191a may be formed by MOCVD or plasma CVD. The silicon nitride film 191a may be formed to a thickness of 2 to 15 nm.
[0197]
The ZrAlO film 191b serving as a trap insulating film is formed by an ALCVD method. For example, Al (CH ₃ ) ₃ And Zr (C ₂ H ₅ ) ₄ Then, the raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto the substrate heated to 300 ° C. to form the ZrAlO film 191b to a thickness of 10 nm. The ZrAlO film 191b may be formed by MOCVD or PVD. Further, the ZrAlO film 191b may be formed to a thickness of 1 to 40 nm.
[0198]
HfO as the top insulating film ₂ The film 191c is formed by an ALCVD method. For example, Hf (C ₂ H ₅ ) ₃ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto a substrate heated to 300 ° C. ₂ The film 191c is formed to a thickness of 10 nm. HfO ₂ The film 191c may be formed by a MOCVD method or a PVD method. In addition, HfO ₂ The film 191c may be formed to a thickness of 1 to 40 nm.
[0199]
Since the method for forming the gate electrode 192 is the same as that of the first embodiment, the description is omitted here.
[0200]
Note that the silicon nitride film 191a, the ZrAlO film 191b, and the HfO ₂ After forming the film 191c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0201]
In the present embodiment, a ZrAlO film having higher charge holding ability than a silicon nitride film is used as a trap insulating film. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0202]
In the present invention, a silicon nitride film having a lower barrier height than a silicon oxide film is used as the tunnel insulating film. As a result, the efficiency of hot electron injection into the trap insulating film is improved as compared with the conventional SONOS memory, and the data write / erase time can be reduced.
[0203]
Further, in the present invention, HfO having a higher dielectric constant than a silicon oxide film is used as a top insulating film. ₂ Since the film is used, the electric field from the gate electrode can be effectively applied to the tunnel insulating film, and as a result, the data write / erase time can be reduced without increasing the drive voltage.
[0204]
In the first to fifteenth embodiments, as shown in FIG. 9, at least one of the tunnel insulating film, the trap insulating film, and the top insulating film may have a multilayer structure.
[0205]
(Sixteenth embodiment)
FIG. 20 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the sixteenth embodiment of the present invention.
[0206]
The memory cell of the nonvolatile semiconductor memory of this embodiment includes a stacked gate insulating film 201 formed on the p-type silicon semiconductor substrate 20 and a polysilicon or amorphous silicon formed on the stacked gate insulating film 201. And a gate electrode 202. The laminated gate insulating film 201 includes a silicon oxide film 201a, La ₂ O ₃ It is formed by laminating a film 201b and a silicon oxide film 201c. Gate electrode 2022, silicon oxide film 201a, La ₂ O ₃ The film 201b and the silicon oxide film 201c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG.
[0207]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0208]
The silicon oxide film 201a serving as a tunnel insulating film is formed by a thermal oxidation method.
For example, after a mask of a silicon nitride film is formed on the surface of the silicon semiconductor substrate 20 in a predetermined pattern, the surface of the silicon semiconductor substrate 20 is thermally oxidized at a temperature of 1000 ° C. in a dry atmosphere to have a thickness of about 7 nm. A silicon oxide film 201a is formed. After that, the silicon nitride film is removed. The silicon oxide film 201a may have a thickness of 2 to 10 nm, and may be formed by a method other than the thermal oxidation method.
[0209]
La which is a trap insulating film ₂ O ₃ The film 201b is formed by an ALCVD method. For example, La (C ₂ H ₅ ) ₃ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied on the substrate heated to 300 ° C. ₂ O ₃ The film 201b is formed to a thickness of 10 nm. La ₂ O ₃ The film 201b may be formed by a MOCVD method or a PVD method. Also, La ₂ O ₃ The film 201b may be formed to a thickness of 1 to 40 nm.
[0210]
The silicon oxide film 201c as a top insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is 133 Pa, the substrate temperature is 800 ° C., and the SiH ₄ And N ₂ By reacting with O, a silicon oxide film (HTO) is formed to a thickness of 10 nm. The silicon oxide film 201c may be formed by a CVD method using a TEOS source, an MOCVD method, or a plasma CVD method. The silicon oxide film 201c may be formed to a thickness of 3 to 20 nm.
[0211]
The silicon oxide film 201a, La ₂ O ₃ After forming the film 201b and the silicon oxide film 201c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. It is expected that the quality of each film will be increased by this annealing treatment, and that good electrical characteristics will be obtained.
[0212]
Since the method for forming the gate electrode 202 is the same as that of the first embodiment, the description is omitted here.
[0213]
In this embodiment, as the trap insulating film, La having higher charge holding ability than the silicon nitride film is used. ₂ O ₃ Uses a membrane. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0214]
(Seventeenth embodiment)
FIG. 21 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the seventeenth embodiment of the present invention.
[0215]
The memory cell of the nonvolatile semiconductor memory of this embodiment includes a stacked gate insulating film 211 formed on the p-type silicon semiconductor substrate 20 and a polysilicon or amorphous silicon formed on the stacked gate insulating film 211. And a gate electrode 212. The laminated gate insulating film 211 is formed by laminating a silicon oxide film 211a, a LaAlO film 211b, and a silicon oxide film 211c in order from the substrate 20 side. The gate electrode 212, the silicon oxide film 211a, the LaAlO film 211b, and the silicon oxide film 211c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively.
[0216]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0217]
The silicon oxide film 211a serving as a tunnel insulating film is formed by a thermal oxidation method.
For example, after a mask of a silicon nitride film is formed on the surface of the silicon semiconductor substrate 20 in a predetermined pattern, the surface of the silicon semiconductor substrate 20 is thermally oxidized at a temperature of 1000 ° C. in a dry atmosphere to have a thickness of about 7 nm. A silicon oxide film 211a is formed. After that, the silicon nitride film is removed. The silicon oxide film 211a may have a thickness of 2 to 10 nm, and may be formed by a method other than the thermal oxidation method.
[0218]
The LaAlO film 211b serving as a trap insulating film is formed by an ALCVD method. For example, Al (CH ₃ ) ₃ And La (C ₂ H ₅ ) ₃ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied on the substrate heated to 300 ° C. to form the LaAlO film 211b to a thickness of 10 nm. The LaAlO film 211b may be formed by MOCVD or PVD. Further, the LaAlO film 211b may be formed to a thickness of 1 to 40 nm.
[0219]
The silicon oxide film 211c as a top insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is 133 Pa, the substrate temperature is 800 ° C., and the SiH ₄ And N ₂ By reacting with O, a silicon oxide film (HTO) is formed to a thickness of 10 nm. The silicon oxide film 211c may be formed by a CVD method using a TEOS source, an MOCVD method, or a plasma CVD method. Further, the silicon oxide film 211c may be formed to a thickness of 3 to 20 nm.
[0220]
After the silicon oxide film 211a, the LaAlO film 211b, and the silicon oxide film 211c are formed, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. It is expected that the quality of each film will be increased by this annealing treatment, and that good electrical characteristics will be obtained.
[0221]
Since the method for forming the gate electrode 212 is the same as that of the first embodiment, the description is omitted here.
[0222]
In this embodiment, a LaAlO film having a higher charge holding ability than a silicon nitride film is used as the trap insulating film. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0223]
(Eighteenth Embodiment)
FIG. 22 is a schematic diagram showing the configuration of the stacked gate insulating film of the nonvolatile semiconductor memory according to the eighteenth embodiment of the present invention.
[0224]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 221 formed on the p-type silicon semiconductor substrate 20 and polysilicon or amorphous silicon formed on the stacked gate insulating film 221. And a gate electrode 222. The laminated gate insulating film 221 is composed of a silicon nitride film 221a, La ₂ O ₃ It is formed by laminating a film 221b and a silicon oxide film 221c. Gate electrode 222, silicon nitride film 221a, La ₂ O ₃ The film 221b and the silicon oxide film 221c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively.
[0225]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0226]
The silicon nitride film 221a serving as a tunnel insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is set to 25 Pa, the substrate temperature is set to 780 ° C., and the silicon nitride film 221 a is formed to a thickness of 10 nm on the silicon semiconductor substrate 20. The silicon nitride film 221a may be formed by MOCVD or plasma CVD. Further, the silicon nitride film 221a may be formed to a thickness of 2 to 15 nm.
[0227]
La which is a trap insulating film ₂ O ₃ The film 221b is formed by an ALCVD method. For example, La (C ₂ H ₅ ) ₄ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto the substrate heated to 300 ° C. ₂ O ₃ The film 221b is formed to a thickness of 10 nm. La ₂ O ₃ The film 221b may be formed by MOCVD or PVD.
Also, La ₂ O ₃ The film 221b may be formed to a thickness of 1 to 40 nm.
[0228]
The silicon oxide film 221c as the top insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is 133 Pa, the substrate temperature is 800 ° C., and the SiH ₄ And N ₂ By reacting with O, a silicon oxide film (HTO) is formed to a thickness of 10 nm. The silicon oxide film 221c may be formed by a CVD method using a TEOS source, an MOCVD method, or a plasma CVD method. Further, the silicon oxide film 221c may be formed to a thickness of 3 to 20 nm.
[0229]
Note that the silicon nitride film 221a, La ₂ O ₃ After forming the film 221b and the silicon oxide film 221c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0230]
Since the method for forming the gate electrode 222 is the same as that of the first embodiment, the description is omitted here.
[0231]
In the present embodiment, as the trap insulating film, La having higher charge holding ability than the silicon nitride film is used. ₂ O ₃ Uses a membrane. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0232]
In the present invention, a silicon nitride film having a lower barrier height than a silicon oxide film is used as the tunnel insulating film. As a result, the efficiency of hot electron injection into the trap insulating film is improved as compared with the conventional SONOS memory, and the data write / erase time can be reduced.
[0233]
(Nineteenth Embodiment)
FIG. 23 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the nineteenth embodiment of the present invention.
[0234]
The memory cell of the nonvolatile semiconductor memory of this embodiment includes a stacked gate insulating film 231 formed on the p-type silicon semiconductor substrate 20 and polysilicon or amorphous silicon formed on the stacked gate insulating film 231. And a gate electrode 232. The laminated gate insulating film 231 is composed of a silicon oxide film 231a, La ₂ O ₃ It is formed by laminating a film 231b and a silicon nitride film 231c. Gate electrode 232, silicon oxide film 231a, La ₂ O ₃ The film 231b and the silicon nitride film 231c correspond to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG. 3, respectively.
[0235]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0236]
The silicon oxide film 231a serving as a tunnel insulating film is formed by a thermal oxidation method.
For example, after a mask of a silicon nitride film is formed on the surface of the silicon semiconductor substrate 20 in a predetermined pattern, the surface of the silicon semiconductor substrate 20 is thermally oxidized at a temperature of 1000 ° C. in a dry atmosphere to have a thickness of about 7 nm. A silicon oxide film 231a is formed. After that, the silicon nitride film is removed. The silicon oxide film 231a may be formed to a thickness of 2 to 10 nm, and may be formed by a method other than the thermal oxidation method.
[0237]
La which is a trap insulating film ₂ O ₃ The film 231b is formed by an ALCVD method. For example, La (C ₂ H ₅ ) ₃ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto the substrate heated to 300 ° C. ₂ O ₃ The film 231b is formed to a thickness of 10 nm. La ₂ O ₃ The film 231b may be formed by a MOCVD method or a PVD method.
Also, La ₂ O ₃ The film 231b may be formed to a thickness of 1 to 40 nm.
[0238]
The silicon nitride film 231c as a top insulating film is formed by an LPCVD method.
For example, the pressure in the chamber of the LPCVD apparatus is set to 25 Pa, the substrate temperature is set to 780 ° C., and the silicon nitride film 231c is formed to a thickness of 10 nm. The silicon nitride film 231c may be formed by MOCVD or plasma CVD. Further, the silicon nitride film 231c may be formed to a thickness of 2 to 15 nm.
[0239]
Note that the silicon oxide film 231a, La ₂ O ₃ After forming the film 231b and the silicon nitride film 231c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0240]
Since the method for forming the gate electrode 232 is the same as that of the first embodiment, the description is omitted here.
[0241]
In the present embodiment, as the trap insulating film, La having higher charge holding ability than the silicon nitride film is used. ₂ O ₃ Uses a membrane. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0242]
Further, in the present invention, since the silicon nitride film having a higher dielectric constant than the silicon oxide film is used as the top insulating film, the electric field from the gate electrode can effectively act on the tunnel insulating film. In addition, the data write / erase time can be reduced without increasing the drive voltage.
[0243]
(Twentieth embodiment)
FIG. 24 is a schematic diagram showing the configuration of the laminated gate insulating film of the nonvolatile semiconductor memory according to the twentieth embodiment of the present invention.
[0244]
The memory cell of the nonvolatile semiconductor memory according to the present embodiment includes a stacked gate insulating film 241 formed on the p-type silicon semiconductor substrate 20 and polysilicon or amorphous silicon formed on the stacked gate insulating film 241. And a gate electrode 242. The laminated gate insulating film 241 includes a silicon nitride film 241a, a LaAlO film 241b, and a HfO ₂ It is formed by laminating the films 241c. Gate electrode 242, silicon nitride film 241a, LaAlO film 241b and HfO ₂ The film 241c corresponds to the word line 24, the tunnel insulating film 23a, the trap insulating film 23b, and the top insulating film 23c in FIG.
[0245]
Hereinafter, a method for manufacturing the nonvolatile semiconductor memory according to the present embodiment will be described.
[0246]
The silicon nitride film 241a serving as a tunnel insulating film is formed by an LPCVD method. For example, the pressure in the chamber of the LPCVD apparatus is set to 25 Pa, the substrate temperature is set to 780 ° C., and the silicon nitride film 241 a is formed to a thickness of 10 nm on the silicon semiconductor substrate 20. The silicon nitride film 241a may be formed by MOCVD or plasma CVD. Further, the silicon nitride film 241a may be formed to a thickness of 2 to 15 nm.
[0247]
The LaAlO film 241b serving as a trap insulating film is formed by an ALCVD method. For example, Al (CH ₃ ) ₃ And La (C ₂ H ₅ ) ₃ Then, the raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto the substrate heated to 300 ° C. to form the LaAlO film 241b to a thickness of 10 nm. The LaAlO film 241b may be formed by MOCVD or PVD. Further, the LaAlO film 241b may be formed to a thickness of 1 to 40 nm.
[0248]
HfO as the top insulating film ₂ The film 241c is formed by an ALCVD method. For example, Hf (C ₂ H ₅ ) ₃ The raw material solution is vaporized by nitrogen bubbling to obtain a raw material gas, and the raw material gas and the ozone gas are alternately supplied onto a substrate heated to 300 ° C. ₂ The film 241c is formed to a thickness of 10 nm. HfO ₂ The film 241c may be formed by a MOCVD method or a PVD method. In addition, HfO ₂ The film 241c may be formed to a thickness of 1 to 40 nm.
[0249]
Since the method for forming the gate electrode 242 is the same as that of the first embodiment, the description is omitted here.
[0250]
Note that the silicon nitride film 241a, the LaAlO film 241b, and the HfO ₂ After forming the film 241c, it is preferable to perform annealing at a temperature of 600 to 1000 ° C. By this annealing treatment, it is expected that the film quality of each film becomes dense and good electrical characteristics are obtained.
[0251]
In the present embodiment, a LaAlO film having higher charge holding ability than a silicon nitride film is used as a trap insulating film. Thereby, data reliability is improved as compared with the conventional SONOS type memory.
[0252]
In the present invention, a silicon nitride film having a lower barrier height than a silicon oxide film is used as the tunnel insulating film. As a result, the efficiency of hot electron injection into the trap insulating film is improved as compared with the conventional SONOS memory, and the data write / erase time can be reduced.
[0253]
Further, in the present invention, HfO having a higher dielectric constant than a silicon oxide film is used as a top insulating film. ₂ Since the film is used, the electric field from the gate electrode can be effectively applied to the tunnel insulating film, and as a result, the data write / erase time can be reduced without increasing the drive voltage.
[0254]
In the sixteenth to twentieth embodiments, at least one of the tunnel insulating film, the trap insulating film, and the top insulating film may have a multilayer structure as shown in FIG.
[0255]
In the sixteenth to twentieth embodiments, the case where the lanthanoid (Ln) is La (lanthanum) is described, but the same effect can be obtained by using other lanthanoid elements.
[0256]
Further, in each of the first to twentieth embodiments, the case where the present invention is applied to an NROM in which a word line and a source / drain are formed in a direction orthogonal to each other has been described. The structure can be applied to a single-gate nonvolatile semiconductor memory having the structure described above, and can be applied to, for example, a single-gate nonvolatile semiconductor memory having a structure as shown in FIG.
[0257]
(Supplementary Note 1) A semiconductor substrate, a pair of impurity diffusion regions formed in the semiconductor substrate, a tunnel insulating film formed on a region between the pair of impurity diffusion regions, ₂ O ₃ , HfO ₂ , ZrO ₂ And Ln ₂ O ₃ (Where Ln is a lanthanoid element) a trap insulating film formed on the tunnel insulating film by at least one oxide selected from the group consisting of: a top insulating film formed on the trap insulating film; And a gate electrode formed on the top insulating film.
[0258]
(Supplementary Note 2) A semiconductor substrate, a pair of impurity diffusion regions formed in the semiconductor substrate, a tunnel insulating film formed on a region between the pair of impurity diffusion regions, Al, Hf, Zr, and Ln ( However, Ln is a trap insulating film formed on the tunnel insulating film by an oxide mainly containing one element selected from the group consisting of lanthanoid elements, and formed on the trap insulating film. A nonvolatile semiconductor memory, comprising: a top insulating film; and a gate electrode formed on the top insulating film.
[0259]
(Supplementary note 3) The nonvolatile semiconductor memory according to claim 1 or 2, wherein a barrier height of the tunnel insulating film is lower than a barrier height of a silicon oxide film having the same thickness.
[0260]
(Supplementary Note 4) The nonvolatile semiconductor memory according to claim 1 or 2, wherein the relative permittivity of the top insulating film is higher than the relative permittivity of the silicon oxide film.
[0261]
(Supplementary Note 5) The nonvolatile semiconductor device according to claim 2, wherein the trap insulating film is formed of at least one compound selected from the group consisting of AlHfO, AlZrO, AlTaO, AlTiO, and ZrAlO. memory.
[0262]
(Supplementary Note 6) The trap insulating film is made of Al ₂ O ₃ 3. The nonvolatile semiconductor memory according to claim 2, wherein the nonvolatile semiconductor memory is made of a silicate or aluminate of at least one compound selected from the group consisting of AlHfO, AlZrO, AlTaO, AlTiO and ZrAlO.
[0263]
(Supplementary Note 7) The tunnel insulating film is made of SiN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , SrTiO ₂ , BaSrTiO ₃ , TiO ₂ , AlN, Ta ₂ O ₅ 3. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory is formed of at least one compound selected from the group consisting of TaN, HfAlO, and ZrAlO.
[0264]
(Supplementary Note 8) The tunnel insulating film is made of SiN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , SrTiO ₂ , BaSrTiO ₃ , TiO ₂ , AlN, Ta ₂ O ₅ 3. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory is formed of a silicate or an aluminate of at least one compound selected from the group consisting of TaN, HfAlO, and ZrAlO. 4.
[0265]
(Supplementary Note 9) The top insulating film is made of SiN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , SrTiO ₂ , BaSrTiO ₃ , TiO ₂ , AlN, Ta ₂ O ₅ 3. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory is formed of at least one compound selected from the group consisting of TaN, HfAlO, and ZrAlO. 4.
[0266]
(Supplementary Note 10) The top insulating film is made of SiN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , SrTiO ₂ , BaSrTiO ₃ , TiO ₂ , AlN, Ta ₂ O ₅ 3. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory is formed of a silicate or an aluminate of at least one compound selected from the group consisting of TaN, HfAlO, and ZrAlO. 4.
[0267]
(Supplementary Note 11) The nonvolatile semiconductor memory according to claim 1 or 2, wherein the tunnel insulating film is constituted by a plurality of films having different compositions.
[0268]
(Supplementary Note 12) The nonvolatile semiconductor memory according to claim 1 or 2, wherein the trap insulating film is constituted by a plurality of films having different compositions.
[0269]
(Supplementary Note 13) The nonvolatile semiconductor memory according to claim 1 or 2, wherein the top insulating film is constituted by a plurality of films having different compositions.
[0270]
【The invention's effect】
As described above, according to the present invention, the trap insulating film is made of Al ₂ O ₃ , HfO ₂ , ZrO ₂ And Ln ₂ O ₃ Of a single-gate nonvolatile semiconductor memory because it is formed of any one of the above oxides or an oxide containing any one of Al, Hf, Zr and Ln as a main component. Data retention ability is improved.
[0271]
Further, by forming the tunnel insulating film from a material having a lower barrier height than the silicon oxide film, the efficiency of hot electron injection into the trap insulating film is improved, and the data read / write time is shortened.
[0272]
Furthermore, when the top insulating film is formed of a material having a higher relative dielectric constant than the silicon oxide film, the electric field from the gate electrode can effectively act on the tunnel insulating film, and as a result, without increasing the driving voltage Data write / erase time can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing a memory cell structure of a conventional SONOS type memory.
FIG. 2 is a plan view of a nonvolatile semiconductor memory to which the present invention is applied;
3 (a) is a cross-sectional view taken along line II of FIG. 2, FIG. 3 (b) is a cross-sectional view taken along line II-II of FIG. 2, and FIG. 3 (c) is a line III-III of FIG. It is sectional drawing by a line.
FIG. 4 is a block diagram showing an example of a circuit configuration of a nonvolatile semiconductor memory of the present invention.
FIG. 5 is a schematic diagram showing a configuration of a laminated gate insulating film of the nonvolatile semiconductor memory according to the first embodiment of the present invention.
FIG. 6 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a second embodiment of the present invention.
FIG. 7 is a schematic diagram illustrating a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a third embodiment of the present invention.
FIG. 8 is a schematic diagram illustrating a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a fourth embodiment of the present invention.
FIG. 9 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a fifth embodiment of the present invention.
FIG. 10 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a sixth embodiment of the present invention.
FIG. 11 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a seventh embodiment of the present invention.
FIG. 12 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to an eighth embodiment of the present invention.
FIG. 13 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a ninth embodiment of the present invention.
FIG. 14 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a tenth embodiment of the present invention.
FIG. 15 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to an eleventh embodiment of the present invention.
FIG. 16 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a twelfth embodiment of the present invention.
FIG. 17 is a schematic view showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a thirteenth embodiment of the present invention.
FIG. 18 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a fourteenth embodiment of the present invention.
FIG. 19 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a fifteenth embodiment of the present invention.
FIG. 20 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a sixteenth embodiment of the present invention.
FIG. 21 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a seventeenth embodiment of the present invention.
FIG. 22 is a schematic diagram showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to an eighteenth embodiment of the present invention.
FIG. 23 is a schematic view showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a nineteenth embodiment of the present invention.
FIG. 24 is a schematic view showing a configuration of a laminated gate insulating film of a nonvolatile semiconductor memory according to a twentieth embodiment of the present invention.
FIG. 25A is a schematic diagram illustrating a nonvolatile semiconductor memory according to the first embodiment, and FIG. 25B is a diagram illustrating write characteristics of the nonvolatile semiconductor memory.
FIG. 26A is a diagram showing a result of examining data retention characteristics when charges are injected only into the Bit1 side of the nonvolatile semiconductor memory according to the first embodiment, and FIG. 26B is the same. FIG. 9 is a diagram showing a result of examining data retention characteristics when charges are injected into both the Bit1 side and the Bit2 side.
FIG. 27 is a diagram illustrating erase characteristics of the nonvolatile semiconductor memory according to the first embodiment;
FIG. 28A is a schematic diagram illustrating a nonvolatile semiconductor memory according to a sixth embodiment, and FIG. 28B is a diagram illustrating write characteristics of the nonvolatile semiconductor memory.
FIG. 29 is a diagram illustrating a result of examining a data retention characteristic when electric charge is injected only into Bit 1 of the nonvolatile semiconductor memory according to the sixth embodiment;
FIG. 30 is a diagram illustrating erasing characteristics of the nonvolatile semiconductor memory according to the sixth embodiment;
[Explanation of symbols]
10, 20 ... semiconductor substrate,
11 ... impurity diffusion region,
12, 23, 4, 51, 61, 71 ... gate insulating film,
12a, 12c, 41a, 41c, 51c, 61a, 81a, 101a, 101c, 111a, 111c, 121c, 131a, 151a, 151c, 161a, 161b, 171c, 181a, 201a, 201c, 211a, 211c, 221c, 231a ... Silicon oxide film,
12b, 51a, 61c, 71a, 82a, 121a, 131c, 141a, 171a, 181c, 191a, 221a, 231c, 241a ... silicon nitride film,
13, 42, 52, 62, 72 ... gate electrode,
21 ... bit line,
22 ... Local insulating film,
23a, 81: tunnel insulating film,
23b, 82: trap insulating film,
23c, 83 ... top insulating film,
24 ... word line,
25 ... memory cell,
30 ... control circuit,
31 Sense amplifier section
32 Word line driver
33 ... CPU,
41b, 82b, 83b ... alumina film,
51b, 61b, 71b ... AlHfO film,
HfO 71c, 83a, 101b, 121b, 131b, 141c, 191c ... ₂ film,
81b ... La ₂ O ₅ film,
111b, 141b, 241c ... HfAlO film,
152b, 171b, 181b ... ZrO ₂ film,
161b, 191b ... ZrAlO film,
201b, 221b, 231b ... La ₂ O ₃ film,
211b, 241b ... LaAlO film.

Claims (7)

A semiconductor substrate;
A pair of impurity diffusion regions formed in the semiconductor substrate,
A tunnel insulating film formed on a region between the pair of impurity diffusion regions,
A trap insulating film formed on the tunnel insulating film by at least one oxide selected from the group consisting of Al ₂ O ₃ , HfO ₂ , ZrO _2, and Ln ₂ O ₃ (where Ln is a lanthanoid element) ,
A top insulating film formed on the trap insulating film,
And a gate electrode formed on the top insulating film. A semiconductor substrate;
A pair of impurity diffusion regions formed in the semiconductor substrate,
A tunnel insulating film formed on a region between the pair of impurity diffusion regions,
A trap insulating film formed on the tunnel insulating film by an oxide mainly containing one element selected from the group consisting of Al, Hf, Zr, and Ln (where Ln is a lanthanoid element);
A top insulating film formed on the trap insulating film,
And a gate electrode formed on the top insulating film. 3. The nonvolatile semiconductor memory according to claim 1, wherein a barrier height of the tunnel insulating film is lower than a barrier height of a silicon oxide film having the same thickness. The nonvolatile semiconductor memory according to claim 1, wherein a relative dielectric constant of the top insulating film is higher than a relative dielectric constant of the silicon oxide film. The nonvolatile semiconductor memory according to claim 1, wherein the tunnel insulating film includes a plurality of films having different compositions. The nonvolatile semiconductor memory according to claim 1, wherein the trap insulating film includes a plurality of films having different compositions. The nonvolatile semiconductor memory according to claim 1, wherein the top insulating film includes a plurality of films having different compositions.

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