JP2013168673A - Nand-type nonvolatile semiconductor memory device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a block insulating film, and to provide a method of manufacturing the same.SOLUTION: A NAND-type nonvolatile semiconductor memory device comprises on a semiconductor substrate: a plurality of memory cell transistors connected to each other in series; and a select transistor. The memory cell transistor comprises: a first insulating film 102a on the semiconductor substrate; a charge storage layer 104; a second insulating film 106a made of aluminum oxide; a first control gate electrode 108a; and a first source/drain region. The select transistor comprises: a third insulating film 102b on the semiconductor substrate; a fourth insulating film 106b made of aluminum oxide and containing a pentavalent cationic element; a second control electrode 108b; and a second source/drain region.

Description

  The present invention relates to a NAND-type nonvolatile semiconductor memory device having a MONOS-type memory cell and a method for manufacturing the same.

  In flash memories, miniaturization of memory cell sizes is progressing with an increase in memory capacity. For this reason, attention has been paid to a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type memory in which the charge storage layer is changed from a floating gate type to an insulating film having a charge trap function.

  The MONOS type memory has a structure in which a tunnel insulating film that selectively passes charges, a charge storage layer, and a block insulating film that blocks current between the charge storage layer and the control gate electrode are sequentially stacked. Since the element can be simplified and miniaturized, studies for further miniaturization as a next-generation memory are underway.

At present, as a study for realizing ultra-fine cells using MONOS type memory, an attempt to introduce a higher dielectric constant material (High-k material) instead of the silicon oxide film that has been used as a block insulating film until now. Is being considered. In particular, an aluminum oxide film has a higher dielectric constant than a silicon oxide film and exhibits good performance in charge retention characteristics. Therefore, studies are underway for practical application as a next-generation block insulating film (for example, Non-Patent Document 1).
JS. Lee, et al. , SSDM (2005) 200.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high-performance MONOS-type NAND nonvolatile semiconductor memory device using an aluminum oxide film as a block insulating film and a method for manufacturing the same. Is to provide.

  A NAND nonvolatile semiconductor memory device of one embodiment of the present invention includes a plurality of memory cell transistors connected in series on a semiconductor substrate and a selection transistor provided at an end of the plurality of memory cell transistors connected in series. The memory cell transistor includes a first insulating film on the semiconductor substrate, a charge storage layer on the first insulating film, and a second insulating film made of aluminum oxide on the charge storage layer. A first control gate electrode on the second insulating film, and a first source / drain region formed in the semiconductor substrate on both sides of the first control gate electrode, and the selection transistor includes: A third insulating film on the semiconductor substrate; a fourth insulating film which is aluminum oxide and contains a pentavalent cation element; and a fourth insulating film on the third insulating film. And second control gate electrodes, characterized by further comprising a second source / drain regions formed in the semiconductor substrate on both sides of the second control gate electrode.

  According to the present invention, it is possible to provide a high-performance MONOS-type NAND nonvolatile semiconductor memory device using an aluminum oxide film as a block insulating film and a method for manufacturing the same.

  In the NAND type nonvolatile semiconductor memory device, a memory cell transistor region and a selection transistor region in which a selection transistor for selecting a desired memory cell transistor is arranged are provided. In order to reduce the number of manufacturing steps and cost, a manufacturing method is adopted in which the structures of the memory cell transistor and the selection transistor are made as common as possible. The interval between the memory cell transistor rows connected in series and the selection transistor is determined in consideration of the degree of integration and electrical characteristics such as erroneous writing. Usually, one or several gate dummy patterns that do not function as an element are interposed at the same interval as the control gate electrode portion of the memory cell transistor.

When an aluminum oxide film (hereinafter also referred to as an Al ₂ O ₃ film is also used as a representative of the aluminum oxide film) is used as the block insulating film of the MONOS memory, the aluminum oxide film is not necessarily formed in the select transistor region due to its characteristics. A material film is not essential. However, the electrical characteristic deterioration of the gate SiO ₂ under the aluminum oxide film due to the increase in the selective removal process, the characteristic variation due to misalignment, and the difficulty of dry etching of the aluminum oxide film, which is the greatest concern, Etc. must be avoided. Therefore, selection transistor region becomes the memory transistor region the same, an electrode _{/ Al 2 O 3 / SiN /} SiO 2 structure (MANOS) electrode _/ Al ₂ to remove SiN or O 3 / SiO ₂ structure (MAOS).

In the former case, charge trapping due to SiN as a charge storage layer is inevitable, while charge trapping due to the Al ₂ O ₃ / SiO ₂ interface also occurs in the latter. In any case, since the threshold shift of the transistor is large, it is a problem that threshold control is difficult. Therefore, even when an Al ₂ O ₃ film is used as the blocking insulating film, it is required to reduce a threshold shift due to charge trapping in the selection transistor.

Before describing the embodiment of the present invention, the basic principle of the present invention will be described. When the Al ₂ O ₃ / SiO ₂ laminated film is used as the gate insulating film of the selection transistor of the NAND type nonvolatile semiconductor memory device, the present inventors have added a tetravalent cation element or a pentavalent cation in Al ₂ O _3. It has been found that the amount of charge trapping is reduced by introducing an element or N. The experimental facts are shown below.

As an elemental experiment showing the effectiveness of charge trap reduction by adding other elements to the Al ₂ O ₃ / SiO ₂ laminated film, the influence of Si as a tetravalent element was first investigated. First, in order to investigate the trap charge density of the current MAOS (Mo electrode / Al ₂ O ₃ / SiO ₂ / Si) capacitor, the SiO ₂ film thickness was fixed and only the Al ₂ O ₃ film thickness was changed. The relationship between the charge trap amount and the film thickness of the sample was investigated. At this time, the effects of heat treatment at 600 ° C. and 1000 ° C. were evaluated together.

FIG. 3 is a graph showing the relationship between Al ₂ O ₃ equivalent silicon oxide film thickness (Teff_AlO) and Vfb change (ΔVfb) after applying 13 MV / cm as stress. Teff_AlO and ΔVfb are expressed in a linear form where the intercept is zero both before and after annealing. This indicates that there is a high possibility that the Al ₂ O ₃ / SiO ₂ / Si charge trap exists at the Al ₂ O ₃ / SiO ₂ interface. It was also found that the trap charge density (N) is reduced as the heat treatment temperature is increased. As a cause of this, considering the contribution of Si in the Al ₂ O ₃ / SiO ₂ reaction by annealing, the influence on trap charge in a sample in which Si was previously added to Al ₂ O ₃ was investigated.

FIG. 4 is a graph showing the relationship between the Si concentration (Si / (Si + Al)) and trap charge density (N) in Al ₂ O ₃ before and after heat treatment at 1000 ° C. Looking at the results before heat treatment (as-depo.), It was found that the trap charge density was greatly reduced when Si / (Si + Al) = 0.03 or more was added. From this result, it was found that even if Si was previously added to Al ₂ O ₃ , the trap charge density was sufficiently reduced. The trap charge density was further reduced by the heat treatment at 1000 ° C. This is thought to be because the contribution of Si was increased by the high-temperature heat treatment.

From the above, it can be seen that the trap charge density seen in the MAOS structure is greatly reduced by diffusing Si into Al ₂ O ₃ by heat treatment or by adding Si in advance to Al ₂ O _3. It was.

From the above experimental fact alone, it is not possible to identify the structure of the defect that contributed to the decrease in trap charge density. Therefore, in order to determine the defects that contributed to the reduction of the trap charge density, the inventors determined a 2 × 2 × 2 cell of α-Al ₂ O ₃ unit cell (containing 2Al ₂ O ₃ = 10 atoms) (total 16Al ₂ O ₃ = initio spun using included) and alpha-SiO ₂ unit cell (3SiO2 = 9 2x2x2 times the cell (total 24SiO ₂ = supercell based on included) 72 atoms atoms include) 80 atom Polarization non-local approximation density functional method (SP-GGA-DFT method: Spin-Polarized Generalized Gradient Density Functional Theory) was performed.

In the calculation of the Al ₂ O ₃ system, this cell has substitutional or interstitial defects of M (M = Si, Hf), and these and Al vacancies (V _Al ), oxygen vacancies (V _O ), and interstitial spaces. Defect pairs (complex: complex) with oxygen (O _i ), substituted nitrogen (N _O ), and interstitial nitrogen (N _i ) are introduced, and each defect structure and the level when they are trapped and released are shown. Calculated. For SiO ₂ based calculations. M (M = Al, Ge, Hf, P, As) substitutional or interstitial defects, and these and Si vacancies (V _Si ), oxygen vacancies (V _O ), interstitial oxygen (O _i ), A defect pair (complex: complex) with substituted nitrogen (N 2 _{O 3} ) and interstitial nitrogen (N _i ) was introduced. When the charge state was changed, the excess dipole energy gain due to the supercell method was corrected according to the method of Makov-Payne-Kantorovich.

5 and 6 show the Kohn-Sham level (one electron energy level) of various charged states of each defect in Al ₂ O ₃ with the electron energy on the horizontal axis and the density of states on the vertical axis. It is a figure. VB is the valence band of Al ₂ O ₃ , CB is the same conduction band, ΔEv (Si) or ΔEv (HfO ₂ ) is the offset amount between the valence band of Al ₂ O _{3 and} the valence band of Si or HfO ₂ , A solid arrow attached to a level appearing in the band gap indicates an electron occupied level, and a white arrow indicates an electron unoccupied level.

FIG. 5 shows a one-electron level when Si is introduced into Al ₂ O ₃ . The fact that the vicinity of the valence band (VB) edge is constituted by the O2p orbit is not limited to Al ₂ O ₃ and SiO ₂ examined here, but is common in oxides. First, when considering the trap origin of the Al ₂ O ₃ / SiO ₂ film, it forms a level that traps electrons and further stabilizes (does not detrap) the trapped electrons, so interstitial oxygen (O _i ) And the possibility of Al deficiency (V _Al ).

FIG. 7 is a diagram showing charge trap levels of O _i , V _Al , and V 2 _O according to theoretical calculation. Here, from the Kohn-Sham level itself shown in FIG. 5 or 6, it can be determined at a glance whether or not charge can be transferred, but the exact charge trapping / emission level is not known. This is because, particularly in an ionic substance such as Al ₂ O ₃ , lattice relaxation accompanied by a large energy gain occurs with charge trapping / release, and a defect level cannot be obtained without consideration thereof.

  The inventors determined the exact defect level by comparing the total energy before and after the structure relaxation associated with charge trapping / release. In FIG. 7, the horizontal axis represents electron energy (Fermi level), and the vertical axis represents defect generation energy. A positive value on the vertical axis indicates an endothermic reaction, and a negative value indicates an exothermic reaction. For each defect, a horizontal line and a straight line bent from it are shown. The horizontal line is the generated energy in the charge neutral state, which is parallel to the horizontal axis because it does not depend on the Fermi level. On the other hand, the energy in the charge trapping state greatly depends on the Fermi level, behaves with a bending point with respect to the value on the horizontal axis, and becomes a broken line. For each charge state of each defect, the difference between the horizontal line and the downward-sloping broken line is the electron affinity, and the difference from the upward-sloping broken line corresponds to the hole affinity. In addition, the difference between the value of the horizontal axis (Fermi level) of the inflection point between “0” and “−2” in the figure and the conduction band lower end (CBM: M is the minimum and the lower end) is the acceptor level. Equivalent to.

According to this figure, neutral O _i forms an unoccupied level of electrons due to an unoccupied O2p orbit in gap. This unoccupied level is shallow in the neutral state (close to the lower end of the conduction band), but when the electrons are captured, a large lattice relaxation occurs, and the unoccupied level is greatly stabilized by the negative U (negative-U) effect. Therefore, it is known that when electrons are captured and become O _i ^2−, they become deep electron occupation levels and stabilize. Also, _{V Al} neutral can also receive up to three electrons to unoccupied orbital of O2p three O adjacent to _{V ^Al (V Al} ^3-), that level is deeper within 2eV from VBM This shows that it is difficult to trap electrons and detrap electrons.

Furthermore, at the interface of Al ₂ O ₃ / SiO ₂ , defect generation in SiO ₂ should also occur, and it is expected that tetravalent Si and trivalent Al are easily replaced with each other. In fact, according to the theoretical calculation by the inventors, even when Al is substituted on the Si site in SiO ₂ (Al 2 _{Si 3} ), the non-O 2p of one O adjacent to Al 2 _Si is adjacent to the valence band edge of SiO _2. It has been found that unoccupied levels of electrons are formed by occupied orbitals and stabilized by electron traps. Here, in the experimental results, there is a high possibility that Al ₂ O ₃ / SiO ₂ has a charge trap at the interface, and the decrease in charge trap due to high-temperature annealing is the influence of Si due to the mixing of Al ₂ O ₃ / SiO _2. I know there is a possibility. Consider the contribution of Si together with the first-principles calculation results.

When Si is added to Al ₂ O ₃ , a small amount of Al site is replaced with Si (Si _Al ), and oxygen is appropriately supplied to include interstitial oxygen (O _i ), the O _i and the Al site The substituted Si (Si _Al ) can make a 1: 1 pair. However, this alone leaves an unoccupied level for one electron per defect pair. However, when electrons are trapped in this, the unoccupied level in gap disappears, stabilizes to a level due to oxygen non-bonded electrons, and appears near the valence band edge. When the Si amount is further increased, O _i and Si _Al form a 1: 2 pair. In this case, the gap level disappears without charge injection from the electrode only by forming the defect pair, which greatly contributes to the reduction of charge traps. On the other hand, Si _Al forms surplus electrons due to the occupied orbitals of Si3sp in the gap of Al ₂ O ₃ . Therefore, it is known that when Al deficiency is present, the surplus electrons are trapped at the Al deficient site (V _Al ) to form a charge compensation defect pair (V _Al -3Si _Al ), which is stabilized in terms of energy. Therefore, the theoretical calculation revealed for the first time that charge traps are reduced by Si into Al ₂ O ₃ in either case of formation of defects.

Next, the effect of adding nitrogen will be described. From Figure 5, N2p because electrons are shallower than O2p electronic In both, _Al 2 _{O 3} gap in value just above the valence band upper end of the interstitial nitrogen _{(N i)} or nitrogen substituted on an oxygen deficiency sites _{(N O)} An electron-occupied level is generated around, and a vacant level is formed on the upper side of N 2 _O and another clogged level is formed on the same side in N _i . Therefore, when Al deficiency in _Al 2 _{O 3 (V Al)} is present it from surplus electrons _{N O} or _{N i} formed shallower also moves _{V Al,} each _2V Al -3N _O defect pair or stabilizing becomes _V Al -N _i defect pair. However, in the 2V _Al- 3N _O defect pair, excessive electron non-occupied levels due to N 2 _O are generated, and it is understood that charge compensation with 3Si _Al or the like is necessary.

Further, when interstitial oxygen (O _i ) is present, an interstitial anion such as O _i is considered to undergo substitutional diffusion while coordinating to the interstitial anion, and N _O + O _i → O _O + N _i The reaction proceeds. Further stabilized by forming a very strong N≡N as N ₂ by meeting N _i Hamou one N _i, resulting in inactivation also electronically. Thus, theoretical calculations show for the first time that charge trapping is also reduced by N in Al ₂ O ₃ .

Further, FIG. 6 compares Si and Hf as substitution elements. Even in the case of Hf, which is a transition metal element having a valence electron of 5d ² 6s ² having a higher energy than that of Si, which is a typical element, the electronic state shows that the result is the same as Si in terms of energy. It became clear for the first time by theoretical calculation.

In addition, in the case of pentavalent elements, when the Al site in Al ₂ O ₃ is replaced, and when interstitial atoms are formed, the surplus valence electrons are further increased by one as compared with Si and Hf. In comparison, there are two surpluses. In this case, the theoretical calculation reveals for the first time that the O _i -M _Al defect pair and the 2V _Al -3M _Al (M = pentavalent cation) defect pair are electronically inactivated without the need to trap charges. Became.

Based on the above results, the electron levels in the Al ₂ O ₃ gap of Al ₂ O ₃ / SiO _{2 as} the selection gate are shown in FIG. 8, and a band depending on the concentration when a tetravalent or pentavalent cation element is added thereto. Changes in the figure are shown in FIG. 9 (M / (M + Al) <0.03: M = tetravalent cation element. In the case of pentavalent cation element, an equivalent effect occurs at half the concentration) and FIG. 10 ((M / (M + Al) ≧ 0.03: In the case of M = tetravalent cation element. In the case of pentavalent cation element, an equivalent effect is produced at half the concentration. From this result, M / (M + Al) ≧ 0.03 (In the case of M = tetravalent cation element. In the case of pentavalent cation element, the same effect is produced at half the concentration), and it can be seen that the effect of addition is more remarkably exhibited.

_Further, Al ₂ O 3 / illustrates an electronic level of the case of adding N in SiO ₂ to _Al 2 _{O 3} in FIG. 11 (0.02 ≦ N / (O + N) ≦ 0.4), N added Al _The contribution to interstitial oxygen and Al vacancies, considered as the origin of charge traps in the ₂ O ₃ gap, is shown in FIG. As described with reference to FIGS. 5 to 6, these optimum addition concentrations are interstitial oxygen (O _i ), Al deficiency (V _Al ), and oxygen deficiency (V _O ), which are intrinsic defects in Al ₂ O _3. the number of Al ₂ O ₃ extra electrons or deficient electrons in the gap by, is what is determined uniquely by the balance between the Al ₂ O ₃ the number of excess electrons or deficient electrons in the gap caused by the added elements.

From the above, when an Al ₂ O ₃ / SiO ₂ laminated film is used as the selection gate, the amount of charge traps is reduced by introducing a tetravalent cation element, a pentavalent cation element, or N into Al ₂ O _3. I found out.

  Hereinafter, an embodiment of the present invention using an aluminum oxide film to which the above-described knowledge found by the inventors is applied will be described with reference to the drawings.

(First embodiment)
The NAND-type nonvolatile semiconductor memory device according to the first embodiment of the present invention includes a plurality of memory cell transistors connected in series on a semiconductor substrate, and ends of the plurality of memory cell transistors connected in series. The selection transistor is provided. The memory cell transistor includes a first insulating film on a semiconductor substrate, a charge storage layer on the first insulating film, and a second insulating film whose main component is aluminum oxide on the charge storage layer. And a first control gate electrode on the second insulating film, and a first source / drain region formed in the semiconductor substrate on both sides of the first control gate electrode. The selection transistor includes a third insulating film on the semiconductor substrate and a main component on the third insulating film made of aluminum oxide, and includes a tetravalent cation element, a pentavalent cation element, and N (nitrogen). A fourth insulating film containing at least one element as a minor component, a second control electrode on the fourth insulating film, and a second control electrode formed in the semiconductor substrate on both sides of the second control gate electrode. 2 source / drain regions.

  Here, the first insulating film is a so-called tunnel insulating film, and has a function of selectively passing charges between the semiconductor substrate and the charge storage layer. The second insulating film is a so-called block insulating film and has a function of blocking current between the charge storage layer and the first control gate electrode. In this specification, the fact that the main component of the insulating film is aluminum oxide means that the band structure of the insulating film, in other words, the band gap, can be described by that of aluminum oxide. That is, the additive element only has an effect of modulating the band structure of the aluminum oxide, for example, by forming a defect level, raising the upper end of the valence band, or lowering the lower end of the conduction band. In addition, the fact that an element is a minor component means that the atomic concentration of the element (atom) in the insulating film is small and no modulation is applied to the extent that the band structure of the aluminum oxide itself cannot be maintained.

  FIG. 2 is a chip layout diagram of the NAND-type nonvolatile memory device according to the present embodiment. This NAND-type nonvolatile memory device 10 has a peripheral circuit region 12 in which peripheral circuit transistors are arranged, and a core region 14 including memory cells. The core region 14 further includes a memory cell array region 16 in which memory cell transistors are arranged, and a selection transistor region 18 sandwiched between the memory cell array regions 16 and in which selection transistors for selecting desired memory cells are arranged. doing.

  FIG. 1 is a cross-sectional view of a part of the core region 14 indicated by a broken line in FIG. In the NAND type nonvolatile memory device 10, for example, n (n is an integer) memory cell transistors MT11 to MT1n are arranged adjacent to each other. Each of the memory cell transistors MT11 to MT1n shares a source region and a drain region with the adjacent memory cell transistors MT11 to MT1n, and the memory cell transistors MT11 to MT1n are connected in series. In the memory cell array region 16 of FIG. 2, a large number of columns of memory cell transistors connected in series are arranged in parallel.

As shown in FIG. 1, the memory cell transistor includes, for example, a first insulating film 102a that is, for example, a SiO ₂ film on a semiconductor substrate 100 that is silicon, and a silicon nitride film, for example, that is on the first insulating film 102a. A charge storage layer 104, a second insulating film 106a on the charge storage layer 104 whose main component is aluminum oxide, and a stacked film of, for example, tantalum nitride and tungsten (TaN) on the second insulating film 106a. / W stacked film) and source / drain regions formed by introducing impurities such as As and P into the semiconductor substrate 100 on both sides of the first control gate electrode 108a. 110a and 110b. Note that in this embodiment, the second insulating film 106a contains at least one element of a tetravalent cation element, a pentavalent cation element, and N (nitrogen) as a small component.

As shown in FIG. 1, two select transistors STS1 and STD1 are arranged adjacent to both ends of the memory cell transistors MT11 to MT1n connected in series. The select transistor STS1 includes a third insulating film 102b that is, for example, a SiO ₂ film on the semiconductor substrate 100, and a main component on the third insulating film 102b that is an aluminum oxide, a tetravalent cation element, and a pentavalent element. A fourth insulating film 106b containing at least one element out of a cation element and N (nitrogen) as a minor component, and a second film that is a stacked film of, for example, tantalum nitride and tungsten on the fourth insulating film 106b. Source / drain regions 110c and 110a formed by introducing impurities such as As and P into the semiconductor substrate 100 on both sides of the control gate electrode 108b and the second control gate electrode 108b are provided. Here, in the present embodiment, the drain region 110a is shared with the source region 110a of the adjacent memory cell transistor (MT11 in FIG. 1), but it is not necessarily required to be shared. For example, when a gate dummy pattern is provided between the memory cell transistor MT11 and the select transistor STS1, the source / drain regions are not shared. A source line contact 22 is disposed on the source region 110c adjacent to the select gate transistor STS1.

On the other hand, the select transistor STD1 is disposed adjacent to the memory cell transistor MT1n located at the other end of the memory cell transistor array. The select transistor STD1 includes a third insulating film 102b that is, for example, a SiO ₂ film on the semiconductor substrate 100, and a main component on the third insulating film 102b that is an aluminum oxide, a tetravalent cation element, and a pentavalent element. A fourth insulating film 106b containing at least one element out of a cation element and N (nitrogen) as a minor component, and a second film that is a stacked film of, for example, tantalum nitride and tungsten on the fourth insulating film 106b. Source / drain regions 110d and 110e formed by introducing impurities such as As and P into the semiconductor substrate 100 on both sides of the control electrode 108b and the second control gate electrode 108b are provided. Here, in the present embodiment, the source region 110d is shared with the drain region 110d of the adjacent memory cell transistor (MT1n in FIG. 1), but it is not necessarily required to be shared. Is the same as that of the select transistor STS1. A bit line contact 24 is disposed on the drain region 110e adjacent to the select gate transistor STD1.

  According to the present embodiment, the amount of charge traps in the aluminum oxide film that is a part of the gate insulating film of the select transistors STS1 and STD1 can be suppressed extremely low. Therefore, it is possible to prevent the memory from malfunctioning because the threshold value of the transistor fluctuates due to trapping of charges in the gate insulating films of the selection transistors STS1 and STD1 during the memory operation. Therefore, a NAND type nonvolatile memory device with improved reliability can be realized. Further, according to the present embodiment, it is not necessary to peel off the aluminum oxide film that is a part of the gate insulating film of the selection transistors STS1 and STD1 in view of the variation in transistor characteristics. Therefore, the alignment margin between the memory cell transistor at the end and the select transistor, which has been conventionally provided for peeling the aluminum oxide film, can be made unnecessary. Therefore, it is possible to reduce the chip area of the NAND type nonvolatile memory device. Further, it is possible to avoid damage to the gate insulating film of the selection transistor that occurs in the aluminum oxide film peeling process.

  In the present embodiment, for example, the first insulating film 102a (FIG. 1) and the third insulating film 102b of a silicon oxide film have a thickness of about 3 nm to 5 nm. For example, the film thickness of the charge storage layer 104 which is a silicon nitride film is about 1 nm to 5 nm. The film thickness of the aluminum oxide to which a tetravalent or pentavalent element is added as the second insulating film 106a and the fourth insulating film 106b is about 4 nm to 15 nm.

  Here, the tetravalent cation element is at least one element selected from Si, Ge, Sn, Hf, Zr, and Ti, and the pentavalent cation element is at least one element selected from V, Nb, and Ta. It is desirable to be.

  In this embodiment, any one element of a tetravalent cation element, a pentavalent cation element, and N (nitrogen) is substantially uniformly contained in the aluminum oxide that is the third insulating film 102b. It is desirable. This reduces both power consumption due to leakage current reduction due to reduction of bulk defects (charge traps) and suppression of threshold change due to reduction of defects (charge traps) near the aluminum oxide / third insulating film interface of the aluminum oxide film. This is because it can be achieved.

  In this embodiment, the concentration distribution is adjusted so that the total concentration of the tetravalent cation element, the pentavalent cation element, and the additive element of N (nitrogen) has a maximum distribution on the third insulating film side. May be. Here, the concentration refers to the number of atoms per unit volume. Further, the third insulating film side means a region in a range where interface defects distributed from the interface with the third insulating film to the aluminum oxide film exist. When an aluminum oxide film having the above film thickness range is used, it corresponds to a region in the range of approximately 10% of the film thickness. As described above, defects that become charge traps in the aluminum oxide are unevenly distributed near the interface between the aluminum oxide film and the lower third insulating film. Moreover, the bulk defect exists substantially uniformly in the aluminum oxide film. Therefore, by setting the distribution of the additive element to have a maximum value on the third insulating film side, it is possible to effectively reduce defects in the entire stacked structure with the minimum element addition amount. In addition, by providing a concentration gradient, stress relaxation and reduction of lattice mismatch can be expected.

  The concentration of tetravalent cation element in the film mainly composed of aluminum oxide as the fourth insulating film is 0.03 ≦ M / (Al + M) ≦ 0.3 (M = tetravalent cation element), pentavalent cation The concentration of the element in the fourth insulating film is 0.015 ≦ M / (Al + M) ≦ 0.15 (M = pentavalent cation element), and the concentration of N (nitrogen) in the fourth insulating film is 0.02. It is desirable that ≦ N / (O + N) ≦ 0.4. This is because the amount of charge traps can be further reduced within this range. In addition, a density | concentration shall be represented by the atomic ratio (molar ratio) in a measurement location here.

  In this embodiment, the case where a silicon oxide film is used as the first insulating film 102a (FIG. 1) and the third insulating film 102b which are block insulating films of the memory cell transistor has been described as an example. However, in addition to the silicon oxide film, a silicon oxynitride film or a laminated film (ONO film) composed of silicon oxide film / silicon nitride film / silicon oxide film may be used.

In this embodiment, the case where a silicon nitride film is used as the charge storage layer 104 (FIG. 1) of the memory transistor is taken as an example. The composition ratio may be Si ₃ N ₄ having a stoichiometric composition or a silicon nitride film having a Si-rich composition in order to increase the trap density in the film. In addition to the silicon nitride film, it is possible to reduce the electrical film thickness by using a high dielectric constant film, so that the charge storage layer can be made of Al, Hf, La, Y, Ce, Ti, Oxides, nitrides, or oxynitrides containing at least one element selected from Zr and Ta can be widely used, and a laminate of these films can also be used.

Further, in the present embodiment, a laminated film of tantalum nitride and tungsten is taken as an example as a material for the first and second control gate electrodes. However, in addition to tantalum nitride, n ⁺ type polycrystalline silicon, p ⁺ type polycrystalline silicon, Au, Pt, Co, Be, Ni, Rh, Pd, Te, Re, Mo, Al, Hf, Ta, Mn, Zn, One or more elements selected from Zr, In, Bi, Ru, W, Ir, Er, La, Ti, and Y, and simple substances thereof or metal systems such as silicides, borides, nitrides, carbides, etc. A wide variety of conductive materials can be used. In particular, a metal-based conductive material having a large work function is desirable because a leakage current from the block insulating film to the control gate electrode can be reduced. In this embodiment mode, tungsten is used for a layer stacked with tantalum nitride, but other than that, low resistance full silicide or metal conductive material such as nickel silicide or cobalt silicide can be widely used.

  Next, a method for manufacturing the NAND nonvolatile memory device according to the present embodiment will be described with reference to FIGS. 13 to 18 are process cross-sectional views illustrating the manufacturing method of the present embodiment. Here, the cross section of the memory cell transistor MT11 and the select transistor STS1 at the source contact side end in FIG. 1 will be described as an example of the memory cell transistors.

The manufacturing method of the present embodiment forms a first insulating film and a third insulating film on a semiconductor substrate,
A charge storage layer is deposited on the first insulating film and the third insulating film, the charge storage layer on the third insulating film is removed, and a second component whose main component is aluminum oxide is formed on the charge storage layer. An insulating film of
On the third insulating film, a fourth insulating film containing a major component of aluminum oxide and containing at least one element selected from a tetravalent cation element, a pentavalent cation element, and N (nitrogen) as a minor component. Forming a first control gate electrode on the second insulating film, forming a second control gate electrode on the fourth insulating film, and in the semiconductor substrate on both sides of the first control gate electrode. Forming a first source / drain region and forming a second source / drain region in the semiconductor substrate on both sides of the second control gate electrode.

  Here, the first insulating film means an insulating film formed on a semiconductor substrate in a region where a memory cell transistor is formed, and is an insulating film that finally becomes a tunnel insulating film of the memory cell transistor. . Here, the third insulating film means an insulating film formed on the semiconductor substrate in a region where the selection transistor is formed, and is an insulating film that finally becomes a gate insulating film of the selection transistor. Hereinafter, a manufacturing method in which the first insulating film and the third insulating film are simultaneously formed will be described as an example. However, the first insulating film and the third insulating film are not necessarily formed at the same time.

  First, as shown in FIG. 13, silicon having a thickness of about 3 nm to 5 nm is formed by, for example, thermal oxidation on a P-type silicon semiconductor substrate 100 having a (100) surface doped with an impurity such as B. A first insulating film 102a and a second insulating film 102b made of an oxide film are formed. The formation of the tunnel oxide film is not limited to thermal oxidation, and may be performed by, for example, a CVD (Chemical Vapor Deposition) method. Prior to the formation of the first insulating film 102a and the third insulating film 102b, an element isolation region (not shown) in which a silicon oxide film is embedded is formed on the semiconductor substrate 100 by a known process. Next, a charge storage layer 104 made of, for example, a silicon nitride film having a thickness of about 1 nm to 5 nm is deposited on the first insulating film 102a and the third insulating film 102b by a CVD method or the like.

  Next, as shown in FIG. 14, the charge storage layer 104 over the third insulating film 102b is removed. That is, the charge storage layer 104 on the insulating film in a region where the selection transistor STS1 is to be formed later is selectively removed. For example, after the first insulating film 102a is masked with a resist, it can be selectively removed by dry etching.

  Next, as shown in FIG. 15, a second insulating film 106 a whose main component is aluminum oxide is formed on the charge storage layer 104. In addition, a fourth component on the third insulating film 102b is a main component of aluminum oxide, and contains at least one element selected from a tetravalent cation element, a pentavalent cation element, and N (nitrogen) as a minor component. An insulating film 106b is formed. Note that the case where the second insulating film 106a and the fourth insulating film 106b are simultaneously formed as films having the same composition is described here as an example.

  The aluminum oxide film containing at least one element among the tetravalent cation element, the pentavalent cation element, and N (nitrogen) as the third and fourth insulating films as a minor component is a tetravalent or pentavalent cation element. And an Al metal target or an oxide target thereof. As a sputtering gas condition, a rare gas such as Ar alone may be used, or a chemical sputtering method in which oxygen or nitrogen is mixed at an appropriate flow rate ratio may be used. From the viewpoint of suppressing the generation of oxygen vacancies in the alumina oxide film, it is desirable to use a sputtering method in which at least the oxygen flow rate is controlled.

  Note that the method for manufacturing this film is not limited to the sputtering method, and a CVD method, an ALD method, a vapor deposition method, a laser ablation method, an MBE method, or a film forming method combining these methods is also possible. Further, after forming a part or all of the thickness of the aluminum oxide film, an element which is a minor component may be introduced by an ion implantation method or the like.

  In addition, this film is formed by, for example, forming a wafer with a solution in which a trace amount of tetravalent or pentavalent cation element is dissolved after forming a charge storage layer or forming a part or all of an aluminum oxide film. It is also possible to introduce it into the aluminum oxide film by heat treatment after the amount of adhesion is controlled by flowing water or dipping, the element concentration in the solution, flowing water time or dipping time.

  When the main element forming the charge storage layer 104 in the memory transistor region and the third insulating film 102b which is the gate insulating film in the selection transistor region is formed from tetravalent or pentavalent cations, aluminum oxide is formed thereon. A film of a tetravalent or pentavalent element is formed by depositing a part or all of the film thickness, then heat-treating, setting the interfacial reaction rate and interdiffusion rate depending on the heat treatment temperature, and controlling the heat treatment time. It is also possible to control the amount of diffusion into the inside. For example, when the charge storage layer 104 is formed of a silicon nitride film and the third insulating film is formed of a silicon oxide film, Si can be added to the aluminum oxide by the above method.

Next, as shown in FIG. 16, a TaN / W stacked film 108 is deposited on the second insulating film 106a and the fourth insulating film 106b. This TaN / W laminated film 108 forms TaN by a CVD method using Ta (N (CH ₃ ) ₂ ) ₅ or Ta (N (CH ₃ ) ₂ ) ₅ and NH ₃ as raw materials, and subsequently W ( CO) W is formed by a CVD method using ₆ as a raw material. In addition, the manufacturing method of this film is not limited to the method shown here, and other source gases may be used. In addition to the CVD method, for example, a sputtering method, an ALD method, a vapor deposition method, a laser ablation method, an MBE method, or a film forming method combining these methods can be employed.

  Next, as shown in FIG. 17, the first control gate electrode 108a, the second insulating film 106a, the charge storage film 104, and the first insulating film 102a are formed in the region of the memory cell transistor MT11 by known lithography and RIE. The pattern is formed. Similarly, the second control gate electrode 108b, the fourth insulating film 106a, and the third insulating film 102b are patterned in the select transistor STS1 region.

  Thereafter, as shown in FIG. 18, for example, As is ion-implanted using the first control gate electrode 108a as a mask, and an n + -type first source is introduced into the semiconductor substrate 100 on both sides of the first control gate electrode 108a. / Drain regions 110a and 110b are formed. Further, for example, As is ion-implanted using the second control gate electrode 108b as a mask, and n + -type second source / drain regions 110c and 110a are formed in the semiconductor substrate 100 on both sides of the second control gate electrode 108b. Form. Here, the case where the first source / drain regions 110a and 110b and the second source / drain regions 110c and 110a are formed by a simultaneous process is shown as an example, but each is formed by a separate process. It doesn't matter. The ion implantation may be performed after depositing a thin film on the control gate electrode or after forming a sidewall insulating film on both sides of the control gate electrode in order to control the position and depth of the diffusion layer.

  Thereafter, wirings and the like are formed by a well-known method to form the NAND type nonvolatile semiconductor memory device of this embodiment.

  Note that in this embodiment, a main component is aluminum oxide in part of the gate insulating film of the selection transistor, and at least one element of a tetravalent cation element, a pentavalent cation element, and N (nitrogen) is added. Although the case where an insulating film containing a small amount of component is applied to reduce the amount of charge traps has been described, the same operation and effect can be expected by applying a similar gate insulating film to peripheral transistors.

(Second Embodiment)
The NAND-type nonvolatile semiconductor memory device according to the second embodiment of the present invention includes a tetravalent cation element, a pentavalent cation element, and nitrogen between the third insulating film and the fourth insulating film of the selection transistor. A memory cell comprising a fifth insulating film made of an oxynitride or oxide of at least one element and having a thickness defined by a half-value width of the concentration distribution of the element of 0.1 nm to 1 nm; The second embodiment is the same as the first embodiment except that a similar insulating film is provided between the charge storage layer of the transistor and the second insulating film. Therefore, the description overlapping the first embodiment is omitted. Note that the fifth insulating film made of an oxynitride or oxide of at least one element selected from the tetravalent cation element, the pentavalent cation element, and the nitrogen is stacked on the element after forming the element. By reacting with the aluminum oxide film, aluminum is diffused and the oxide is formed. Here, the element concentration means the number of atoms per unit volume.

  FIG. 19 is a cross-sectional view of the NAND nonvolatile semiconductor memory device of this embodiment. As shown in the figure, at least one element of a tetravalent cation element, a pentavalent cation element, and nitrogen is provided between the third insulating film 102b and the fourth insulating film 106b of the selection transistor (STS1 in the figure). A fifth insulating film 112b made of oxynitride or oxide. In the present embodiment, an insulating film 112a similar to the fifth insulating film 112b is also formed between the charge storage layer 104 of the memory cell transistor (MT11 in the figure) and the second insulating film 106a.

  According to the present embodiment, the insulating film 112a and the fifth insulating film 112b made of oxynitride or oxide of at least one element selected from a tetravalent cation element, a pentavalent cation element, and nitrogen are formed by heat treatment or the like. The aluminum oxide films 106a and 106b are added by mutual diffusion. In this manner, by inserting the oxide film containing the additive element into the interface of the heterogeneous insulating film having many defects originally, the vicinity of the interface of the second insulating film 106a containing aluminum oxide as a main component and the fourth insulating film 106b A cation element can be introduced in the vicinity of the interface, and defects in the entire laminated structure can be effectively reduced, and threshold change suppression can be achieved. In addition, heat treatment is applied to the laminated structure to redistribute the additive elements so that the concentration distribution continuously changes from the heterogeneous insulating film interface and has the maximum concentration at the heterogeneous insulating film interface. The effect is maintained.

  Note that the thicknesses of the insulating film 112a and the fifth insulating film 112b, which are oxynitrides or oxides of at least one element selected from a tetravalent cation element, a pentavalent cation element, and nitrogen, are 0.1 nm to 1 nm. It is desirable that This is because if the film thickness is thinner than 0.1 nm, the additive element is not uniform in the in-plane direction but in the form of dots at the interface between the different types of insulating films, which causes variation in a fine cell. On the other hand, if the thickness exceeds 1 nm, the increase in the actual film thickness and the electrical film thickness cannot be ignored, which hinders the selection transistor miniaturization.

  In the manufacturing method of the present embodiment, in the first embodiment, after the selective removal of the charge storage layer 104 shown in FIG. 14, at least one of a tetravalent cation element, a pentavalent cation element, and nitrogen is used. A step of depositing the insulating film 112a and the fifth insulating film 112b, which are oxynitrides or oxides of these elements, may be inserted. The deposited film thickness is, for example, 0.1 nm to 2 nm. Here, the fifth insulating film 112b can be deposited by, for example, a sputtering method using a metal target or oxide target of a tetravalent or pentavalent element. Note that the method for manufacturing this film is not limited to the sputtering method, and a CVD method, an ALD method, a vapor deposition method, a laser ablation method, an MBE method, or a film forming method combining these methods is also possible. Alternatively, an insulating film having a thickness of 0.1 to 1 nm may be formed by radical nitriding the base surface. Alternatively, since nitrogen is easily segregated at an interface having a large lattice mismatch, after the fifth insulating film 112b is deposited or an upper layer of the fifth insulating film 112b is formed, an appropriate heat treatment is performed to reduce the interface to 0. An insulating film with a thickness of 1 to 1 nm may be formed. Note that the insulating film thickness described here is a film thickness defined by the half-value width of the concentration distribution of the element.

  Then, according to the present embodiment, the added cation is added from the insulating film 112a and the fifth insulating film 112b which are oxynitrides or oxides of at least one element of a tetravalent cation element, a pentavalent cation element, and nitrogen. Since the element is introduced into the upper aluminum oxide insulating film, when the aluminum oxide film is deposited on the insulating film 112a and the fifth insulating film 112b, the element which is necessarily a small component is not always positive. It does not have to be introduced in

(Third embodiment)
In the NAND-type nonvolatile semiconductor memory device according to the third embodiment of the present invention, the third insulating film of the selection transistor is a silicon oxide film, and between the fourth insulating film mainly composed of aluminum oxide. The second embodiment is the same as the first embodiment except that a silicon oxynitride film is provided. Therefore, the description overlapping the first embodiment is omitted.

  FIG. 20 is a cross-sectional view of the NAND-type nonvolatile semiconductor memory device of this embodiment. As shown in the figure, as shown in the figure, a silicon oxynitride film 114 is provided between the third insulating film 102b and the fourth insulating film 106b of the selection transistor (STS1 in the figure).

  According to the present embodiment, the silicon oxynitride film 114 containing nitrogen (N) is thus inserted into the interface of the heterogeneous insulating film having many defects, so that the fourth insulation mainly containing aluminum oxide is obtained. Nitrogen can be introduced in the vicinity of the interface of the film 106b, and defects in the entire stacked structure can be effectively reduced, and threshold change suppression can be achieved. In addition, the heat treatment is applied to the laminated structure to redistribute nitrogen so that the concentration distribution continuously changes from the interface of the different insulating film and has the maximum concentration at the interface of the different insulating film. Is maintained.

  Here, the thickness of the silicon oxynitride film 114 is desirably 0.1 nm or more and 1 nm or less. Here, if the nitriding region is thinner than 0.1 nm, N atoms are present in a locally aggregated state at the interface between the different types of insulating films, which causes variation in a fine cell. On the other hand, if the thickness exceeds 1 nm, an increase in the actual film thickness and the electrical film thickness cannot be ignored, which hinders miniaturization of the select transistor.

  In the manufacturing method of the present embodiment, in the first embodiment, the first and third insulating films are formed of silicon oxide films, and after the selective removal of the charge storage layer 104 shown in FIG. A silicon oxynitride film 114 may be formed at least on the upper part of the third insulating film 102b, which is a silicon oxide film, in at least the selection transistor region by radical nitridation or the like.

  According to the present embodiment, nitrogen is introduced from the silicon oxynitride film 114 into the upper aluminum oxide insulating film. Therefore, when depositing the aluminum oxide film, the amount of charge trapping is not necessarily reduced. Therefore, it is not necessary to positively introduce an element that becomes a small component for the purpose. In this embodiment, nitrogen may be added to the block insulating films in the memory transistor region and the select transistor region. At this time, when the charge storage layer is formed of a silicon nitride film in the memory transistor region, the step of adding nitrogen to the block insulating film hardly affects the element characteristics.

(Fourth embodiment)
The NAND nonvolatile semiconductor memory device according to the fourth embodiment of the present invention does not have a silicon nitride film (SiN) layer as a charge storage layer in the memory cell transistor region, and functions as a charge storage layer instead. There is no insulating film made of oxynitride or oxide of at least one element selected from the group consisting of tetravalent cation element, pentavalent cation element and nitrogen between the aluminum oxide layer to be formed and the underlying silicon oxide film layer. Except for this, the second embodiment is the same as the second embodiment. Therefore, the description overlapping the second embodiment is omitted.

  FIG. 21 is a cross-sectional view of the NAND-type nonvolatile semiconductor memory device of this embodiment. As shown in the drawing, the memory cell transistor MT11 is formed by a stacked structure of a first insulating film 102a made of a silicon oxide film, a second insulating film 106a made of an aluminum oxide film, and a first control gate electrode 108a. ing. Here, it is desirable that the second insulating film 106a contains as little a tetravalent cation element, a pentavalent cation element, and N (nitrogen) as possible as small components. On the other hand, the select transistor STS1 includes a third insulating film 102b made of a silicon oxide film, a fifth insulation made of an oxynitride or oxide of at least one element selected from the group consisting of a tetravalent cation element, a pentavalent cation element, and nitrogen. The film 112b is formed of a stacked structure of a fourth insulating film 106b whose main component is aluminum oxide and a second control electrode 108b. Note that in the fifth insulating film 112b, aluminum is diffused by reacting with the fourth insulating film 106b after the element is formed, and an oxide thereof is formed.

  According to the present embodiment, it is possible to reduce the amount of charge traps in the select transistor STS1 as in the second embodiment. In addition, although the charge storage layer is not explicitly formed in the memory cell transistor, as can be seen from the above experimental results (FIGS. 3 and 4), the interface formed in the aluminum oxide film / silicon oxide film When the trap captures the electric charge, the memory function can be sufficiently developed.

  Hereinafter, the manufacturing method of the present embodiment will be described focusing on the differences from the first embodiment. After the first and second insulating films are formed of a silicon oxide film, an insulating film made of an oxynitride or oxide of at least one of a tetravalent cation element, a pentavalent cation element, and nitrogen is deposited. Thereafter, this insulating film is patterned so that the insulating film remains only in the select transistor region. Thereafter, after forming the aluminum oxide film without forming the charge storage layer, the memory cell transistor and the select transistor may be formed by the same method as the manufacturing method of the first embodiment. Note that an insulating film made of an oxynitride or oxide of at least one element selected from the tetravalent cation element, the pentavalent cation element, and the nitrogen described above includes an aluminum oxide film stacked thereon after element formation. By reacting, aluminum diffuses to form an oxide thereof. Therefore, when an aluminum oxide film is deposited, it is not always necessary to positively introduce an element which is a small component.

(Fifth embodiment)
A NAND-type nonvolatile semiconductor memory device according to a fifth embodiment of the present invention includes a tetravalent cation element, a pentavalent cation element, and a silicon oxide film of a selection transistor between an insulating film whose main component is aluminum oxide. Instead of having an insulating film made of oxynitride or oxide of at least one element of nitrogen, aluminum oxide containing at least one element of tetravalent cation element, pentavalent cation element, and nitrogen as a minor component Except for using a thing, it is the same as that of 4th Embodiment. Therefore, the description overlapping with the fourth embodiment and effects is omitted.

  FIG. 22 is a cross-sectional view of the NAND-type nonvolatile semiconductor memory device of this embodiment. As shown in the drawing, the memory cell transistor MT11 is formed by a stacked structure of a first insulating film 102a made of a silicon oxide film, a second insulating film 106a made of an aluminum oxide film, and a first control gate electrode 108a. ing. Here, it is desirable that the second insulating film 106a contains as little a tetravalent cation element, a pentavalent cation element, and N (nitrogen) as possible as small components. The select transistor STS1 includes a third insulating film 102b made of a silicon oxide film, the main component being aluminum oxide, and at least one element selected from a tetravalent cation element, a pentavalent cation element, and N (nitrogen). It is formed of a stacked structure of a fourth insulating film 106b and a second control electrode 108b that are contained as a minor component.

  According to the present embodiment, in the select transistor STS1, as in the first embodiment, any one element of a tetravalent cation element and a pentavalent cation element is substantially uniformly contained in the aluminum oxide. Therefore, it is possible to achieve both low power consumption due to leakage current reduction due to reduction of bulk defects (charge traps) and suppression of threshold change due to reduction of defects (charge traps) near the aluminum oxide film interface. In addition, by distributing the additive elements together with the distribution of the bulk defects and the interface defects, it is possible to effectively reduce the defects of the entire stacked structure with the minimum addition amount. Specifically, in the selection transistor region, a distribution with an inclination so that the concentration of the additive element is maximized at the aluminum oxide film / silicon oxide film interface is preferable. A concentration gradient can be expected to reduce stress relaxation and lattice mismatch. The memory cell transistor does not have a charge storage layer. However, as in the fourth embodiment, the memory function can be sufficiently exhibited by trap charges in the aluminum oxide film / silicon oxide film. is there.

  Hereinafter, the manufacturing method of the present embodiment will be described focusing on the differences from the first embodiment. A mask material is deposited on the second insulating film 102b in the select transistor region. Next, an aluminum oxide film is deposited on the memory transistor region and the select transistor region. Next, the aluminum oxide film on the mask material is peeled off together with the mask material in the selection transistor region, whereby the second insulating film 106a in the memory cell transistor region is formed.

  Thereafter, a mask material is deposited on the memory transistor region, and tetravalent or pentavalent is formed on the memory transistor region and the selective transistor region by sputtering using a tetravalent or pentavalent element and an Al metal target or an oxide target thereof. An aluminum oxide film to which an element was added was formed. In addition, the manufacturing method of this film is not limited to the sputtering method, and a CVD method, an ALD method, a vapor deposition method, a laser ablation method, an MBE method, or a film forming method combining these methods is also possible. Alternatively, the film may be introduced by ion implantation after forming a part or all of the film thickness.

  Thereafter, the aluminum oxide film on the memory transistor region is peeled off together with the mask material. Thus, the fourth insulating film 106b in the selection transistor region is formed. Thereafter, a NAND type semiconductor nonvolatile memory device is formed by the same manufacturing method as in the first embodiment.

(Sixth embodiment)
The NAND nonvolatile semiconductor memory device according to the sixth embodiment of the present invention is different from the first embodiment in that the second oxide film of the aluminum oxide of the memory cell transistor is an aluminum oxide film and is oxidized by silicon. A block insulating film having a three-layer structure with a film sandwiched therebetween, and a fourth insulating film of aluminum oxide of the selection transistor being an insulating film having a three-layer structure in which a silicon oxide film is sandwiched between aluminum oxide films Is the same as in the first embodiment. Therefore, the description overlapping the first embodiment is omitted. The aluminum oxide film is an insulating film containing at least one element selected from a tetravalent cation element, a pentavalent cation element, and N (nitrogen) as a minor component.

  FIG. 23 is a cross-sectional view of the NAND-type nonvolatile semiconductor memory device of this embodiment. As shown in the figure, the block insulating film of the memory cell transistor MT11 is a block having a three-layer structure in which a silicon oxide film 126a is sandwiched between an aluminum oxide second insulating film 106a and an aluminum oxide second insulating film 106c. It is an insulating film. Further, the insulating film stacked on the silicon oxide film 102b of the select transistor STS1 is 3 in which the silicon oxide film 126b is sandwiched between the fourth insulating film 106b made of aluminum oxide and the fourth insulating film 106d made of aluminum oxide. The insulating film has a layer structure.

  In the memory cell transistor region, the tunnel insulating film 102a has a thickness of about 3 nm to 5 nm, the silicon nitride film as the charge storage layer 104 has a thickness of about 1 nm to 5 nm, and is formed on the charge storage layer 104 as a blocking insulating film. The aluminum oxide film 106a containing at least one element among the tetravalent cation element, the pentavalent cation element, and N (nitrogen) as a minor component has a thickness of about 4 nm to 15 nm, and is a silicon oxide film 126a sandwiched between the films. The aluminum oxide film 106c has a thickness of about 1 nm to 5 nm and contains at least one element selected from a tetravalent cation element, a pentavalent cation element, and N (nitrogen) formed on the silicon oxide film 126a as a minor component. The film thickness is about 4 nm to 15 nm.

  In the select transistor region, the tunnel insulating film 102b has a film thickness of about 3 nm to 5 nm, and at least one element selected from a tetravalent cation element, a pentavalent cation element, and N (nitrogen), which is an insulating film formed thereon. The aluminum oxide film 106b contained as a minor component has a thickness of about 4 nm to 15 nm, and the sandwiched silicon oxide film 126b has a thickness of about 1 nm to 5 nm. A tetravalent cation element formed on the silicon oxide film 126b, 5 The film thickness of the aluminum oxide film 106d containing at least one element among the valent cation element and N (nitrogen) as a minor component is about 4 nm to 15 nm.

  According to the present embodiment, the block insulating film in the memory transistor region uses a laminated film of an aluminum oxide film to which a desired element is added, a silicon oxide film, and an aluminum oxide film to which a desired element is added, It is possible to achieve both low power consumption due to reduction of leakage current due to reduction of bulk defects (charge traps) and suppression of threshold change due to reduction of defects (charge traps) near the interface of the aluminum oxide film. In addition, by distributing the additive elements together with the distribution of the bulk defects and the interface defects, it is possible to effectively reduce the defects of the entire stacked structure with the minimum addition amount. Furthermore, a favorable charge retention performance can be ensured by disposing a silicon oxide film having a larger electron barrier than the aluminum oxide film in the center of the block film.

  Hereinafter, the manufacturing method of the present embodiment will be described focusing on the differences from the first embodiment. After the charge storage layer 104 in the selection transistor region is removed, an aluminum oxide film to which a desired element is added, a silicon oxide film, and an aluminum oxide film to which a desired element is added are sequentially formed. As a method for forming the silicon oxide film, an ALD method using an organic silicon gas such as thermal oxidation or radical oxidation of polycrystalline silicon, or TDMAS (Trisdimethyl Amino Silane) and ozone as raw materials may be used.

  Thereafter, a control gate electrode material is deposited as in the step shown in FIG. 16, and a NAND type semiconductor nonvolatile memory device is formed by the same method as in the first embodiment.

(Seventh embodiment)
The NAND-type nonvolatile semiconductor memory device according to the seventh embodiment of the present invention includes an aluminum oxide film of a memory cell transistor and a select transistor and a silicon oxide film or a silicon nitride film in contact with the upper or lower side of the aluminum oxide film. Is the same as that of the sixth embodiment except that an insulating film made of an oxynitride or oxide of at least one element selected from a tetravalent cation element, a pentavalent cation element, and nitrogen is present. With this stacked structure, the portion corresponding to the block insulating film of the memory cell transistor has a six-layer structure. For the sake of process simplicity, the insulating film of the selection transistor is also in contact with the silicon oxide film, which is the original gate insulating film, so that the insulating film having the six-layer structure exists. Therefore, the description overlapping with the first and sixth embodiments is omitted.

  FIG. 24 is a cross-sectional view of the NAND-type nonvolatile semiconductor memory device of this embodiment. As shown in the figure, in the memory cell transistor MT11, a film corresponding to a block insulating film between the charge storage layer 104 and the first control electrode 108a is formed of a tetravalent cation element, a pentavalent cation element, and nitrogen from the lower layer. An insulating film 120a made of an oxynitride or oxide of at least one element, an aluminum oxide second insulating film 106a, an oxynitride of at least one element out of a tetravalent cation element and a pentavalent cation element, or 6 of the insulating film 120c made of oxide, the silicon oxide film 126a, the insulating film 120e made of at least one element selected from the group consisting of tetravalent cation element, pentavalent cation element and nitrogen, and the second insulating film 106c made of aluminum oxide. It has a layered structure. Note that in the insulating films 120a, 120c, and 120e, aluminum reacts with the second insulating films 106a and 106c after element formation, so that aluminum diffuses and oxides thereof are formed.

  In the select transistor STS1, the insulating film between the tunnel oxide film 102b and the first control electrode 108b has an oxynitride or an oxide of at least one element selected from a lower layer, a tetravalent cation element, a pentavalent cation element, and nitrogen. An insulating film 120b made of aluminum oxide, a fourth insulating film 106b made of aluminum oxide, an insulating film 120d made of oxynitride or oxide of at least one element selected from the group consisting of a tetravalent cation element, a pentavalent cation element, and nitrogen, and silicon oxide The film 126b has a six-layer structure of an insulating film 120f made of an oxynitride or oxide of at least one element selected from a tetravalent cation element, a pentavalent cation element, and nitrogen, and an aluminum oxide fourth insulating film 106d. ing. Note that in the insulating films 120b, 120d, and 120f, aluminum reacts with the fourth insulating film 106d after element formation, so that aluminum is diffused and oxides thereof are formed.

  In the memory cell transistor region, the tunnel insulating film 102a has a thickness of about 3 nm to 5 nm, the silicon nitride film as the charge storage layer 104 has a thickness of about 1 nm to 5 nm, a tetravalent cation element formed on the silicon nitride film, The insulating film 120a made of an oxynitride or oxide of at least one element of pentavalent cation element and nitrogen has a thickness of about 0.1 nm to 1 nm. The aluminum oxide film 106a formed on the insulating film 120a The film thickness is about 4 nm to 15 nm, and the film thickness of the insulating film 120c made of oxynitride or oxide of at least one element among the tetravalent cation element and the pentavalent cation element formed on the aluminum oxide film 106a. The film thickness of the silicon oxide film 126a formed on the insulating film 120c is about 0.1 nm to 1 nm. The film thickness of the insulating film 102e made of oxynitride or oxide of at least one element of tetravalent cation element, pentavalent cation element, and nitrogen formed on this silicon oxide film is about 0.1 nm to 5 nm. The film thickness of the aluminum oxide film 106c formed on the insulating film 102e is about 4 nm to 15 nm.

  The select transistor region is formed in the same manufacturing process as the memory cell transistor region except that there is no silicon nitride film that is a charge storage layer on the tunnel insulating film 102b. It is.

  According to the present embodiment, an aluminum oxide film, a silicon oxide film in which a desired element is added in a suitable concentration distribution, and an aluminum in which a desired element is added in a suitable concentration distribution to the block insulating film in the memory transistor region A laminated film of oxide films is used. For this reason, it is possible to achieve both a reduction in power consumption due to a reduction in leakage current due to a reduction in bulk defects (charge traps) and a threshold change suppression due to a reduction in defects (charge traps) near the aluminum oxide film interface. In addition, by distributing the additive elements together with the distribution of the bulk defects and the interface defects, it is possible to effectively reduce the defects of the entire stacked structure with the minimum addition amount. Furthermore, a favorable charge retention performance can be ensured by disposing a silicon oxide film having a larger electron barrier than the aluminum oxide film in the center of the block film.

  Hereinafter, the manufacturing method of the present embodiment will be described focusing on differences from the first and sixth embodiments. After removal of the charge storage layer 104 in the select transistor region, an oxynitride or oxide of at least one of a tetravalent cation element, a pentavalent cation element, and nitrogen, an aluminum oxide film, a tetravalent cation element, and a pentavalent element Cation element, oxynitride or oxide of at least one element out of nitrogen, silicon oxide film, tetravalent cation element, pentavalent cation element, oxynitride or oxide of at least one element out of nitrogen, aluminum A six-layer structure of oxide films is sequentially formed.

  Thereafter, a control gate electrode material is deposited as in the step shown in FIG. 16, and a NAND type semiconductor nonvolatile memory device is formed by the same method as in the first embodiment.

(Eighth embodiment)
In the NAND-type nonvolatile semiconductor memory device according to the eighth embodiment of the present invention, the main component is aluminum oxide between the first insulating film (tunnel insulating film) of the memory cell transistor and the charge storage layer. Yes, except that an insulating film containing at least one element of a tetravalent cation element, a pentavalent cation element, and N (nitrogen) as a minor component and an upper silicon oxide film are interposed. It is the same as the form. Therefore, the description overlapping the first embodiment is omitted. In this embodiment, a known silicon oxide film / silicon nitride film (oxynitride film) / silicon oxide film structure as a tunnel insulating film, a silicon nitride film (oxynitride film) having a so-called ONO structure is mainly composed of aluminum oxide, This corresponds to a structure in which at least one element selected from a tetravalent cation element, a pentavalent cation element, and N (nitrogen) is replaced with an insulating film containing a minor component. In other words, this is an embodiment aimed at improving the tunnel insulating film, and the purpose is different from the improvement of the block film or charge trapping layer shown in the first to seventh embodiments. Therefore, the present invention can be applied to all of the tunnel insulating film of the memory cell transistor and the gate insulating film of the selection transistor shown in the first to seventh embodiments.

  FIG. 25 is a cross-sectional view of the NAND-type nonvolatile semiconductor memory device of this embodiment. As shown in the figure, the main component of the memory cell transistor MT11 is an aluminum oxide between the first insulating film 102a and the charge storage layer 104, a tetravalent cation element, a pentavalent cation element, and N (nitrogen). ), An insulating film 130a containing at least one element as a minor component and an upper silicon oxide film 132 are interposed. That is, the tunnel insulating film has a three-layer structure of the first insulating film 102a and the aluminum oxide film 130a to which a desired element is added in a suitable concentration distribution and the silicon oxide film 132. The selection transistor STS1 includes a first insulating film 102b and a main component formed on the first insulating film 102b. The selection transistor STS1 includes at least one element selected from a tetravalent cation element, a pentavalent cation element, and N (nitrogen). It has a two-layer laminated structure with the insulating film 130b contained as a minor component.

  In the memory transistor region, the thickness of silicon oxide on the silicon substrate which is the tunnel insulating film 102a is about 1 nm to 4 nm, and the thickness of the aluminum oxide film 130a to which tetravalent or pentavalent element or nitrogen is added is 1 nm. About 5 nm, the thickness of the silicon oxide film 132 thereon is about 1 nm to 4 nm, the thickness of the silicon nitride film as the charge storage layer 104 is about 1 nm to 5 nm, a tetravalent or pentavalent element as a block insulating film, or The thickness of the aluminum oxide film 106a to which nitrogen is added is about 4 nm to 15 nm.

  In the select transistor region, the thickness of the tunnel insulating film 102b is about 3 nm to 5 nm, and the thickness of the aluminum oxide film 106a added with a tetravalent or pentavalent element as a block insulating film is about 4 nm to 15 nm.

  According to this embodiment, a laminated film of a silicon oxide film, an aluminum oxide film to which a desired element is added in a suitable concentration distribution, and a silicon oxide film are used for the tunnel insulating film in the memory transistor region. For this reason, it is possible to achieve both a reduction in power consumption due to a reduction in leakage current due to a reduction in bulk defects (charge traps) and a threshold change suppression due to a reduction in defects (charge traps) near the aluminum oxide film interface. In addition, by distributing the additive elements together with the distribution of the bulk defects and the interface defects, it is possible to effectively reduce the defects of the entire stacked structure with the minimum addition amount. Specifically, a distribution having an inclination so that the concentration of the additive element is maximized at the interface between the aluminum oxide film and the silicon oxide film is preferable. A concentration gradient can be expected to reduce stress relaxation and lattice mismatch. Furthermore, by arranging an aluminum oxide film having a smaller electron barrier than the silicon oxide film at the center of the block film, it is possible to ensure good write / erase performance as a tunnel film.

  The embodiments of the present invention have been described above with reference to specific examples. The above embodiment is merely given as an example, and does not limit the present invention. Further, in the description of the embodiment, the description of the NAND-type nonvolatile semiconductor memory device, the manufacturing method thereof, and the like that are not directly required for the description of the present invention is omitted, but the required NAND-type nonvolatile semiconductor memory device is omitted. The elements related to the conductive semiconductor memory device, the manufacturing method thereof, and the like can be appropriately selected and used.

  Further, although silicon (Si) has been described as an example of the semiconductor substrate, it is not necessarily limited to silicon (Si), but silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs). It is possible to use aluminum nitride (AlN), gallium nitride (GaN), indium antimony (InSb), or the like, or a substrate obtained by adding strain thereto.

  Further, the plane orientation of the substrate material is not necessarily limited to the (100) plane, and the (110) plane or the (111) plane can be appropriately selected.

  In addition, all NAND-type non-volatile semiconductor memory devices that include the elements of the present invention and whose design can be changed as appropriate by those skilled in the art and manufacturing methods thereof are included in the scope of the present invention. The scope of the present invention is defined by the appended claims and equivalents thereof.

1 is a cross-sectional view of a NAND nonvolatile semiconductor memory device according to a first embodiment. FIG. 2 is a chip layout diagram of the NAND-type nonvolatile semiconductor memory device according to the first embodiment. Graph showing the relationship between Vfb change after equivalent oxide thickness and stress application Al ₂ O _3. Graph showing the relationship between the Si concentration and the trapped charge density in the _Al 2 _{O 3} before and after heat treatment. It shows the Kohn-Sham level of various charge states of the respective defects in Al ₂ O _3. It shows the Kohn-Sham level of various charge states of the respective defects in Al ₂ O _3. It shows a charge trapping level of _{O i, V Al,} and _{V O} by theoretical calculation. It shows an electron level of Al ₂ O ₃ / SiO ₂ of _Al 2 _{O 3} in the gap. Al ₂ O ₃ / graph showing changes in the band diagram according to the concentration at which the SiO ₂ to _Al 2 _{O 3} was added tetravalent or pentavalent cation element. Al ₂ O ₃ / graph showing changes in the band diagram according to the concentration at which the SiO ₂ to _Al 2 _{O 3} was added tetravalent or pentavalent cation element. It shows an electron level in the case of adding N in Al ₂ O ₃ / SiO ₂ of _Al 2 _{O 3.} The figure which shows the contribution which N addition has on interstitial oxygen and Al deficiency. Process sectional drawing which shows the manufacturing method of the NAND type non-volatile memory device of 1st Embodiment. Process sectional drawing which shows the manufacturing method of the NAND type non-volatile memory device of 1st Embodiment. Process sectional drawing which shows the manufacturing method of the NAND type non-volatile memory device of 1st Embodiment. Process sectional drawing which shows the manufacturing method of the NAND type non-volatile memory device of 1st Embodiment. Process sectional drawing which shows the manufacturing method of the NAND type non-volatile memory device of 1st Embodiment. Process sectional drawing which shows the manufacturing method of the NAND type non-volatile memory device of 1st Embodiment. Sectional drawing of the NAND type non-volatile semiconductor memory device of 2nd Embodiment. Sectional drawing of the NAND type non-volatile semiconductor memory device of 3rd Embodiment. Sectional drawing of the NAND type non-volatile semiconductor memory device of 4th Embodiment. Sectional drawing of the NAND type non-volatile semiconductor memory device of 5th Embodiment. Sectional drawing of the NAND type non-volatile semiconductor memory device of 6th Embodiment. Sectional drawing of the NAND type non-volatile semiconductor memory device of 7th Embodiment. Sectional drawing of the NAND type non-volatile semiconductor memory device of 8th Embodiment.

100 Semiconductor substrate 102a First insulating film 102b Third insulating film 104 Charge storage layer 106a, c Second insulating film 106b, d Fourth insulating film 108a First control gate electrode 108b Second control gate electrode 112b 5th insulating film

Claims (15)

A semiconductor substrate includes a plurality of memory cell transistors connected in series and a selection transistor provided at an end of the plurality of memory cell transistors connected in series,
The memory cell transistor is
A first insulating film on the semiconductor substrate;
A charge storage layer on the first insulating film;
A second insulating film made of aluminum oxide on the charge storage layer;
A first control gate electrode on the second insulating film;
A first source / drain region formed in the semiconductor substrate on both sides of the first control gate electrode;
The selection transistor is:
A third insulating film on the semiconductor substrate;
A fourth insulating film which is an aluminum oxide and contains a pentavalent cation element on the third insulating film;
A second control gate electrode on the fourth insulating film;
A NAND type nonvolatile semiconductor memory device, comprising: second source / drain regions formed in the semiconductor substrate on both sides of the second control gate electrode.   2. The NAND type nonvolatile semiconductor memory device according to claim 1, wherein the concentration of the pentavalent cation element in the fourth insulating film has a distribution having a maximum value on the third insulating film side.   The NAND-type nonvolatile semiconductor memory device according to claim 1, wherein the pentavalent cation element is substantially uniformly contained in the aluminum oxide.   The film thickness defined by the half width of the concentration distribution of the pentavalent cation element, which is an aluminum oxide and contains the pentavalent cation element, between the third insulating film and the fourth insulating film. The NAND-type nonvolatile semiconductor memory device according to claim 1, further comprising a fifth insulating film having a thickness of 0.1 nm to 1 nm.   5. The NAND type nonvolatile semiconductor memory device according to claim 1, wherein the pentavalent cation element is at least one element selected from V, Nb, and Ta.   The concentration of the pentavalent cation element in the fourth insulating film is 0.015 ≦ M / (Al + M) ≦ 0.15 (M = pentavalent cation element). 6. The NAND-type nonvolatile semiconductor memory device according to 5. A semiconductor substrate includes a plurality of memory cell transistors connected in series and a selection transistor provided at an end of the plurality of memory cell transistors connected in series,
The memory cell transistor is
A first insulating film on the semiconductor substrate;
A second insulating film made of aluminum oxide on the first insulating film;
A first control gate electrode on the second insulating film;
A first source / drain region formed in the semiconductor substrate on both sides of the first control gate electrode;
The selection transistor is:
A third insulating film on the semiconductor substrate;
A fourth insulating film which is an aluminum oxide and contains a pentavalent cation element on the third insulating film;
A second control gate electrode on the fourth insulating film;
A NAND type nonvolatile semiconductor memory device, comprising: second source / drain regions formed in the semiconductor substrate on both sides of the second control gate electrode. 8. The NAND type nonvolatile semiconductor memory device according to claim 1, wherein the first insulating film and the third insulating film are a silicon oxide film or a silicon oxynitride film. A semiconductor substrate includes a plurality of memory cell transistors connected in series and a selection transistor provided at an end of the plurality of memory cell transistors connected in series,
The memory cell transistor is
A first insulating film on the semiconductor substrate;
A charge storage layer on the first insulating film;
A second insulating film made of aluminum oxide on the charge storage layer;
A first control gate electrode on the second insulating film;
A first source / drain region formed in the semiconductor substrate on both sides of the first control gate electrode;
The selection transistor is:
A third insulating film on the semiconductor substrate;
A fourth insulating film which is aluminum oxide and contains N (nitrogen) on the third insulating film;
A second control gate electrode on the fourth insulating film;
A second source / drain region formed in the semiconductor substrate on both sides of the second control gate electrode;
A NAND-type nonvolatile semiconductor memory device, wherein a concentration of N (nitrogen) in the fourth insulating film satisfies 0.02 ≦ N / (O + N) ≦ 0.4.   10. The NAND-type nonvolatile semiconductor memory device according to claim 9, wherein the N (nitrogen) concentration in the fourth insulating film has a distribution having a maximum value on the third insulating film side.   10. The NAND type nonvolatile semiconductor memory device according to claim 9, wherein the N (nitrogen) is substantially uniformly contained in the aluminum oxide.   The film thickness defined by the half-value width of the concentration distribution of N (nitrogen), which is aluminum oxide and contains N (nitrogen), between the third insulating film and the fourth insulating film. 10. The NAND type nonvolatile semiconductor memory device according to claim 9, further comprising a fifth insulating film having a thickness of 0.1 nm to 1 nm. A semiconductor substrate includes a plurality of memory cell transistors connected in series and a selection transistor provided at an end of the plurality of memory cell transistors connected in series,
The memory cell transistor is
A first insulating film on the semiconductor substrate;
A second insulating film made of aluminum oxide on the first insulating film;
A first control gate electrode on the second insulating film;
A first source / drain region formed in the semiconductor substrate on both sides of the first control gate electrode;
The selection transistor is:
A third insulating film on the semiconductor substrate;
A fourth insulating film which is aluminum oxide and contains N (nitrogen) on the third insulating film;
A second control gate electrode on the fourth insulating film;
A second source / drain region formed in the semiconductor substrate on both sides of the second control gate electrode;
A NAND-type nonvolatile semiconductor memory device, wherein a concentration of N (nitrogen) in the fourth insulating film satisfies 0.02 ≦ N / (O + N) ≦ 0.4. 14. The NAND type nonvolatile semiconductor memory device according to claim 9, wherein the first insulating film and the third insulating film are a silicon oxide film or a silicon oxynitride film. 15. The NAND type nonvolatile semiconductor memory device according to claim 9, wherein the fourth insulating film contains a tetravalent cation element or a pentavalent cation element.

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