KR100762902B1 - Method for forming metal interconnection layer of semiconductor device - Google Patents

Method for forming metal interconnection layer of semiconductor device Download PDF

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KR100762902B1
KR100762902B1 KR1020060061353A KR20060061353A KR100762902B1 KR 100762902 B1 KR100762902 B1 KR 100762902B1 KR 1020060061353 A KR1020060061353 A KR 1020060061353A KR 20060061353 A KR20060061353 A KR 20060061353A KR 100762902 B1 KR100762902 B1 KR 100762902B1
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film
metal wiring
semiconductor device
sion
photoresist
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KR1020060061353A
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Korean (ko)
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윤양한
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming a metal interconnection of a semiconductor device is provided to form a hydrophobicity reflection barrier layer having improved adhesive strength for preventing an undesired movement of a photoresist pattern by performing H2 plasma or H2 annealing process to a surface of an anti-reflection barrier. A SiON film is deposited on a material layer for a metal interconnection(24) as an anti-reflection barrier(25). A photoresist pattern defining a metal interconnection(26) and a pad area is formed by spraying, exposing and developing the photoresist on the SiON film. In a process of forming the metal interconnection, before spraying the photoresist, the H2 plasma process is performed to enhance the adhesive strength by performing hydrophobicity treatment to the SiON film.

Description

반도체 소자의 금속배선 형성방법{METHOD FOR FORMING METAL INTERCONNECTION LAYER OF SEMICONDUCTOR DEVICE}METHOD FOR FORMING METAL INTERCONNECTION LAYER OF SEMICONDUCTOR DEVICE}

도 1은 종래기술의 문제점을 보여주는 사진.1 is a photograph showing the problem of the prior art.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정별 단면도.2A through 2C are cross-sectional views illustrating processes for forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

21 : 반도체 기판 22 : 절연막21 semiconductor substrate 22 insulating film

23 : 베리어막 24 : 금속배선용 물질막23: barrier film 24: material film for metal wiring

25 : 반사방지막 25a : 소수성 반사방지막25: antireflection film 25a: hydrophobic antireflection film

26 : 금속배선26: metal wiring

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 보다 상세하게는, 반사방지막의 소수성 처리를 통해 상기 반사방지막과 감광막과의 접착력을 향상시켜 소자 특성을 개선할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, to form a metal wiring of a semiconductor device capable of improving device characteristics by improving the adhesion between the antireflection film and the photosensitive film through hydrophobic treatment of the antireflection film. It is about a method.

주지된 바와 같이, 금속배선의 재료로서는 전기 전도도가 매우 우수한 알루미늄(Al)이 주로 이용되고 있으며, 알루미늄 배선은 물리기상증착(Physical Vapor Deposition : 이하, PVD) 공정에 의한 알루미늄의 증착 및 패터닝을 통해 형성하고 있다. 또한, 상기 알루미늄 배선을 포함한 통상의 금속배선의 형성시에는 실질적인 배선 재료의 하부에 베리어막(Barrier Layer)을 배치시키고, 그리고, 상부에는 반사방지막(Anti Reflective Coating layer)을 배치시킨 상태로 형성하고 있다.As is well known, aluminum (Al), which has excellent electrical conductivity, is mainly used as a material for metal wiring, and aluminum wiring is formed through deposition and patterning of aluminum by a physical vapor deposition (PVD) process. Forming. In addition, in forming a normal metal wiring including the aluminum wiring, a barrier layer is disposed under a substantial wiring material, and an anti-reflective coating layer is disposed on a top. have.

여기서, 상기 베리어막은 배선 재료, 예를 들어, 알루미늄막의 접착력를 증대시키면서, 알루미늄과 기판 실리콘간의 반응이 일어나는 것을 방지하기 위해 형성되는 것으로서 통상 티타늄/티타늄질화(Ti/TiN)막이 이용되고 있으며, 상기 반사방지막으로는 통상 SiON막이 이용되고 있다.Here, the barrier film is formed to prevent the reaction between the aluminum and the substrate silicon while increasing the adhesion of the wiring material, for example, the aluminum film, and a titanium / titanium nitride (Ti / TiN) film is generally used. As the prevention film, a SiON film is usually used.

그러나, 상기 SiON막은 상기 SiON막 상에 금속배선 및 패드 영역을 한정하기 위해 형성되는 감광막과의 접착력이 좋지 않아, 상기 감광막 패턴이 원치 않는 부분으로 이동하는 현상이 발생하게 된다. 상기 감광막 패턴이 이동되면, 도 1에 도시된 바와 같이, 후속 식각 공정시 금속배선과 패드 영역이 붙게 되어 전기적 단락(Short)이 유발되며, 이때문에, 소자 특성이 열화된다는 문제점이 있다.However, the SiON film does not have good adhesion to the photoresist film formed on the SiON film to define the metal wiring and pad regions, and thus the photoresist pattern is moved to an undesired portion. When the photoresist pattern is moved, as shown in FIG. 1, the metal wiring and the pad region are attached to each other during a subsequent etching process, thereby causing an electrical short, thereby degrading device characteristics.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, SiON막과 감광막의 접착력을 향상시켜 상기 감광막 패턴의 이동을 억제할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of suppressing the movement of the photosensitive film pattern by improving the adhesion between the SiON film and the photosensitive film, which is devised to solve the conventional problems as described above. There is this.

또한, 본 발명은 상기 감광막 패턴의 이동을 억제함으로써 전기적 단락을 방 지하여 소자 특성을 개선할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 다른 목적이 있다.In addition, another object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of improving device characteristics by preventing electrical short circuits by suppressing movement of the photoresist pattern.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 금속배선 형성방법은, 금속배선용 물질막 상에 반사방지막으로서 SiON막을 증착하는 단계; 및 상기 SiON막 상에 감광막을 도포, 노광 및 현상해서 금속배선 및 패드 영역을 한정하는 감광막 패턴을 형성하는 단계;를 포함하는 반도체 소자의 금속배선 형성방법에 있어서, 상기 감광막의 도포 전, 상기 SiON막을 H2 플라즈마 처리를 통해 소수성 처리하여 상기 감광막과의 접착력을 향상시킨다.
여기서, 상기 H2 플라즈마 처리는, 상기 SiON막의 증착과 인-시튜(In-Situ)로 수행한다.
상기 H2 플라즈마 처리는 0.1∼10Torr의 압력과 100∼500℃의 온도로 수행한다.
상기 H2 플라즈마 처리는 10∼2000sccm의 H2 가스와 50∼2000W의 플라즈마 파워를 사용하여 수행한다.
또한, 상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 금속배선 형성방법은, 금속배선용 물질막 상에 반사방지막으로서 SiON막을 증착하는 단계; 및 상기 SiON막 상에 감광막을 도포, 노광 및 현상해서 금속배선 및 패드 영역을 한정하는 감광막 패턴을 형성하는 단계;를 포함하는 반도체 소자의 금속배선 형성방법에 있어서, 상기 감광막의 도포 전, 상기 SiON막을 H2 어닐링을 통해 소수성 처리하여 상기 감광막과의 접착력을 향상시킨다.
여기서, 상기 H2 어닐링은, 상기 SiON막의 증착과 익스-시튜(Ex-Situ)로 수행한다.
상기 H2 어닐링은 1∼450℃의 온도에서 100∼10000sccm의 H2 가스를 사용하여 수행한다.
상기 H2 어닐링은 H2 가스와 N2 및 Ar 가스를 함께 사용하여 수행한다.Method of forming a metal wiring of the semiconductor device of the present invention for achieving the above object comprises the steps of: depositing a SiON film as an antireflection film on the material film for metal wiring; And forming a photoresist pattern defining a metal wiring and a pad region by coating, exposing and developing a photoresist on the SiON film, wherein the method for forming a metal wiring of a semiconductor device comprises: before applying the photoresist, the SiON The film is hydrophobized through H 2 plasma treatment to improve adhesion to the photosensitive film.
Here, the H 2 plasma treatment is performed by deposition of the SiON film and In-Situ.
The H 2 plasma treatment is performed at a pressure of 0.1 to 10 Torr and a temperature of 100 to 500 ° C.
The H 2 plasma treatment is performed using 10 to 2000 sccm of H 2 gas and 50 to 2000 W of plasma power.
In addition, the method for forming a metal wiring of the semiconductor device of the present invention for achieving the above object comprises the steps of: depositing a SiON film as an antireflection film on the material film for metal wiring; And forming a photoresist pattern defining a metal wiring and a pad region by coating, exposing and developing a photoresist on the SiON film, wherein the method for forming a metal wiring of a semiconductor device comprises: before applying the photoresist, the SiON The film is hydrophobized through H 2 annealing to improve adhesion to the photosensitive film.
Here, the H 2 annealing is performed by the deposition of the SiON film and Ex-Situ.
The H 2 annealing is carried out using H 2 gas of 100 to 10000 sccm at a temperature of 1 to 450 ° C.
The H 2 annealing is performed using H 2 gas together with N 2 and Ar gas.

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(실시예)(Example)

이하에서는, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

먼저, 본 발명의 기술적 원리를 간략하게 설명하면, 본 발명은 반사방지막으로서 SiON막을 증착한 다음, 상기 SiON막 상에 감광막을 도포하기 전에 SiON막의 표면을 소수성 처리한다.First, briefly describing the technical principle of the present invention, the present invention deposits a SiON film as an antireflection film, and then hydrophobizes the surface of the SiON film before applying the photosensitive film on the SiON film.

이렇게 하면, 상기 SiON막과 감광막의 접착력이 향상되어 상기 감광막으로 이루어진 감광막 패턴의 이동이 억제되므로 전기적 단락을 방지할 수 있으며, 이를 통해, 소자 특성을 개선할 수 있다.In this case, since the adhesion between the SiON film and the photoresist film is improved, the movement of the photoresist pattern made of the photoresist film is suppressed, thereby preventing an electrical short circuit, thereby improving device characteristics.

자세하게, 도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.In detail, FIGS. 2A to 2C are cross-sectional views illustrating processes for forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention.

도 2a를 참조하면, 소정의 하부구조물(도시안됨)이 형성된 반도체 기판(21) 상에 절연막(22)을 증착한다. 그 다음, 상기 절연막 상에 베리어막(23), 금속배선용 물질막(24) 및 반사방지막(25)을 차례로 증착한다.Referring to FIG. 2A, an insulating film 22 is deposited on a semiconductor substrate 21 on which a predetermined substructure (not shown) is formed. Next, the barrier layer 23, the metal layer 24 and the antireflection layer 25 are sequentially deposited on the insulating layer.

여기서, 상기 베리어막은 상기 금속배선용 물질막(24)의 접착력를 증대시키면서, 금속배선용 물질막(24)과 기판(21) 실리콘 간의 반응이 일어나는 것을 방지하기 위해 형성되는 것으로서 통상 티타늄/티타늄질화(Ti/TiN)막으로 형성한다. 이 때, 상기 티타늄막은 80∼120Å, 바람직하게는, 100Å 정도의 두께로 형성하며, 상기 티타늄질화막은 220∼260Å, 바람직하게는, 240Å 정도의 두께로 형성한다.Here, the barrier film is formed to prevent the reaction between the metallization material layer 24 and the substrate 21 silicon while increasing the adhesive force of the metallization material layer 24, and is generally titanium / titanium nitride (Ti / TiN) film. At this time, the titanium film is formed to a thickness of 80 to 120 kPa, preferably about 100 kPa, and the titanium nitride film is formed to a thickness of 220 to 260 kPa, preferably 240 kPa.

그리고, 상기 금속배선용 물질막(24)으로는 전기 전도도가 매우 우수한 알루미늄(Al)막을 형성하며, 상기 알루미늄막은 PVD(Physical Vapor Deposition) 방식을 통해 3500∼4500Å, 바람직하게는, 4000Å 정도의 두께로 형성한다. 또한, 상기 반사방지막(25)으로는 SiON막을 형성한다.The metal wiring material film 24 forms an aluminum (Al) film having excellent electrical conductivity, and the aluminum film has a thickness of 3500 to 4500 mV, preferably 4000 mV through a physical vapor deposition (PVD) method. Form. In addition, a SiON film is formed as the anti-reflection film 25.

도 2b를 참조하면, 상기 반사방지막에 대해 H2 플라즈마 처리를 수행하여 소수성 반사방지막(25a)을 형성한다. 이때, 상기 H2 플라즈마 처리는 인-시튜(In-Situ) 방식으로 H2 가스를 플로우시킨 다음, 플라즈마를 이용해 상기 반사방지막의 표면에 H2 플라즈마 처리를 수행한다. Referring to FIG. 2B, a hydrophobic antireflection film 25a is formed by performing H 2 plasma treatment on the antireflection film. In this case, the H 2 plasma treatment flows H 2 gas in an in-situ manner, and then performs H 2 plasma treatment on the surface of the anti-reflection film using plasma.

여기서, 상기 H2 플라즈마 처리를 통해 상기 SiON막으로 이루어진 반사방지막의 표면이 Si-H의 결합을 갖게 되어 소수성 반사방지막(25a)이 형성되며, 상기 소수성 반사방지막(25a)은 후속으로 형성될 감광막 패턴과의 접착력이 우수하므로 상기 감광막 패턴의 이동이 억제된다. 따라서, 상기 감광막 패턴의 이동으로 인한 전기적 단락을 방지할 수 있으므로, 소자 특성을 개선할 수 있다.Here, the surface of the anti-reflection film made of the SiON film has a Si-H bond through the H 2 plasma treatment to form a hydrophobic anti-reflection film 25a, and the hydrophobic anti-reflection film 25a is subsequently formed. Since the adhesive force with the pattern is excellent, the movement of the photosensitive film pattern is suppressed. Therefore, an electrical short circuit due to the movement of the photosensitive film pattern can be prevented, and thus device characteristics can be improved.

이때, 상기 H2 플라즈마 처리는 0.1∼10Torr 정도의 압력과 100∼500℃ 정도의 온도에서 10∼2000sccm의 H2 가스와 50∼2000W의 플라즈마 파워를 사용하여 수행된다.At this time, the H 2 plasma treatment is performed using 10 to 2000 sccm of H 2 gas and 50 to 2000 W of plasma power at a pressure of about 0.1 to 10 Torr and a temperature of about 100 to 500 ° C.

도 2c를 참조하면, 상기 소수성 반사방지막(25a) 상에 감광막(도시안됨)을 도포한 다음, 상기 감광막을 노광 및 현상하여 금속배선 및 패드 영역을 한정하는 감광막 패턴을 형성한다. 이어서, 상기 감광막 패턴을 식각 마스크로 이용해서 상기 소수성 반사방지막(25a), 금속배선용 물질막(24) 및 베리어막(23)을 식각한 후, 상기 감광막 패턴을 제거하여 금속배선(26)을 형성한다.Referring to FIG. 2C, a photoresist (not shown) is coated on the hydrophobic antireflection film 25a, and then the photoresist is exposed and developed to form a photoresist pattern defining a metal wiring and a pad region. Subsequently, the hydrophobic antireflection film 25a, the metal wiring material film 24 and the barrier film 23 are etched using the photoresist pattern as an etching mask, and then the photoresist pattern is removed to form the metal wiring 26. do.

여기서, 본 발명은 금속배선용 물질막 상에 반사방지막으로서 형성된 SiON막의 표면을 H2 플라즈마 처리함으로써 감광막과의 접착력이 개선된 소수성 반사방지막을 형성할 수 있으며, 상기 소수성 반사방지막 상에 감광막을 도포함으로써 감광막의 원치않는 이동을 억지할 수 있다. 따라서, 상기 감광막의 이동으로 인한 전기적 단락(Short)을 방지하여 소자 특성을 향상시킬 수 있다.Here, the present invention can form a hydrophobic antireflection film having improved adhesion to the photosensitive film by H 2 plasma treatment of the surface of the SiON film formed as an antireflection film on the metallization material film, and by applying a photoresist film on the hydrophobic antireflection film Undesired movement of the photoresist film can be suppressed. Therefore, it is possible to prevent the electrical short (Short) due to the movement of the photosensitive film to improve the device characteristics.

한편, 본 발명의 일실시예에서는 인-시튜(In-Situ) 방식으로 상기 반사방지막 표면에 H2 플라즈마 처리를 수행함으로써 소수성 반사방지막을 형성하였지만, 본 발명의 다른 실시예로서 익스-시튜(Ex-Situ) 방식으로 반사방지막에 H2 어닐링을 수행함으로써 소수성 반사방지막을 형성할 수 있다.Meanwhile, in one embodiment of the present invention, a hydrophobic antireflection film was formed by performing an H 2 plasma treatment on the surface of the antireflection film in an in-situ method, but as another embodiment of the present invention, Ex-situ A hydrophobic antireflection film can be formed by performing H 2 annealing on the antireflection film in the -Situ) manner.

여기서, 상기 H2 어닐링을 통해 반사방지막으로서 형성된 SiON막 표면의 Si-OH의 결합이 깨지게 되며, 대신 상기 OH가 H로 치환되어 상기 소수성 반사방지막이 형성된다. 이때, 상기 H2 어닐링은 1∼450℃의 온도에서 100∼10000sccm의 H2 가스를 사용하여 수행하며, 상기 H2 가스와 함께 N2 및 Ar 가스를 함께 사용하는 것도 가능하다.Here, the bond of Si-OH on the surface of the SiON film formed as the antireflection film is broken through the H 2 annealing, and instead, the OH is substituted with H to form the hydrophobic antireflection film. At this time, the H 2 annealing is performed using a H 2 gas of 100-10000sccm at a temperature of 1 ~ 450 ℃, it is also possible to use N 2 and Ar gas together with the H 2 gas.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 SiON막으로 형성된 반사방지막의 표면에 H2 플라즈마 처리, 또는, H2 어닐링을 수행함으로써 감광막과의 접착력이 개선된 소수성 반사방지막을 형성할 수 있다.As described above, the present invention can form a hydrophobic antireflection film having improved adhesion to the photosensitive film by performing H 2 plasma treatment or H 2 annealing on the surface of the antireflection film formed of the SiON film.

또한, 본 발명은 상기 소수성 반사방지막 상에 감광막 패턴을 형성함으로써 상기 감광막 패턴의 원치 않는 이동을 억제할 수 있으며, 이를 통해, 상기 감광막 패턴의 이동으로 인해 유발되는 전기적 단락을 방지하여 소자 특성을 향상시킬 수 있다.In addition, the present invention can suppress the unwanted movement of the photosensitive film pattern by forming a photosensitive film pattern on the hydrophobic antireflection film, thereby improving the device characteristics by preventing an electrical short circuit caused by the movement of the photosensitive film pattern You can.

Claims (8)

금속배선용 물질막 상에 반사방지막으로서 SiON막을 증착하는 단계; 및Depositing a SiON film as an antireflection film on the material film for metallization; And 상기 SiON막 상에 감광막을 도포, 노광 및 현상해서 금속배선 및 패드 영역을 한정하는 감광막 패턴을 형성하는 단계;Coating, exposing and developing a photoresist film on the SiON film to form a photoresist pattern defining a metal wiring and a pad region; 를 포함하는 반도체 소자의 금속배선 형성방법에 있어서, In the metal wiring forming method of a semiconductor device comprising: 상기 감광막의 도포 전, 상기 SiON막을 H2 플라즈마 처리를 통해 소수성 처리하여 상기 감광막과의 접착력을 향상시키는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of forming a metal wiring of the semiconductor device, characterized in that before the application of the photosensitive film, the SiON film is hydrophobized by H 2 plasma treatment to improve adhesion to the photosensitive film. 제 1 항에 있어서,The method of claim 1, 상기 H2 플라즈마 처리는, 상기 SiON막의 증착과 인-시튜(In-Situ)로 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The H 2 plasma treatment is performed by depositing the SiON film and In-Situ. 제 1 항에 있어서,The method of claim 1, 상기 H2 플라즈마 처리는 0.1∼10Torr의 압력과 100∼500℃의 온도로 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The H 2 plasma treatment is performed at a pressure of 0.1 to 10 Torr and a temperature of 100 to 500 ° C. 제 1 항에 있어서,The method of claim 1, 상기 H2 플라즈마 처리는 10∼2000sccm의 H2 가스와 50∼2000W의 플라즈마 파워를 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The H 2 plasma treatment is performed using 10 to 2000 sccm of H 2 gas and 50 to 2000 W of plasma power. 금속배선용 물질막 상에 반사방지막으로서 SiON막을 증착하는 단계; 및Depositing a SiON film as an antireflection film on the material film for metallization; And 상기 SiON막 상에 감광막을 도포, 노광 및 현상해서 금속배선 및 패드 영역을 한정하는 감광막 패턴을 형성하는 단계;Coating, exposing and developing a photoresist film on the SiON film to form a photoresist pattern defining a metal wiring and a pad region; 를 포함하는 반도체 소자의 금속배선 형성방법에 있어서, In the metal wiring forming method of a semiconductor device comprising: 상기 감광막의 도포 전, 상기 SiON막을 H2 어닐링을 통해 소수성 처리하여 상기 감광막과의 접착력을 향상시키는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of forming a metal wiring of the semiconductor device, characterized in that before the application of the photosensitive film, the SiON film is hydrophobicly treated through H 2 annealing to improve adhesion to the photosensitive film. 제 5 항에 있어서,The method of claim 5, 상기 H2 어닐링은, 상기 SiON막의 증착과 익스-시튜(Ex-Situ)로 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The H 2 annealing is performed by depositing and ex-situ the SiON film. 제 5 항에 있어서,The method of claim 5, 상기 H2 어닐링은 1∼450℃의 온도에서 100∼10000sccm의 H2 가스를 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The H 2 annealing is performed using a H 2 gas of 100 to 10000 sccm at a temperature of 1 to 450 ℃ metal wiring forming method of a semiconductor device. 제 5 항에 있어서,The method of claim 5, 상기 H2 어닐링은 H2 가스와 N2 및 Ar 가스를 함께 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The H 2 annealing is a metal wiring forming method of a semiconductor device, characterized in that performed using a combination of H 2 gas and N 2 and Ar gas.
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US9772555B2 (en) 2015-06-02 2017-09-26 Samsung Electronics Co., Ltd. Methods of forming patterns using photoresists

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JPH0955351A (en) * 1995-08-15 1997-02-25 Sony Corp Manufacture of semiconductor device

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JPH0955351A (en) * 1995-08-15 1997-02-25 Sony Corp Manufacture of semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9772555B2 (en) 2015-06-02 2017-09-26 Samsung Electronics Co., Ltd. Methods of forming patterns using photoresists

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