KR100840641B1 - Method for Forming Semiconductor Device - Google Patents

Method for Forming Semiconductor Device Download PDF

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KR100840641B1
KR100840641B1 KR1020060109319A KR20060109319A KR100840641B1 KR 100840641 B1 KR100840641 B1 KR 100840641B1 KR 1020060109319 A KR1020060109319 A KR 1020060109319A KR 20060109319 A KR20060109319 A KR 20060109319A KR 100840641 B1 KR100840641 B1 KR 100840641B1
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film
forming
aluminum
silver
torr
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KR20080041345A (en
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이재석
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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Abstract

본 발명은 반도체 기판에 산화막을 형성하고, 상기 산화막 상부에 제1 Ti/TiN막을 형성하는 단계; 상기 제1 Ti/TiN막 상부에 층간 금속막을 형성하는 단계; 상기 층간 금속막 상부에 제2 Ti/TiN막을 형성하는 단계; 상기 산화막이 일부 노출되도록 건식식각 공정을 이용하여 상기 제2 Ti/TiN막, 상기 층간 금속막 및 상기 제1 Ti/TiN 막을 선택적으로 식각하여 패턴을 형성하는 단계; 상기 패턴을 포함하는 상기 반도체 기판 전면에 알루미늄(Al)막을 형성하는 단계; 및 상기 알루미늄(Al)막을 질산화시켜 DARC막을 형성하는 단계를 포함하는 반도체 소자 형성 방법에 관한 것이다.The present invention includes forming an oxide film on a semiconductor substrate and forming a first Ti / TiN film on the oxide film; Forming an interlayer metal film on the first Ti / TiN film; Forming a second Ti / TiN film on the interlayer metal film; Forming a pattern by selectively etching the second Ti / TiN film, the interlayer metal film, and the first Ti / TiN film by using a dry etching process to partially expose the oxide film; Forming an aluminum (Al) film on an entire surface of the semiconductor substrate including the pattern; And nitriding the aluminum (Al) film to form a DARC film.

이종금속접촉 부식 Dissimilar Metal Contact Corrosion

Description

반도체 소자 형성 방법{Method for Forming Semiconductor Device}Method for Forming Semiconductor Device {Method for Forming Semiconductor Device}

도 1a 내지 도 1f는 본 발명에 따른 반도체 소자 형성 방법을 설명하기 위한 단면도.1A to 1F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

*** 도면의 주요 부분에 대한 부호의 설명 ****** Explanation of symbols for the main parts of the drawing ***

100 : 반도체 기판 102 : 산화막100 semiconductor substrate 102 oxide film

104 : 제1 Ti/TiN막 105 : 층간 금속막104: first Ti / TiN film 105: interlayer metal film

106 : 제1 은막 107 : 패턴106: first silver film 107: pattern

108 : 제1 알루미늄막 110 : 제2 은막108: first aluminum film 110: second silver film

112 : 제2 알루미늄막 114 : 제3 은막112: second aluminum film 114: third silver film

116 : 제3 알루미늄막 118 : 제4 은막116: third aluminum film 118: fourth silver film

120 : 제2 Ti/TiN막 122a : DARC막120: second Ti / TiN film 122a: DARC film

본 발명은 반도체소자 형성 방법에 관한 것으로, 특히, 알루미늄(Al)막과 은(Ag)막 사이에서 발생하는 이종금속접촉 부식을 방지하는 반도체 소자 형성 방법에 관한 것이다.The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a semiconductor device for preventing dissimilar metal contact corrosion occurring between an aluminum (Al) film and a silver (Ag) film.

알루미늄(Al) 소재는 반도체 소자의 제작을 위한 여러 가지의 단위 공정 중 금속공정(metallization)에 널리 사용된다. 알루미늄 합금으로, 예컨대, Al-실리콘(Si), Al-구리(Cu), Al-Si-Cu, Al-티타늄(Ti), 그리고 Al-갈륨(Ga) 등이 콘택 홀(contact hole) 매립 및 배선 형성을 위하여 쓰이는데, 이렇게 알루미늄 합금을 사용하는 것은 소자의 전기적 특성을 향상시키고 신뢰성을 개선시키는 목적을 위해서이다.Aluminum (Al) is widely used in metallization among various unit processes for manufacturing semiconductor devices. As aluminum alloys, for example, Al-silicon (Si), Al-copper (Cu), Al-Si-Cu, Al-titanium (Ti), and Al-gallium (Ga), etc. It is used for wiring formation, and the use of aluminum alloy is for the purpose of improving the electrical characteristics and the reliability of the device.

구리(Cu)를 혼합한 알루미늄 합금은 Al2Cu 형태로 그레인 바운더리(grain boundary)에 석출되어 알루미늄 원자의 마이그레이션(migration)을 저지함으로써, 일렉트로마이그레이션(EM:Electro-Migration) 신뢰성 특성을 향상시키는 것으로 널리 알려져 있다.Copper (Cu) mixed aluminum alloys are deposited on grain boundaries in the form of Al 2 Cu to prevent migration of aluminum atoms, thereby improving electro-migration (EM) reliability characteristics. It is widely known.

그러나, 알루미늄 합금을 배선의 재료로 사용하는 경우에서는 알루미늄의 부식(corrosion)이 문제가 되는데 이 부식은 알루미늄층이 예를 들어 산소에 노출됨으로써 발생할 수 있다.However, when aluminum alloy is used as the wiring material, corrosion of aluminum becomes a problem, which may be caused by the aluminum layer being exposed to oxygen, for example.

또한, 금속배선의 패터닝 공정에서 주로 사용되는 소스 가스(source gas)인 BCl3에 의해 염소(Cl)가 완전히 제거되지 않아 부식이 발생하기도 하고, 물기나 습한 분위기에서 알루미늄의 전위(potential) 차이에 의한 이종금속접촉 부식(galvanic corrosion)이 발생하기도 한다.In addition, chlorine (Cl) is not completely removed by BCl 3 , a source gas mainly used in the patterning process of metallization, and corrosion may occur. Galvanic corrosion may occur due to dissimilar metals.

특히, 이종금속접촉 부식은 패키징(packaging)에서 와이어 본딩(wire bonding)을 위하여 패드를 오픈하게 되는데, 이때 알루미늄(Cu를 첨가한 알루미늄 합금)이 드러나게 되고 Al2Cu 또는 Cu 석축물이 그레인 바운더리에 존재할 경우 그 주위 부분과 석출이 일어난 부분에서의 전위차로 인해 이종금속 접촉부식이 발생한다.In particular, dissimilar metal contact corrosion causes pads to be opened for wire bonding in packaging, where aluminum (aluminum alloy with Cu) is revealed and Al 2 Cu or Cu deposits on the grain boundary. If present, dissimilar metal contact corrosion occurs due to the potential difference between the surrounding part and the precipitated part.

본 발명은 상술한 바와 같은 종래 기술의 문제점을 해결하기 위하여 제안된 것으로, 알루미늄(Al)막과 은(Ag)막 사이에서 발생하는 이종금속접촉 부식을 방지하는 반도체 소자 형성 방법을 제공하는 데 목적이 있다.The present invention has been proposed to solve the problems of the prior art as described above, and an object of the present invention is to provide a method for forming a semiconductor device for preventing dissimilar metal contact corrosion occurring between an aluminum (Al) film and a silver (Ag) film. There is this.

전술한 목적을 달성하기 위한 본 발명의 특징은 반도체 기판에 산화막을 형성하고, 상기 산화막 상부에 제1 Ti/TiN막을 형성하는 단계; 상기 제1 Ti/TiN막 상부에 층간 금속막을 형성하는 단계; 상기 층간 금속막 상부에 제2 Ti/TiN막을 형성하는 단계; 상기 산화막이 일부 노출되도록 건식식각 공정을 이용하여 상기 제2 Ti/TiN막, 상기 층간 금속막 및 상기 제1 Ti/TiN 막을 선택적으로 식각하여 패턴을 형성하는 단계; 상기 패턴을 포함하는 상기 반도체 기판 전면에 알루미늄(Al)막을 형성하는 단계; 및 상기 알루미늄(Al)막을 질산화시켜 DARC막을 형성하는 단계를 포함하는 반도체 소자 형성 방법에 관한 것이다.A feature of the present invention for achieving the above object is the step of forming an oxide film on the semiconductor substrate, and forming a first Ti / TiN film on the oxide film; Forming an interlayer metal film on the first Ti / TiN film; Forming a second Ti / TiN film on the interlayer metal film; Forming a pattern by selectively etching the second Ti / TiN film, the interlayer metal film, and the first Ti / TiN film by using a dry etching process to partially expose the oxide film; Forming an aluminum (Al) film on an entire surface of the semiconductor substrate including the pattern; And nitriding the aluminum (Al) film to form a DARC film.

본 발명에서 상기 알루미늄(Al)막은, (CH3)2AlH, (CH3)3Al 및 I-(C4H9)3Al를 ALD(atomic layer deposition)방법 또는 CVD(chemical vapor depostion)방법을 이용하여 형성하는 것을 특징으로 한다.In the present invention, the aluminum (Al) film, (CH3) 2AlH, (CH3) 3Al and I- (C4H9) 3Al is formed by using an atomic layer deposition (ALD) method or a chemical vapor depostion (CVD) method do.

본 발명에서 상기 층간 금속막은, ALD(atomic layer deposition) 방법을 이용하여 상기 제1 Ti/TiN막 상부에 제1 은(Ag)막, 제1 알루미늄(Al)막, 제2 은(Ag)막, 제2 알루미늄(Al)막, 제3 은(Ag)막, 제3 알루미늄(Al)막 및 제4 은(Ag)막을 순차적으로 형성하는 것을 특징으로 한다. In the present invention, the interlayer metal film may include a first silver (Ag) film, a first aluminum (Al) film, and a second silver (Ag) film on the first Ti / TiN film by using an atomic layer deposition (ALD) method. And a second aluminum (Al) film, a third silver (Ag) film, a third aluminum (Al) film, and a fourth silver (Ag) film are sequentially formed.

본 발명에서 상기 ALD(atomic layer deposition) 방법은, (CH3)2AlH, (CH3)3Al 및 I-(C4H9)3Al를 소스로 하여 상기 제1 알루미늄(Al)막 내지 제4 알루미늄(Al)막을 형성하고 AgNO3 또는 Ag2NH를 소스로 하여 상기 제1 은(Ag)막 내지 상기 제3 은(Ag)막을 형성하는 것을 특징으로 한다.In the present invention, the atomic layer deposition (ALD) method includes forming the first aluminum (Al) to fourth aluminum (Al) films using (CH 3) 2 AlH, (CH 3) 3 Al, and I- (C 4 H 9) 3 Al as a source. And the first silver (Ag) film to the third silver (Ag) film are formed using AgNO 3 or Ag 2 NH as a source.

본 발명에서 상기 제1 은(Ag)막 내지 제4 은(Ag)막 및 제1 알루미늄(Al)막 내지 제3 알루미늄(Al)막의 두께는, 100Å~1000Å의 두께로 각각 형성되는 것을 특징으로 한다.In the present invention, the thicknesses of the first silver (Ag) film to the fourth silver (Ag) film and the first aluminum (Al) film to the third aluminum (Al) film are formed to have a thickness of 100 kPa to 1000 kPa, respectively. do.

본 발명에서 상기 건식식각 공정 조건은, 9E-4 torr 내지 11E-4 torr의 압력 공정 조건을 갖는 것을 특징으로 한다.In the present invention, the dry etching process conditions are characterized in that the pressure process conditions of 9E-4 torr to 11E-4 torr.

본 발명에서 상기 DARC막 형성 단계는, 9E-3 torr 내지 11E-3 torr의 압력 및 350℃ 내지 450℃의 온도에서 불활성 가스 및 N2O를 이용하는 것을 특징으로 한다.In the present invention, the step of forming the DARC film is characterized by using an inert gas and N 2 O at a pressure of 9E-3 torr to 11E-3 torr and a temperature of 350 ° C to 450 ° C.

본 발명에서 상기 DARC막 형성 단계는, 9E-3 torr 내지 11E-3 torr의 압력 및 350℃ 내지 450℃의 온도에서 불활성 가스, O2 및 NH3를 이용하는 것을 특징으로 한다.In the present invention, the step of forming the DARC film is characterized in that using an inert gas, O2 and NH3 at a pressure of 9E-3 torr to 11E-3 torr and a temperature of 350 ℃ to 450 ℃.

본 발명에서 상기 DARC막 형성 단계는, 9E-3 torr 내지 11E-3 torr의 압력 및 350℃ 내지 450℃의 온도에서 불활성 가스, N2 및 O2를 이용하는 것을 특징으로 한다.In the present invention, the step of forming the DARC film is characterized in that using an inert gas, N2 and O2 at a pressure of 9E-3 torr to 11E-3 torr and a temperature of 350 ℃ to 450 ℃.

본 발명에서 상기 DARC막은, 상기 불활성 가스 및 N20를 플라즈마로 형성하여 상기 알루미늄(Al)막을 질산화시킨 AlxOyNz로 형성되는 것을 특징으로 한다.In the present invention, the DARC film is formed of AlxOyNz in which the inert gas and N20 are formed by plasma to nitrate the aluminum (Al) film.

본 발명에서 상기 DARC막은, 상기 불활성 가스, NH3 및 02를 플라즈마로 형성하여 상기 알루미늄(Al)막을 질산화시킨 AlxOyNz로 형성되는 것을 특징으로 한다.In the present invention, the DARC film is formed of Al x O y N z in which the inert gas, NH 3 and 02 are formed by plasma to nitrate the aluminum (Al) film.

본 발명에서 상기 DARC막은, 상기 불활성 가스, N2 및 02를 플라즈마로 형성하여 상기 알루미늄(Al)막을 질산화시킨 AlxOyNz로 형성되는 것을 특징으로 한다.In the present invention, the DARC film is formed of AlxOyNz in which the inert gas, N2 and 02 are formed by plasma to nitrate the aluminum (Al) film.

이하에서 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자 형성방법에 대해서 상세히 설명한다.Hereinafter, a method of forming a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1f는 본 발명에 따른 반도체 소자 형성방법을 설명하기 위한 단면도들이다.1A to 1F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

도 1a에서 나타낸 바와 같이, 반도체 기판(100)상에 소정의 두께를 갖는 산화막(102)을 형성하고, 산화막(102) 상부에 스퍼터링(sputtering) 방법으로 난반사 방지막(ARC:Anti Reflective Coating)인 제1 Ti/TiN막(104)을 형성한다.As shown in FIG. 1A, an oxide film 102 having a predetermined thickness is formed on the semiconductor substrate 100, and an anti-reflective coating (ARC) is formed by sputtering on the oxide film 102. 1 Ti / TiN film 104 is formed.

도 1b에서 나타낸 바와 같이, 제1 Ti/TiN막(104) 상부에 ALD(atomic layer deposition)방법으로 제1 은(Ag)막(106)을 형성하고 제1 은(Ag)막(106) 상부에 제1 알루미늄(Al)막(108)을 형성하며 제1 알루미늄막(108) 상부에 제2 은(Ag)막(110)을 형성하고 제2 은(Ag)막(110) 상부에 제2 알루미늄(Al)막(112)을 형성하며 제2 알루미늄(Al)막(112)에 제3 은(Ag)막(114)을 형성하고 제3 은(Ag)막(114) 상부에 제3 알루미늄(Al)막(116)을 형성하고 제3 알루미늄(Al)막(116) 상부에 제4 은(Ag)막(118)을 형성하여 층간 금속막(105)을 구비한다.As shown in FIG. 1B, the first silver (Ag) film 106 is formed on the first Ti / TiN film 104 by the ALD (atomic layer deposition) method, and the first silver (Ag) film 106 is formed on the first Ti / TiN film 104. A first aluminum (Al) film 108 is formed on the second aluminum film 108, and a second silver (Ag) film 110 is formed on the second silver (Ag) film 110. An aluminum (Al) film 112 is formed, and a third silver (Ag) film 114 is formed on the second aluminum (Al) film 112, and the third aluminum is formed on the third silver (Ag) film 114. An Al film 116 is formed, and a fourth silver (Ag) film 118 is formed on the third aluminum (Al) film 116 to provide an interlayer metal film 105.

ALD(atomic layer deposition)방법은 제1 은(Ag)막(106) 내지 제4 은(Ag)막(118)을 형성하는 경우 AgNO3 또는 Ag2NH 등의 소스를 사용하고, 제1 알루미늄(Al)막(108) 내지 제3 알루미늄(Al)막(116)을 형성하는 경우 (CH3)2AlH와 (CH3)3Al, I-(C4H9)3Al 등의 소스를 사용한다.The ALD (atomic layer deposition) method uses a source such as AgNO3 or Ag2NH to form the first silver (Ag) film 106 to the fourth silver (Ag) film 118, and the first aluminum (Al) film. When forming the 108 to third aluminum (Al) film 116, sources such as (CH3) 2AlH, (CH3) 3Al, and I- (C4H9) 3Al are used.

여기서, 제1 은(Ag)막(106) 내지 제4 은(Ag)막(118) 및 제1 알루미늄(Al)막(108) 내지 제3 알루미늄(Al)막(116)의 두께는 각각 100Å~1000Å의 두께로 형성되지만 원하는 조성에 따라 조절이 가능하다.In this case, the thicknesses of the first silver (Ag) film 106 to the fourth silver (Ag) film 118 and the first aluminum (Al) film 108 to the third aluminum (Al) film 116 are 100 μs, respectively. It is formed to a thickness of ~ 1000Å but can be adjusted according to the desired composition.

도 1c에서 나타낸 바와 같이, 제4 은(Ag)막(118) 상부에 제2 Ti/TiN막(120)을 형성하고, 제2 Ti/TiN막(120) 상부에 포토 레지스트 물질을 도포한 후 패터닝하여 포토 레지스트패턴(122)을 형성한다.As shown in FIG. 1C, after the second Ti / TiN film 120 is formed on the fourth silver (Ag) film 118 and the photoresist material is coated on the second Ti / TiN film 120. Patterning is performed to form the photoresist pattern 122.

도 1d에서 나타낸 바와 같이, 포토 레지스트 패턴(122)을 식각마스크로 이용하는 건식식각(dry etch)공정을 수행하여 산화막(102)의 일부가 노출되도록 제2 Ti/TiN막(120), 층간 금속막(105) 및 제1 Ti/TiN막을 선택적으로 식각하여 패턴(pattern)(107)을 형성한다.As shown in FIG. 1D, the second Ti / TiN film 120 and the interlayer metal film may be exposed to a portion of the oxide film 102 by performing a dry etch process using the photoresist pattern 122 as an etching mask. 105 and the first Ti / TiN film are selectively etched to form a pattern 107.

여기서, 건식식각 공정조건은 9E-4 torr 내지 11E-4 torr 의 압력에서 NaOH 및 KOH에 대해 He 플라즈마를 이용하여 액티브한(Active) OH-기를 생성하고 생성한 OH-기를 통해 제2 Ti/TiN 막(120), 층간 금속막(105) 및 제1 Ti/TiN막(104)을 선택적으로 식각하여 패턴(107)을 형성한다.Here, the dry etching process is the second Ti / TiN through the OH- group generated by using an active OH- group using He plasma for NaOH and KOH at a pressure of 9E-4 torr to 11E-4 torr The film 120, the interlayer metal film 105, and the first Ti / TiN film 104 are selectively etched to form a pattern 107.

또한, 반도체 기판에 -바이어스(bias)를 형성시켜 반도체 기판에 스퍼터링(sputtering) 식각이 병행되도록 한다.In addition, a -bias is formed on the semiconductor substrate so that sputtering etching is performed on the semiconductor substrate in parallel.

도 1e에서 나타낸 바와 같이, 패턴(pattern)을 포함하는 반도체 기판(100) 전면에 ALD(atomic layer deposition)방법 또는 CVD(chemical vapor depostion)방법으로 소정의 두께 예컨대, 900Å 내지 1100Å의 두께를 갖는 제4 알루미늄(Al)막(122)을 증착한다.As illustrated in FIG. 1E, a material having a predetermined thickness, for example, 900 kPa to 1100 kPa, may be formed on the entire surface of the semiconductor substrate 100 including the pattern by ALD (atomic layer deposition) or CVD (chemical vapor depostion). 4 An aluminum (Al) film 122 is deposited.

여기서, ALD방법 또는 CVD방법은 (CH3)2AlH와 (CH3)Al, I-(C4H9)3Al 등의 소스 가스로 제4 알루미늄(Al)막(122)을 형성한다.Here, the ALD method or the CVD method forms the fourth aluminum (Al) film 122 with source gases such as (CH3) 2AlH, (CH3) Al, and I- (C4H9) 3Al.

도 1f에서 나타낸 바와 같이, 350℃ 내지 450℃의 온도 및 9E-3 torr 내지 11E-3 torr의 압력에서 불활성 가스(He, Ne, Ar등) 및 N2O를 수십 MHz 수준의 플라즈마(Plasma)로 형성하여 제4 알루미늄(Al)막(122)을 질산화시킨 AlxOyNz의 DARC(dielectric anti reflection coating)막(122a)을 형성시킨다.As shown in FIG. 1F, an inert gas (He, Ne, Ar, etc.) and N 2 O are formed into a plasma of several tens of MHz at a temperature of 350 ° C. to 450 ° C. and a pressure of 9E-3 torr to 11E-3 torr. As a result, an AlxOyNz DARC (dielectric anti reflection coating) film 122a obtained by nitrifying the fourth aluminum (Al) film 122 is formed.

또한, 불활성 가스(He, Ne, Ar등) 및 N2O 대신에 불활성 가스(He, Ne, Ar등), NH3 및 O2를 수십 MHz 수준의 플라즈마(Plasma)로 형성하거나, 불활성 가스(He, Ne, Ar등), N2 및 O2를 수십 MHz 수준의 플라즈마(Plasma)로 형성하여 제5 알루미늄(Al)막(122)을 질산화시킨 AlxOyNz의 DARC(dielectric anti reflection coating)막(122a)을 형성시킬 수도 있다.In addition, instead of inert gas (He, Ne, Ar, etc.) and N2O, inert gas (He, Ne, Ar, etc.), NH3, and O2 may be formed in a plasma of several tens of MHz levels, or inert gases (He, Ne, Ar, N2, and O2 may be formed by plasma of several tens of MHz level to form a dielectric anti reflection coating (DARC) film 122a of AlxOyNz, which nitrifies the fifth aluminum (Al) film 122. .

여기서, 산화된 AlxOyNz의 DARC(dielectric anti reflection coating)막은 반사 방지막으로 작용하며 동시에 알루미늄(Al)막과 은(Ag)막 사이에 발생할 수 있는 이종금속 접촉부식(galvanic corrosion)을 방지할 수 있다.Here, the oxidized AlxOyNz DARC (dielectric anti reflection coating) film acts as an anti-reflection film and can prevent galvanic corrosion that may occur between the aluminum (Al) film and the silver (Ag) film.

이후 HDP CVD(High density plasma chemical vapor depostion) 공정 등을 이용하여 USG(undoped silicon glass) 또는 FSG(flourine doped silicon glass)로 패턴(107)을 갭 필(gap fill)한다.Thereafter, the pattern 107 is gap-filled with undoped silicon glass (USG) or flour doped silicon glass (FSG) using a high density plasma chemical vapor depostion (HDP) process.

이상과 같이 본 발명은 비록 한정된 실시 예와 도면에 의해 설명되었으나, 본 발명은 상기의 실시 예에 한정되는 것이 아니며, 본 발명이 속하는 분야에서 통상의 지식을 가진 자라면, 이러한 기재로부터 다양한 수정 및 변형이 가능하다.As described above, although the present invention has been described with reference to the limited embodiments and the drawings, the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains can make various modifications and Modifications are possible.

그러므로, 본 발명의 범위는 설명된 실시 예에 국한되어 정해져서는 아니되며, 후술하는 특허청구범위뿐만 아니라 이 특허 청구범위와 균등한 것들에 의해 정해져야 한다.Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자 형성방법에서 패턴을 포함하는 반도체 기판 전면에 DARC막을 형성함으로써, 알루미늄(Al)막과 은(Ag)막 사이에 발생할 수 있는 이종금속접촉 부식을 방지할 수 있는 효과가 있다.As described above, in the method of forming a semiconductor device according to the present invention, forming a DARC film on the entire surface of a semiconductor substrate including a pattern prevents dissimilar metal contact corrosion that may occur between the aluminum (Al) film and the silver (Ag) film. It can work.

또한, 본 발명에서 패턴을 포함하는 반도체 기판 전면에 DARC막을 형성하여 알루미늄(Al)막과 은(Ag)막 사이의 이종금속접촉 부식을 방지함으로써, RC 지연(delay)을 개선할 수 있는 효과가 있다.In addition, in the present invention, by forming a DARC film on the entire surface of the semiconductor substrate including the pattern to prevent dissimilar metal contact corrosion between the aluminum (Al) film and the silver (Ag) film, the effect of improving the RC delay is improved. have.

Claims (12)

반도체 기판에 산화막을 형성하고, 상기 산화막 상부에 제1 Ti/TiN막을 형성하는 단계;Forming an oxide film on the semiconductor substrate, and forming a first Ti / TiN film on the oxide film; 상기 제1 Ti/TiN막 상부에 층간 금속막을 형성하는 단계;Forming an interlayer metal film on the first Ti / TiN film; 상기 층간 금속막 상부에 제2 Ti/TiN막을 형성하는 단계;Forming a second Ti / TiN film on the interlayer metal film; 상기 산화막이 일부 노출되도록 건식식각 공정을 이용하여 상기 제2 Ti/TiN막, 상기 층간 금속막 및 상기 제1 Ti/TiN 막을 선택적으로 식각하여 패턴을 형성하는 단계;Forming a pattern by selectively etching the second Ti / TiN film, the interlayer metal film, and the first Ti / TiN film by using a dry etching process to partially expose the oxide film; 상기 패턴을 포함하는 상기 반도체 기판 전면에 알루미늄(Al)막을 형성하는 단계; 및Forming an aluminum (Al) film on an entire surface of the semiconductor substrate including the pattern; And 상기 알루미늄(Al)막을 질산화시켜 DARC막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 형성방법.And nitrifying the aluminum (Al) film to form a DARC film. 제1항에 있어서,The method of claim 1, 상기 알루미늄(Al)막은,The aluminum (Al) film, (CH3)2AlH, (CH3)3Al 및 I-(C4H9)3Al를 ALD(atomic layer deposition)방법 또는 CVD(chemical vapor depostion)방법을 이용하여 형성하는 것을 특징으로 하는 반도체 소자 형성방법.(CH3) 2AlH, (CH3) 3Al and I- (C4H9) 3Al are formed using an atomic layer deposition (ALD) method or a chemical vapor depostion (CVD) method. 제1 항에 있어서,According to claim 1, 상기 층간 금속막은,The interlayer metal film, ALD(atomic layer deposition) 방법을 이용하여 상기 제1 Ti/TiN막 상부에 제1 은(Ag)막, 제1 알루미늄(Al)막, 제2 은(Ag)막, 제2 알루미늄(Al)막, 제3 은(Ag)막, 제3 알루미늄(Al)막 및 제4 은(Ag)막을 순차적으로 형성하는 것을 특징으로 하는 반도체 소자 형성방법. A first silver (Ag) film, a first aluminum (Al) film, a second silver (Ag) film, and a second aluminum (Al) film on the first Ti / TiN film by using an atomic layer deposition (ALD) method. And forming a third silver (Ag) film, a third aluminum (Al) film and a fourth silver (Ag) film sequentially. 제3항에 있어서,The method of claim 3, 상기 ALD(atomic layer deposition) 방법은,The ALD (atomic layer deposition) method, (CH3)2AlH, (CH3)3Al 및 I-(C4H9)3Al를 소스로 하여 상기 제1 알루미늄(Al)막 내지 제3 알루미늄(Al)막을 형성하고 AgNO3 또는 Ag2NH를 소스로 하여 상기 제1 은(Ag)막 내지 상기 제4 은(Ag)막을 형성하는 것을 특징으로 하는 반도체 소자 형성방법.The first aluminum (Al) film to the third aluminum (Al) film are formed using (CH 3) 2 AlH, (CH 3) 3 Al, and I- (C 4 H 9) 3 Al as a source, and the first silver (AgNO 3 or Ag 2 NH is used as a source). An Ag) film to the fourth silver (Ag) film are formed. 제3항 또는 제4항에 있어서,The method according to claim 3 or 4, 상기 제1 은(Ag)막 내지 제4 은(Ag)막 및 제1 알루미늄(Al)막 내지 제3 알루미늄(Al)막의 두께는,The thickness of the first silver (Ag) film to the fourth silver (Ag) film and the first aluminum (Al) film to the third aluminum (Al) film, 100Å~1000Å의 두께로 각각 형성되는 것을 특징으로 하는 반도체 소자 형성방법.A method of forming a semiconductor device, characterized in that formed in each of the thickness of 100 ~ 1000Å. 제1항에 있어서,The method of claim 1, 상기 건식식각 공정 조건은,The dry etching process conditions, 9E-4 torr 내지 11E-4 torr의 압력 공정 조건을 갖는 것을 특징으로 하는 반도체 소자 형성방법.A process for forming a semiconductor device, characterized in that it has a pressure processing condition of 9E-4 torr to 11E-4 torr. 제1항에 있어서,The method of claim 1, 상기 DARC막 형성 단계는,The DARC film forming step, 9E-3 torr 내지 11E-3 torr의 압력 및 350℃ 내지 450℃의 온도에서 불활성 가스 및 N2O를 이용하는 것을 특징으로 하는 반도체 소자 형성방법.A method of forming a semiconductor device comprising using an inert gas and N 2 O at a pressure of 9E-3 torr to 11E-3 torr and a temperature of 350 ° C to 450 ° C. 제1항에 있어서,The method of claim 1, 상기 DARC막 형성 단계는,The DARC film forming step, 9E-3 torr 내지 11E-3 torr의 압력 및 350℃ 내지 450℃의 온도에서 불활성 가스, O2 및 NH3를 이용하는 것을 특징으로 하는 반도체 소자 형성방법.A method of forming a semiconductor device comprising using an inert gas, O2 and NH3 at a pressure of 9E-3 torr to 11E-3 torr and a temperature of 350 ° C to 450 ° C. 제1항에 있어서,The method of claim 1, 상기 DARC막 형성 단계는,The DARC film forming step, 9E-3 torr 내지 11E-3 torr의 압력 및 350℃ 내지 450℃의 온도에서 불활성 가스, N2 및 O2를 이용하는 것을 특징으로 하는 반도체 소자 형성방법.A method of forming a semiconductor device comprising using an inert gas, N2 and O2 at a pressure of 9E-3 torr to 11E-3 torr and a temperature of 350 ° C to 450 ° C. 제7항에 있어서,The method of claim 7, wherein 상기 DARC막은,The DARC film, 상기 불활성 가스 및 N20를 플라즈마로 형성하여 상기 알루미늄(Al)막을 질산화시킨 AlxOyNz로 형성되는 것을 특징으로 하는 반도체 소자 형성방법.And forming Al x O y N z in which the inert gas and N 20 are formed by plasma to nitrate the aluminum (Al) film. 제8항에 있어서,The method of claim 8, 상기 DARC막은,The DARC film, 상기 불활성 가스, NH3 및 02를 플라즈마로 형성하여 상기 알루미늄(Al)막을 질산화시킨 AlxOyNz로 형성되는 것을 특징으로 하는 반도체 소자 형성방법.And forming Al x O y N z in which the inert gas, NH 3 and 02 are formed by plasma to nitrate the aluminum (Al) film. 제9항에 있어서,The method of claim 9, 상기 DARC막은,The DARC film, 상기 불활성 가스, N2 및 02를 플라즈마로 형성하여 상기 알루미늄(Al)막을 질산화시킨 AlxOyNz로 형성되는 것을 특징으로 하는 반도체 소자 형성방법.And forming the inert gas, N2, and 02 into plasma to form AlxOyNz in which the aluminum (Al) film is nitridated.
KR1020060109319A 2006-11-07 2006-11-07 Method for Forming Semiconductor Device KR100840641B1 (en)

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KR19990007431A (en) 1997-06-30 1999-01-25 가나이 쓰토우 Manufacturing method of semiconductor integrated circuit device
KR20000062522A (en) 1999-02-03 2000-10-25 조셉 제이. 스위니 Tailoring of a wetting/barrier layer to reduce electromigration in an aluminum interconnect
KR100399417B1 (en) * 2001-01-08 2003-09-26 삼성전자주식회사 A method for preparing of integrated circuit of semiconductor
KR100495960B1 (en) * 1995-02-24 2005-11-22 프리스케일 세미컨덕터, 인크. Semiconductor device and semiconductor device manufacturing method
KR100599123B1 (en) * 2004-12-09 2006-07-12 한국전자통신연구원 Fabrication method of nitride semiconductor

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KR100495960B1 (en) * 1995-02-24 2005-11-22 프리스케일 세미컨덕터, 인크. Semiconductor device and semiconductor device manufacturing method
KR19990007431A (en) 1997-06-30 1999-01-25 가나이 쓰토우 Manufacturing method of semiconductor integrated circuit device
KR20000062522A (en) 1999-02-03 2000-10-25 조셉 제이. 스위니 Tailoring of a wetting/barrier layer to reduce electromigration in an aluminum interconnect
KR100399417B1 (en) * 2001-01-08 2003-09-26 삼성전자주식회사 A method for preparing of integrated circuit of semiconductor
KR100599123B1 (en) * 2004-12-09 2006-07-12 한국전자통신연구원 Fabrication method of nitride semiconductor

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