KR100748361B1 - Logic gate, scan driver and organic light emitting display using the same - Google Patents

Abstract

A logic gate, a scan driver and an OLED(Organic Light Emitting Display) device using the same are provided to achieve stable operation performance by setting a high period longer than a low period in a driving waveform. A control transistor(M7) is disposed between a first source voltage(VDD) and a second source voltage(VSS) lower than the first source voltage, and a first electrode thereof is connected to an output terminal(Vout). A first driver(10), which is disposed between the first electrode and the first source voltage, controls a connection between the first electrode and the first source voltage based on input signals(IN1,IN2,IN3). A second driver(12), which is disposed between the first electrode and a gate electrode of the first transistor, controls a connection between the first electrode and the gate electrode based on the input signals. A third driver(14), which is disposed between the gate electrode and the second source voltage, controls a connection between the gate electrode and the second source voltage based on input bar signals(/IN1,/IN2,/IN3). The first, second, and third drivers are composed of plural PMOS transistors.

Description

Logic Gate, Scan Driver and Organic Light Emitting Display Using the Same

1 is a circuit diagram illustrating a negative AND gate according to an exemplary embodiment of the present invention.

2 is a circuit diagram illustrating a logic sum gate according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a scan driver configured using the logic gates illustrated in FIGS. 1 and 2.

4 is a diagram illustrating an embodiment of a driving waveform supplied to the input terminals of FIG. 3.

FIG. 5 is a diagram illustrating a connection configuration of negative AND gates input terminals illustrated in FIG. 3.

FIG. 6A is a diagram illustrating in detail a driving waveform supplied to a first input terminal, a second input terminal, and a third input terminal shown in FIG. 4.

6B is a diagram illustrating another embodiment of a driving waveform supplied to the first input terminal.

7 is a diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

10, 12, 14, 20, 22, 24, 26: Driver 30, 32, 34: Decoder

110: scan driver 120: data driver

130: pixel portion 140: pixel

150: timing controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic gate, a scan driver using the same, and an organic light emitting display, and more particularly, to a logic gate implemented using PMOS transistors, and a scan driver using the same.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, and an organic light emitting display.

Among flat panel displays, an organic light emitting display device displays an image using an organic light emitting diode (OLED) that generates light by recombination of electrons and holes. Such an organic light emitting display device has an advantage of having a fast response speed and being driven with low power consumption.

In general, an organic light emitting display device includes pixels arranged in a matrix, a data driver for driving data lines connected to the pixels, and a scan driver for driving scan lines connected with the pixels.

The scan driver sequentially selects pixels on a line-by-line basis while sequentially supplying scan signals for each horizontal period. The data driver supplies a data signal to pixels selected in line units by the scan signal. Then, each of the pixels displays a predetermined image corresponding to the data signal by supplying a predetermined current corresponding to the data signal to the organic light emitting diode.

On the other hand, in order to reduce the manufacturing cost of the organic light emitting display device, the scan driver must be mounted on the panel. However, since the conventional scan driver is composed of a PMOS transistor and an NMOS transistor, it is difficult to be mounted on a panel. In other words, a problem arises in that the number of masks increases when a scan driver composed of PMOS and NMOS transistors is formed in a panel. Accordingly, there is a need for a scan driver that can be implemented in PMOS transistors and formed in a panel.

Accordingly, an object of the present invention is to provide a logic gate implemented with PMOS transistors, a scan driver using the same, and an organic light emitting display device.

In order to achieve the above object, a logic gate according to an embodiment of the present invention comprises a first power source and a second power source set to a lower voltage value than the first power source; A control transistor positioned between the first power supply and the second power supply, and having an output terminal connected to its first electrode; A first driver disposed between the first electrode of the control transistor and the first power source and controlling a connection between the first electrode and the first power source in response to a plurality of input signals supplied from the outside; A second driver positioned between the first electrode and the gate electrode of the control transistor and controlling a connection between the first electrode and the gate electrode of the control transistor in response to the plurality of input signals; A third driver disposed between the gate electrode of the control transistor and the second power source and controlling a connection between the gate electrode of the control transistor and the second power source in response to a plurality of input bar signals input from the outside; To; Each of the first driver, the second driver, and the third driver includes a plurality of transistors, and the transistors and the control transistor are formed of a PMOS.

A logic gate according to an embodiment of the present invention includes a first power supply and a second power supply set to a lower voltage value than the first power supply; A first driver positioned between the first power source and the first node and controlling a voltage of the first node in response to a plurality of input signals supplied from the outside; A second driver positioned between the first node and the second power source to control a voltage value of the first node; A third driver positioned between the first power source and the output terminal and controlling whether the first power source and the output terminal are connected by a voltage value applied to the first node; A control transistor connected between the third driver and the second power source; A fourth driver connected between the gate electrode of the control transistor and the second power source and controlling a connection between the gate electrode of the control transistor and the second power source in response to the plurality of input signals; Each of the first driver, the second driver, the third driver, and the fourth driver includes a plurality of transistors, and the transistors and the control transistor are formed of a PMOS.

According to an embodiment of the present invention, a scan driver includes at least one decoder having a plurality of negative AND gates, and a plurality of logical sums connected to different scan lines, respectively, to generate a scan signal by performing an OR operation on the outputs of the decoders. Gates, and each of the negative AND gates and the OR gate is composed of a plurality of PMOS transistors.

An organic light emitting display device according to an embodiment of the present invention includes a data driver for supplying a data signal to data lines, a scan driver for supplying a scan signal to scan lines, and a scan signal connected to the data line and the scan line. Is provided with a plurality of pixels for charging a voltage corresponding to the data signal, wherein the scan driver is connected to at least one decoder having a plurality of negative AND gates, each of which is connected to different scan lines; And a plurality of logical sum gates configured to perform an OR operation on the outputs of the decoder to generate a scan signal, wherein each of the negative AND gates and the OR gates include a plurality of PMOS transistors.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 7 to which a person skilled in the art may easily implement the present invention.

1 is a diagram illustrating an NAND gate according to an exemplary embodiment of the present invention. Here, the negative AND gate according to the embodiment of the present invention is implemented with PMOS transistors.

Referring to FIG. 1, a negative AND gate according to an exemplary embodiment of the present invention may include a seventh transistor M7 (control transistor), a first power source VDD, and a second voltage for controlling a voltage supplied to an output terminal Vout. Located between the seventh transistor M7 and corresponding to the polarity (high or low) of the first input signal IN1, the second input signal IN2, and the third input signal IN3, The first driver 10 controls whether the first electrode of the seventh transistor M7 is connected, and is located between the first electrode and the gate electrode of the seventh transistor M7, and includes the first input signal IN1 and the first electrode. A second driver 12 controlling whether the first electrode and the gate electrode of the seventh transistor M7 are connected to each other in response to the polarity (high or low) of the second input signal IN2 and the third input signal IN3; And positioned between the gate electrode of the seventh transistor M7 and the second power supply VSS, and include a first input bar signal / IN1, a second input bar signal / IN2, and a third input bar signal / IN. The third driver 14 controls whether the gate electrode of the seventh transistor M7 and the second power source VSS are connected to each other according to the polarity (high or low) of 3).

The seventh transistor M7 is turned on or turned off in response to the voltage supplied to its gate electrode. For example, the seventh transistor M7 is turned off when the voltage of the first power source VDD is supplied to its gate electrode, and is turned on when the voltage of the second power source VSS is supplied. To this end, the first power source VDD is set to a higher voltage than the second power source VSS. For example, the first power source VDD may be set to a positive voltage, and may be set to a ground voltage or a negative voltage of the second power source VSS.

The first driving unit 10 is the first transistor M1, the second transistor M2 and the third transistor M3 connected in parallel between the first power supply VDD and the first electrode of the seventh transistor M7. It is provided. The first driver 10 may include the first power source VDD and the first power source when one of the first input signal IN1, the second input signal IN2, and the third input signal IN3 is set to low polarity. The first electrode of the seven transistors M7 is electrically connected.

In detail, the first transistor M1 is connected between the first power supply VDD and the first electrode of the seventh transistor M1, and is turned on or turned off by the first input signal IN1. . That is, the first transistor M1 is turned on when the first input signal IN1 is low polarity, and is otherwise turned off.

The second transistor M2 is connected between the first power supply VDD and the first electrode of the seventh transistor M1, and is turned on or turned off by the second input signal IN2. That is, the second transistor M2 is turned on when the second input signal IN2 is low polarity, and is otherwise turned off.

The third transistor M3 is connected between the first power supply VDD and the first electrode of the seventh transistor M1, and is turned on or turned off by the third input signal IN3. That is, the third transistor M3 is turned on when the third input signal IN3 is low polarity, and is turned off otherwise.

The second driver 12 includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6 connected in parallel between the first electrode and the gate electrode of the seventh transistor M7. The second driver 12 may include the seventh transistor M7 when one of the first input signal IN1, the second input signal IN2, and the third input signal IN3 is set to low polarity. One electrode and the gate electrode are electrically connected.

In detail, the fourth transistor M4 is connected between the first electrode and the gate electrode of the seventh transistor M7 and is turned on or turned off by the third input signal IN3. That is, the fourth transistor M4 is turned on when the third input signal IN3 is low polarity, and is turned off otherwise.

The fifth transistor M5 is connected between the first electrode and the gate electrode of the seventh transistor M7 and is turned on or turned off by the second input signal IN2. That is, the fifth transistor M5 is turned on when the second input signal IN2 is low polarity, and is otherwise turned off.

The sixth transistor M6 is connected between the first electrode and the gate electrode of the seventh transistor M7 and is turned on or turned off by the first input signal IN1. That is, the sixth transistor M6 is turned on when the first input signal IN1 is low polarity, and is otherwise turned off.

The third driving unit 14 connects the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 that are connected in series between the gate electrode of the seventh transistor M7 and the second power supply VSS. Equipped. The third driver 14 may include the seventh transistor M7 when the first input bar signal / IN1, the second input bar signal / IN2, and the third input bar signal / IN3 are set to low polarity. Gate electrode and the second power source VSS are electrically connected to each other.

In detail, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are installed in series between the gate electrode of the seventh transistor M7 and the second power source VSS. Here, the eighth transistor M8 is turned on when the first input bar signal / IN1 is low polarity, and the ninth transistor M9 is turned on when the second input bar signal / IN2 is low polarity. -On. The tenth transistor M1 is turned on when the third input bar signal / IN3 is low polarity.

Table 1 shows the truth table of negative AND gates.

IN1 IN2 IN3 Vout 0 0 0 One 0 0 One One 0 One 0 One 0 One One One One 0 0 One One 0 One One One One 0 One One One One 0

Referring to Figure 1 and Table 1 will be described in detail the operation process. First, when any one of the first input signal IN1, the second input signal IN2, and the third input signal IN3 is set to low polarity, the first transistor M1, the second transistor M2, and the first transistor One of the three transistors M3 is turned on. Then, the first power source VDD and the first electrode of the seventh transistor M7 are electrically connected, and the voltage of the first power source VDD is output to the output terminal vout. That is, when any one of the first input signal IN1, the second input signal IN2, and the third input signal IN3 is set to low polarity, a high polarity voltage is supplied to the output terminal vout.

The fourth transistor M4, the fifth transistor M5, and the sixth transistor when any one of the first input signal IN1, the second input signal IN2, and the third input signal IN3 are set to low polarity. Any one of M6 is turned on. Then, the first electrode VDD and the gate electrode of the seventh transistor M7 are electrically connected. In this case, voltages at both ends of the first capacitor C1 positioned between the gate electrode and the first electrode of the seventh transistor M7 are set to be the same (that is, the first power source VDD). That is, the first capacitor C1 maintains the same voltage between the gate electrode and the first electrode of the seventh transistor M7 to prevent the leakage current from flowing from the seventh transistor M7 to the second electrode VSS. do.

When any one of the first input signal IN1, the second input signal IN2, and the third input signal IN3 is set to low polarity, the first input bar signal / IN1 and the second input bar signal Any one of / IN2 and the third input bar signal / IN3 is set to high polarity. In this case, any one of the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 is turned off so that the gate electrode of the seventh transistor M7 and the second power source VSS are electrically connected to each other. Is blocked.

Meanwhile, when all of the first input signal IN1, the second input signal IN2, and the third input signal IN3 are set to high polarity, the first transistor M1, the second transistor M2, and the third transistor M3 is turned off. Then, the first electrode VDD and the first electrode of the seventh transistor M7 are electrically cut off.

When the first input signal IN1, the second input signal IN2, and the third input signal IN3 are all set to high polarity, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6. ) Is turned off. Then, the first electrode and the gate electrode of the seventh transistor M7 are electrically blocked.

Meanwhile, when all of the first input signal IN1, the second input signal IN2, and the third input signal IN3 are set to high polarity, the first input bar signal / IN1 and the second input bar signal ( / IN2) and the third input bar signal / IN3 are set to low polarity. In this case, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are turned on to supply the voltage of the second power source VSS to the gate electrode of the seventh transistor M7. When the voltage of the second power supply VSS is supplied to the gate electrode of the seventh transistor M7, the seventh transistor M7 is turned on to supply the voltage of the second power supply VSS to the output terminal vout. That is, when all of the first input signal IN1, the second input signal IN2, and the third input signal IN3 are set to high polarity, the second terminal VSS corresponding to the low polarity is output to the output terminal vout. The voltage of is output.

The negative AND gates of the present invention as described above are all composed of PMOS transistors. Accordingly, the organic light emitting display device may be embedded in a panel, thereby reducing manufacturing costs and shortening the manufacturing process.

Meanwhile, although FIG. 1 illustrates a negative AND gate having three inputs, the present invention is not limited thereto. In other words, the number of inputs may be controlled by adjusting the number of transistors included in each of the first driver 10, the second driver 12, and the third driver 14. For example, if four transistors are included in each of the first driver 10, the second driver 12, and the third driver 14, a negative AND gate having four inputs may be formed.

2 illustrates an OR gate according to an exemplary embodiment of the present invention. Here, the OR gate according to the embodiment of the present invention is implemented with PMOS transistors.

Referring to FIG. 2, the OR gate according to an exemplary embodiment of the present invention includes an eighteenth transistor M18 (control transistor), a first power source VDD, and a first power source for controlling a voltage supplied to an output terminal vout. Located between the nodes N1, the first power source VDD and the first power source correspond to the polarity (high or low) of the first input signal IN1, the second input signal IN2, and the third input signal IN3. The voltage is controlled between the fourth driver 20 (first driver) controlling the connection of the node N1 and between the first node N1 and the second power source VSS to control the voltage of the first node N1. The 18th transistor is connected between the 5th drive part 22 (2nd drive part), the 1st electrode of the 18th transistor M18, and the 1st power supply VDD, and respond | corresponds to the voltage of the 1st node N1. Between the sixth driver 24 (third driver) for controlling whether the first electrode of the M18 and the first power source VDD are connected, and between the gate electrode of the eighteenth transistor M18 and the second power source VSS. Connected to the first input signal Corresponding to the polarity (high or low) of the arc IN1, the second input signal IN2, and the third input signal IN3, whether the gate electrode of the eighteenth transistor M18 and the second power supply VSS are connected or not. A seventh drive part 26 (fourth drive part) to control is provided.

The eighteenth transistor M18 controls the voltage supplied to the output terminal Vout while being turned on or off in response to the voltage supplied to its gate electrode. For example, the eighteenth transistor M18 is turned off when the voltage of the first power source VDD is supplied to its gate electrode, and is turned on when the voltage of the second power source VSS is supplied.

The fourth driving unit 20 is an eleventh transistor M11 (first transistor), a twelfth transistor M12 (second transistor), which are connected in series between the first power source VDD and the first node N1, and A thirteenth transistor M13 (third transistor) is provided. The fourth driver 20 may include the first power source VDD and the first node when the first input signal IN1, the second input signal IN2, and the third input signal IN3 are set to low polarity. N1) is electrically connected.

In detail, the eleventh transistor M11 is turned on when the first input signal IN1 is low polarity, and the twelfth transistor M12 is turned on when the second input signal IN2 is low polarity. do. The thirteenth transistor M13 is turned on when the third input signal IN3 is low polarity. Here, since the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are connected in series between the first power source VDD and the first node N1, the first input signal IN1 is used. When the second input signal IN2 and the third input signal IN3 are all low polarity, the first power source VDD and the first node N1 are electrically connected to each other.

The fifth driving part 22 includes a fourteenth transistor M14 (fourth transistor) connected between the first node N1 and the second power supply VSS, the gate electrode and the second power supply of the fourteenth transistor M14. A fifteenth transistor M15 (fifth transistor) connected between the VSS, and a second capacitor C2 connected between the gate electrode and the first electrode of the fourteenth transistor M14. The fifth driver 22 maintains the voltage of the first power source VDD when the voltage of the first power source VDD is supplied to the first node N1, and in other cases, the first node N1. Is maintained at the voltage of the second power supply VSS.

In detail, the first electrode of the fifteenth transistor M15 is connected to the gate electrode of the fourteenth transistor M14, and the gate electrode and the second electrode are connected to the second power source VSS. That is, the fifteenth transistor M15 is connected in a diode form to maintain the voltage of the gate electrode of the fourteenth transistor M14 at approximately the voltage of the second power source VSS.

When the first power source VDD and the first node N1 are electrically disconnected by the fourth driving unit 20, the fourteenth transistor M14 has a low polarity (that is, a second voltage) of the first node N1. Power supply (VSS). In addition, when the first power source VDD and the first node N1 are electrically connected by the fourth driving unit 20, the fourteenth transistor M14 has a high polarity (that is, a voltage of the first node N1). The first power supply VDD is maintained. For this purpose, the channel / length ratio W / L of the fourteenth transistor M14 is the channel / length ratio W / L of each of the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13. It is narrower than).

Then, when the voltage of the first power source VDD is supplied to the first node N1, the voltage of the first power source VDD may be stably maintained. Meanwhile, when the voltage of the first power source VDD is supplied to the first node N1, a predetermined leakage current may be generated by the fourteenth transistor M14. However, when the first power source VDD is supplied to the first node N1, when the first input signal IN1, the second input signal IN2, and the third input signal IN3 all have low polarity. This is only a part of the furnace operation process, and therefore, a lot of power consumption is not consumed by the leakage current. Meanwhile, the second capacitor C2 charges a voltage between the first electrode and the gate electrode of the fourteenth transistor M14 to stabilize the operation of the fourteenth transistor M14.

The sixth driver 24 includes the sixteenth transistor M16 (the sixth transistor) connected between the first power supply VDD and the first electrode of the eighteenth transistor M18, and the gate electrode of the sixteenth transistor M16. And a seventeenth transistor M17 (seventh transistor) connected between the second electrode and the second electrode. The sixth driver 24 controls whether the first power source VDD is connected to the first electrode of the eighteenth transistor M18 in response to the voltage supplied to the first node N1.

In detail, the sixteenth transistor M16 and the seventeenth transistor M17 are turned on when the low polarity voltage is supplied to the first node N1, and is otherwise turned off. When the sixteenth transistor M16 is turned on, the voltage of the first power source VDD is supplied to the output terminal Vout. When the seventeenth transistor M17 is turned on, the first electrode and the gate electrode of the eighteenth transistor M18 are electrically connected to each other. That is, when the seventeenth transistor M17 is turned on, the first power supply VDD is supplied to the gate electrode of the eighteenth transistor M18 to turn off the eighteenth transistor M18. Herein, the third capacitor C3 connected between the first electrode and the gate electrode of the eighteenth transistor M18 charges a voltage between the first electrode and the gate electrode of the eighteenth transistor M18 and the eighteenth transistor M18. This prevents leakage current from occurring.

The seventh driver 26 is the nineteenth transistor M19 (ninth transistor) and the twentieth transistor M20 (the tenth transistor) connected in series between the gate electrode of the eighteenth transistor M18 and the second power supply VSS. Transistor) and a twenty-first transistor M21 (eleventh transistor). The seventh driver 26 may include the gate electrode and the eighth transistor of the eighteenth transistor M18 when the first input signal IN1, the second input signal IN2, and the third input signal IN3 are set to low polarity. 2 Connect the power supply VSS electrically.

In detail, the 19th transistor M19 is turned on when the first input signal IN1 is low polarity, and the 20th transistor M20 is turned on when the second input signal IN2 is low polarity. do. The twenty-first transistor M21 is turned on when the third input signal IN3 has a low polarity. Here, the first input signal is because the 19th transistor M19, the 20th transistor M20, and the 21st transistor M21 are connected in series between the gate electrode of the 18th transistor M18 and the second power source VSS. When IN1, the second input signal IN2, and the third input signal IN3 are all low polarity, the gate electrode of the eighteenth transistor M18 and the second power source VSS are electrically connected.

Table 2 shows the truth table of the OR gate.

IN1 IN2 IN3 Vout 0 0 0 0 0 0 One One 0 One 0 One 0 One One One One 0 0 One One 0 One One One One 0 One One One One One

Referring to Figure 2 and Table 2 will be described in detail the operation process. First, when any one of the first input signal IN1, the second input signal IN2, and the third input signal IN3 is set to high polarity, the eleventh transistor M11, the twelfth transistor M12, and the first transistor One of the 13 transistors M13 is turned off. Then, the first power source VDD and the first node N1 are electrically cut off, and thus the voltage of the first node N1 is set to approximately the voltage of the second power source VSS.

When the voltage of the first node N1 is set to low polarity, the sixteenth transistor M16 and the seventeenth transistor M17 are turned on. When the sixteenth transistor M16 and the seventeenth transistor M17 are turned on, the voltage of the first power source VDD is output to the output terminal Vout (that is, a high polarity voltage output) and a first input. When any one of the signal IN1, the second input signal IN2, and the third input signal IN3 is set to high polarity, the 19th transistor M19, the 20th transistor M20, and the 21st transistor M21 are selected. Either of them is turned off. As a result, the gate electrode of the eighteenth transistor M18 and the second power supply VSS are electrically blocked to maintain the high polarity output voltage.

Meanwhile, when the first input signal IN1, the second input signal IN2, and the third input signal IN3 are set to low polarity, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor ( M13) is turned on. As a result, the first power source VDD and the first node N1 are electrically connected to each other, so that the voltage of the first node N1 is set to approximately the voltage of the first power source VDD.

When the voltage of the first node N1 is set to high polarity, the sixteenth transistor M16 and the seventeenth transistor M17 are turned off. In addition, when the first input signal IN1, the second input signal IN2, and the third input signal IN3 are set to low polarity, the 19th transistor M19, the 20th transistor M20, and the 21st transistor ( M21) is turned on. Then, the voltage of the second power supply VSS is supplied to the gate electrode of the eighteenth transistor M18, and the eighteenth transistor M18 is turned on, thereby outputting a low polarity voltage to the output terminal Vout. .

As described above, the logic sum gates of the present invention are all composed of PMOS transistors. Accordingly, the organic light emitting display device may be embedded in a panel, thereby reducing manufacturing costs and shortening the manufacturing process.

On the other hand, in Fig. 2 is shown an OR gate having three inputs, the present invention is not limited thereto. In other words, the number of inputs may be controlled by adjusting the number of transistors included in each of the fourth driver 20 and the seventh driver 26. For example, if four transistors are included in each of the fourth driver 20 and the seventh driver 26, a logic sum gate having four inputs may be formed.

FIG. 3 is a diagram illustrating a scan driver implemented using an AND gate and an OR gate illustrated in FIGS. 1 and 2. In FIG. 3, it is assumed that the scan driver is connected to 320 scan lines S1 to S320 and the scan signals are sequentially supplied to the scan lines S1 to S320 for convenience of description.

Referring to FIG. 3, the scan driver of the present invention performs a logical OR operation on the plurality of decoders 30, 32, and 34 and the outputs of the decoders 30, 32, and 34 to generate a scan signal OR1. To OR320).

The first decoder 30 and the second decoder 32 have three input terminals and eight output terminals, and the third decoder 34 has three input terminals and five output terminals. That is, eight negative AND gates are included in each of the first decoder 30 and the second decoder 32, and five negative AND gates are included in the third decoder 34. Here, the number of negative AND gates included in each of the decoders 30, 32, and 34 is determined by the number of scan lines S1 to S320 connected to the scan driver. For example, in FIG. 3, 21 negative AND gates are formed to supply a scan signal to 320 scan lines S1 to S320.

The first decoder 30 has eight negative AND gates NAND1 to NAND8. The first decoder 30 is connected to the input signals supplied from the first input terminal a1, the second input terminal a2, and the third input terminal a3, and to the first input terminal a1. The input bar signals supplied from the first inverter INV1, the second inverter INV2 connected to the second input terminal a2, and the third inverter INV3 connected to the third input terminal a3 are ANDed. The gates NAND1 and NAND8 are properly supplied. The input signals and the input bar signals supplied to the negative AND gates NAND1 to NAND8 will be described later.

The second decoder 32 has eight negative AND gates NAND9 to NAND16. The second decoder 32 is connected to the input signals supplied from the fourth input terminal a4, the fifth input terminal a5 and the sixth input terminal a6, and the fourth input terminal a4. The input bar signals supplied from the fourth inverter INV4, the fifth inverter INV5 connected to the fifth input terminal a5, and the sixth inverter INV6 connected to the sixth input terminal a6 are ANDed. The gates NAND9 to NAND16 are properly supplied. The input signals and the input bar signals supplied to the negative AND gates NAND9 to NAND16 will be described later.

The third decoder 34 has five negative AND gates NAND17 to NAND21. The third decoder 34 is connected to input signals supplied to the seventh input terminal a7, the eighth input terminal a8, and the ninth input terminal a9, and the seventh input terminal a7. A connection diagram with the eighth inverter INV8 and the ninth input terminal a9 connected to the seventh inverter INV7, the eighth input terminal a8, and the input bar signals supplied from the ninth inverter INV9 are negative logic. The product gates NAND17 to NAND21 are properly supplied. The input signals and the input bar signals supplied to the negative AND gates NAND17 to NAND21 will be described later.

Each of the OR gates OR1 to OR320 receives an output signal from the first decoder 30, the second decoder 32, and the third decoder 34, and performs an OR operation on the supplied output signal to scan lines S1. To S320).

Here, the first logical sum gate OR1 performs an OR operation on the outputs of the first negative AND gate, NAND1, the ninth AND logic gate, NAND9, and the seventeenth AND logic gate NAND17, and generates a first scan line S1. The scan signal is supplied to The second logical sum gate OR1 performs an OR operation on the outputs of the second negative AND gate NAND2, the ninth negative AND gate NAND9, and the seventeenth negative AND gate NAND17, and passes the result to the second scan line S2. Supply the scan signal.

The 64th logical sum gate OR64 performs an OR operation on the outputs of the eighth negative AND gate NAND8, the sixteenth AND logic gate NAND16, and the seventeenth AND logic gate NAND17. ). The 320th logical gate OR320 performs an OR operation on the outputs of the eighth negative AND gate NAND8, the sixteenth AND logic gate NAND16, and the 21st negative OR gate NAND21, and supplies the same to the 320th scan line S320. do. That is, in the present invention, each of the OR gates OR1 to OR320 may OR the outputs of the decoders 30, 32, and 34 to supply the scan signal to any one of the scan lines S1 to S320.

4 is a diagram illustrating a driving waveform supplied to the input terminals illustrated in FIG. 3.

Referring to FIG. 4, driving waveforms having different frequencies are supplied to the input terminals a1 to a9. In practice, the frequencies of the driving waveform are set to increase by two times from the ninth input terminal a9 to the first input terminal a1. In other words, the frequency of the driving waveform supplied to the eighth input terminal a8 is set to a frequency two times higher than the frequency of the driving waveform supplied to the ninth input terminal a9, and the seventh input terminal a7. The frequency of the driving waveform supplied is set to a frequency two times higher than the frequency of the driving waveform supplied to the eighth input terminal a8. In addition, the frequency of the driving waveform supplied to the sixth input terminal a6 is set to a frequency two times higher than the frequency of the driving waveform supplied to the seventh input terminal a7 and is supplied to the fifth input terminal a5. The frequency of the driving waveform is set to a frequency two times higher than the frequency of the driving waveform supplied to the sixth input terminal a6.

Meanwhile, in the present invention, the parasitic cap of the line wiring can be minimized by disposing the decoders 30, 32, and 34 corresponding to the input frequency. For example, by placing the decoder receiving the high frequency close to the OR gates OR1 to OR320, the parasitic cap and the resistance may be lowered, and thus the operating speed may be improved.

FIG. 5 is a diagram illustrating a connection of negative AND gates illustrated in FIG. 3. FIG. 6A is a diagram illustrating in detail a driving waveform supplied to the first input terminal a1, the second input terminal a2, and the third input terminal a3 shown in FIG. 4. In FIG. 5, for the convenience of description, connection of negative AND gates NAND1, NAND2, NAND3,... And NAND8 included in the first decoder 30 will be described. Here, the connection configurations of the negative AND gates NAND9 to NAND21 included in the second decoder 32 and the third decoder 34 are also set to be the same, except that the input terminals to be connected are different.

In other words, when the first negative AND gate NAND1 is connected to the first input bar terminal / a1 to the third input bar terminal / a2 as shown in FIG. 5, the ninth negative AND gate NAND9 is connected. Is connected to the fourth input bar terminal / a4 to the sixth input bar terminal / a6. Similarly, the seventeenth negative AND gate NAND17 is also connected to the seventh input bar terminal / a7 to the ninth input bar terminal / a9.

Referring to FIG. 5, in order to sequentially output scan signals, the first negative AND gates NAND1 to the eighth negative AND gate NAND8 should sequentially output low polarity signals. To this end, the first negative AND gate NAND1 receives the driving signal from the first input bar terminal / a1 as the first input signal IN1 and the driving from the second input bar terminal / a2. The signal is supplied to the second input signal IN2. The first negative AND gate NAND1 receives the driving signal from the third input bar terminal / a3 as the third input signal IN3 (wherein, the driving signal of the first input terminal a1). Is the first input bar signal / IN1, the drive signal of the second input terminal a2 is the second input bar signal / IN2, and the drive signal of the third input terminal a3 is the third input bar signal (/ IN3).)

Then, a low polarity voltage is output from the first negative AND gate NAND1 during the first period T1 shown in FIG. 6A. On the other hand, since the fourth input bar signal / a4, the fifth input bar signal / a5 and the sixth input bar signal / a6 are set to high polarity during the first period T1, the ninth negative logical product. A low polarity voltage is output from the gate NAND9. In addition, since the seventh input bar signal / a7, the eighth input bar signal / a8, and the ninth input bar signal / a9 are set to high polarity during the first period T1, the seventeenth negative logical product The low polarity voltage is output from the gate NAND17.

In this case, a low polarity signal, that is, a scan, is performed at the first logic gate OR1 connected to the first negative AND gate NAND1, the ninth negative AND gate NAND9, and the seventeenth negative AND gate NAND17. The signal is output. That is, the scan signal is output to the first scan line S1 during the first period T1.

The second negative AND gate NAND2 receives the driving signal from the first input terminal a1 as the first input signal IN1, and the driving signal from the second input bar terminal / a2 to the second input. It is supplied by the signal IN2. The second negative AND gate NAND2 receives the driving signal from the third input bar terminal / a3 as the third input signal IN3 (wherein the first input bar terminal / a1). The driving signal is the first input bar signal / IN1, the driving signal of the second input terminal a2 is the second input bar signal / IN2, and the driving signal of the third input terminal a3 is the third input bar signal. (/ IN3).)

Then, a low polarity voltage is output from the second negative AND gate NAND2 during the second period T2. On the other hand, since the fourth input bar signal / a4, the fifth input bar signal / a5, and the sixth input bar signal / a6 are set to high polarity during the second period T2, the ninth negative logical product. A low polarity voltage is output from the gate NAND9. In addition, since the seventh input bar signal / a7, the eighth input bar signal / a8, and the ninth input bar signal / a9 are set to high polarity during the second period T2, the seventeenth negative AND The low polarity voltage is output from the gate NAND17.

In this case, a low polarity signal, that is, a scan, is performed at the second logic gate OR2 connected to the second negative AND gate NAND2, the ninth negative AND gate NAND9, and the seventeenth negative AND gate NAND17. The signal is output. That is, the scan signal is output to the second scan line S2 during the second period T2.

The eighth negative AND gate NAND8 receives the driving signal from the first input terminal a1 as the first input signal IN1, and receives the driving signal from the second input terminal a2. IN2). The eighth negative AND gate NAND8 receives the driving signal from the third input terminal a3 as the third input signal IN3. Here, the driving signal of the first input bar terminal / a1. Is the first input bar signal / IN1, the second input bar terminal / a2 drive signal is the second input bar signal / IN2, the third input bar terminal / a3 drive signal is the third input Used as a bar signal (/ IN3).)

Then, a low polarity voltage is output from the eighth negative AND gate NAND8 during the eighth period T2. On the other hand, since the fourth input bar signal / a4, the fifth input bar signal / a5, and the sixth input bar signal / a6 are set to high polarity during the eighth period T8, the ninth negative logical product. A low polarity voltage is output from the gate NAND9. In addition, since the seventh input bar signal / a7, the eighth input bar signal / a8, and the ninth input bar signal / a9 are set to high polarity during the eighth period T8, the seventeenth negative logical product The low polarity voltage is output from the gate NAND17.

In this case, a low polarity signal, that is, a scan, is performed at the eighth logic gate OR8 connected to the eighth negative AND gate NAND8, the ninth negative AND gate NAND9, and the seventeenth negative AND gate NAND17. The signal is output. That is, the scan signal is output to the eighth scan line S8 during the eighth period T2.

In this manner, the scan driver of the present invention sequentially supplies the scan signal to the scan lines S1 to S320. Here, the scan driver of the present invention is composed of negative AND gates NAND1 to NAND21 made of PMOS and OR gates OR1 to OR320 made of PMOS. That is, the scan driver of the present invention can be mounted on a panel of an organic light emitting display device.

Meanwhile, although FIG. 3 illustrates a connection configuration in which scan signals are sequentially supplied to the scan lines S1 to S320, the present invention is not limited thereto. Currently, a method of digitally driving an organic light emitting display device has been proposed to compensate for voltage deviations of pixels of the organic light emitting display device. The digital method is a method of displaying a predetermined image by supplying a data signal of "1" or "0" and controlling the emission time of each pixel.

When driving the digital system by dividing it into sub-frame units, there is a problem in that a contour noise is generated. Therefore, a method of supplying an arbitrary line without supplying scan signals sequentially has been proposed. For example, after the scan signal is supplied to the tenth scan line S10 and the scan signal is supplied to the 60th scan line S60, the non-emission time is reduced to remove pseudo contour noise. Here, the scan driver of the present invention can simply supply the scan signal by an arbitrary line by changing the drive waveform shown in FIG. 4 and / or the connection configuration shown in FIG.

For example, the first logic gate OR1 may be connected to the tenth scan line S10, and the second logic gate OR2 may be connected to the 60th scan line S60. In other words, the present invention has an advantage in that it is possible to supply the scan signal to a place to be supplied by changing the connection positions of the first logical gates OR1 to OR320, and thus it is easily applicable to digital driving.

Meanwhile, in the present invention, as shown in FIG. 6B, the high polarity period may be set longer than the low polarity period in the driving waveforms supplied to the output terminals a1 to a9 and / a1 to / a9.

In detail, the period of the high polarity in the driving waveform supplied to the first input terminal a1 is set longer than the period of the low polarity. The period of high polarity is set longer than the period of low polarity in the driving waveform supplied to the first input bar terminal / a1. In this case, the driving waveform supplied to the first input bar terminal / a1 is not generated by the inverter INV1 but is supplied from the outside. As described above, when the period of the high polarity is set longer than the period of the low polarity in the driving waveform, the row periods can be prevented from overlapping by a delay or the like, thereby ensuring stable driving.

7 is a diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 7, an organic light emitting display device according to an exemplary embodiment of the present invention includes a pixel unit including pixels 140 formed at an intersection area of scan lines S1 to Sn and data lines D1 to Dm. 130, the scan driver 110 for driving the scan lines S1 to Sn, the data driver 120 for driving the data lines D1 to Dm, the scan driver 110 and the data driver 120. ), A timing controller 150 for controlling.

The data driver 120 generates data signals in response to the data driving control signal DCS supplied from the timing controller 150, and supplies the generated data signals to the data lines D1 to Dm. In this case, the data driver 120 supplies one line of data signals to the data lines D1 to Dm for each horizontal period 1H.

The scan driver 110 generates a scan signal in response to a scan drive control signal SCS (for example, a driving waveform as shown in FIG. 4) supplied from the timing controller 150, and generates the scan signal through the scan lines ( S1 to Sn). Here, the scan signals generated by the scan driver 110 are supplied to the scan lines S1 to Sn in any order or sequentially. As illustrated in FIG. 3, the scan driver 110 includes a plurality of negative AND gates made of PMOS transistors and a plurality of OR gates.

Meanwhile, the decoders 30, 32, and 34 included in the scan driver 110 may be formed in the form of an integrated circuit in the data driver 120 to reduce the mounting area of the panel. In other words, the data driver 120 is formed to include the decoders 30, 32, and 34 when the chip of the data driver 120 is formed. In addition, by electrically connecting the OR gates formed in the panel and the decoders 30, 32, and 34, the scan driver 110 may be stably driven while reducing the mounting area of the panel.

The timing controller 150 generates a data drive control signal DCS and a scan drive control signal SCS in response to external synchronization signals. The data driving control signals DCS generated by the timing controller 150 are supplied to the data driver 120, and the scan driving control signals SCS are supplied to the scan driver 110. The timing controller 150 rearranges the data Data supplied from the outside and supplies the data to the data driver 120.

The pixel unit 130 receives the first driving power ELVDD and the second driving power ELVSS from the outside and supplies the first driving power ELVDD and the second driving power ELVSS to each of the pixels 140. The pixels 140 supplied with the first driving power source ELVDD and the second driving power source ELVSS receive a second driving power source from the first driving power source ELVDD via the organic light emitting diode OLED in response to a data signal. Control the amount of current flowing to ELVSS.

The above detailed description and drawings are merely exemplary of the present invention, but are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the meaning or claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the logic gate, the scan driver using the same, and the organic light emitting display device according to the exemplary embodiment of the present invention, the scan driver may be configured by using negative AND gates made of PMOS and logical sum gates made of PMOS. have. In this case, since the transistors included in the scan driver are all set to PMOS, the transistors can be mounted on the panel without increasing the number of masks, thereby reducing manufacturing costs. In addition, the scan driver of the present invention can variously set the order of the scan signals supplied to the scan lines by changing the connection between the driving waveforms or the logic gates, and thus can be easily applied to various driving methods.

Claims (38)

A second power supply set to a first power supply and a voltage value lower than the first power supply; A control transistor positioned between the first power supply and the second power supply, and having an output terminal connected to its first electrode; A first driver disposed between the first electrode of the control transistor and the first power source and controlling a connection between the first electrode and the first power source in response to a plurality of input signals supplied from the outside; A second driver positioned between the first electrode and the gate electrode of the control transistor and controlling a connection between the first electrode and the gate electrode of the control transistor in response to the plurality of input signals; A third driver disposed between the gate electrode of the control transistor and the second power source and controlling a connection between the gate electrode of the control transistor and the second power source in response to a plurality of input bar signals input from the outside; To; And wherein each of the first driver, the second driver, and the third driver includes a plurality of transistors, wherein the transistors and the control transistor are formed of a PMOS. The method of claim 1, And a capacitor positioned between the first electrode and the gate electrode of the control transistor. The method of claim 1, The first driver includes the plurality of transistors connected in parallel between the first power supply and the first electrode of the control transistor, and each of the transistors turned on or off by different input signals. Logic gate The method of claim 3, wherein The first driving unit A first transistor controlled by a first input signal of the input signals; A second transistor controlled by a second input signal of the input signals; And a third transistor controlled by a third input signal among the input signals. The method of claim 1, The second driver includes the plurality of transistors connected in parallel between the first electrode and the gate electrode of the control transistor, each of which is turned on or off by different input signals. Logic gates. The method of claim 5, The second driving unit A fourth transistor controlled by a first input signal of the input signals; A fifth transistor controlled by a second input signal of the input signals; And a sixth transistor controlled by a third input signal among the input signals. The method of claim 1, The third driver includes the plurality of transistors connected in series between a gate electrode of the control transistor and the second power source, each of which is turned on or off by different input bar signals. Logic gate. The method of claim 7, wherein The third driving unit An eighth transistor controlled by a first input bar signal among the input bar signals; A ninth transistor controlled by a second input bar signal among the input bar signals; And a tenth transistor controlled by a third input bar signal among the input bar signals. The method of claim 1, And the input signals and the input bar signals have a longer period of high polarity than a period of low polarity. The method of claim 1, The first driver and the second driver output an output corresponding to a negative logical product by electrically blocking the first power source, the first electrode of the control transistor, and the gate electrode when all of the input signals are set to a high polarity signal. And control the output to the output terminal. A second power supply set to a first power supply and a voltage value lower than the first power supply; A first driver positioned between the first power source and the first node and controlling a voltage of the first node in response to a plurality of input signals supplied from the outside; A second driver positioned between the first node and the second power source to control a voltage value of the first node; A third driver positioned between the first power source and the output terminal and controlling whether the first power source and the output terminal are connected by a voltage value applied to the first node; A control transistor connected between the third driver and the second power source; A fourth driver connected between the gate electrode of the control transistor and the second power source and controlling a connection between the gate electrode of the control transistor and the second power source in response to the plurality of input signals; And each of the first driver, the second driver, the third driver, and the fourth driver includes a plurality of transistors, and the transistors and the control transistor are formed of a PMOS. The method of claim 11, And the first driver includes the plurality of transistors connected in series between the first power supply and the first node, each of which is turned on or turned off by different input signals. gate. The method of claim 12, The first driving unit A first transistor controlled by a first input signal of the input signals; A second transistor controlled by a second input signal of the input signals; And a third transistor controlled by a third input signal among the input signals. The method of claim 13, The second driving part maintains the first node at the voltage of the first power supply when the voltage of the first power supply is supplied from the first driving part to the first node. Otherwise, the second driving part maintains the first node. A logic gate, characterized in that held at the voltage of the second power supply. The method of claim 14, The second driving unit A fourth transistor connected between the first node and the second power source; A fifth transistor having its first electrode connected to the gate electrode of the fourth transistor, and having a second electrode and a gate electrode connected to the second power source; And a capacitor connected between the first electrode and the gate electrode of the fourth transistor. The method of claim 15, The channel / length ratio of the fourth transistor is set to be narrower than the channel / length ratio of each of the first transistor, the second transistor and the third transistor. The method of claim 11, The third driving unit When the voltage of the second power source is applied to the first node, the first electrode and the first power source of the control transistor are electrically connected. Otherwise, the first electrode and the first power source of the control transistor are electrically connected. A sixth transistor for blocking by; When the voltage of the second power source is applied to the first node, the first electrode and the gate electrode of the control transistor are electrically connected. Otherwise, the first electrode and the gate electrode of the control transistor are electrically blocked. And a seventh transistor. The method of claim 17, The first driving unit controls an output corresponding to a logic sum to be supplied to the output terminal by connecting the first node and the first power supply when all of the input signals are set to low polarity signals. Logic gates. The method of claim 11, The fourth driver includes a plurality of transistors connected in series between the gate electrode of the control transistor and the second power source, each of which is turned on or off by different input signals. Logic gates. The method of claim 11, The fourth driving unit A ninth transistor controlled by a first input signal of the input signals; A tenth transistor controlled by a second input signal of the input signals; And an eleventh transistor controlled by a third input signal among the input signals. The method of claim 11, And a capacitor positioned between the first electrode and the gate electrode of the control transistor. At least one decoder having a plurality of negative AND gates, A plurality of OR gates, each of which is connected to different scan lines and ORs the outputs of the decoder to generate a scan signal, And each of the negative AND gates and the OR gates includes a plurality of PMOS transistors. The method of claim 22, A plurality of input terminals provided at each of the decoders to receive input signals from the outside; And a plurality of inverters connected to each of the input terminals for inverting the input signals. The method of claim 22, And a plurality of input terminals provided at each of the decoders to receive input signals and input bar signals from an external device, wherein the driving signal and the input bar signals have a longer period of high polarity than a period of low polarity. Scan driving unit. The method of claim 22, Each of the negative AND gates A second power supply set to a first power supply and a voltage value lower than the first power supply; A control transistor positioned between the first power supply and the second power supply, and having an output terminal connected to its first electrode; A plurality of first transistors disposed in parallel between the first electrode of the control transistor and the first power source and receiving different input signals from outside; A plurality of second transistors disposed in parallel between the first electrode and the gate electrode of the control transistor and receiving the different input signals; And a plurality of third transistors disposed in series between the gate electrode of the control transistor and the second power supply and receiving input bar signals having polarities inverted from the input signals. The method of claim 25, And a capacitor connected between the first electrode and the gate electrode of the control transistor. The method of claim 22, Each of the OR gates With control transistors, A second power supply set to a first power supply and a voltage value lower than the first power supply; A plurality of first transistors disposed in series between the first power source and the first node and receiving different input signals from outside; A fourth transistor disposed between the first node and a second power source; A fifth transistor having a first electrode connected to a gate electrode of the fourth transistor, and a second electrode and a gate electrode connected to the second power source; A sixth transistor positioned between the first power supply and the first electrode of the control transistor, the sixth transistor being turned on or off in response to a voltage applied to the first node; A seventh transistor connected between the first electrode and the gate electrode of the control transistor and turned on or off in response to a voltage applied to the first node; And second transistors disposed in series between the gate electrode of the control transistor and the second power supply and receiving the different input signals. The method of claim 27, A first capacitor connected between the gate electrode and the first electrode of the fourth transistor; And a second capacitor connected between the gate electrode and the first electrode of the control transistor. A data driver for supplying a data signal to the data lines; A scan driver for supplying a scan signal to the scan lines; A plurality of pixels connected to the data line and the scan line and configured to charge a voltage corresponding to the data signal when the scan signal is supplied; The scan driver At least one decoder having a plurality of negative AND gates, A plurality of OR gates, each of which is connected to different scan lines and ORs the outputs of the decoder to generate a scan signal, And each of the negated AND gates and the AND gates is formed of a plurality of PMOS transistors. The method of claim 29, And the PMOS transistors included in the scan driver are formed on the panel at the same time as the pixels. The method of claim 29, And the negative AND gates are included in the data driver manufactured in a chip form, and the OR gates are formed in a panel on which the pixels are formed. The method of claim 29, A plurality of input terminals provided at each of the decoders to receive input signals from the outside; And a plurality of inverters connected to each of the input terminals for inverting the input signals. The method of claim 29, And a plurality of input terminals provided at each of the decoders to receive input signals and input bar signals from the outside, wherein the input signals and the input bar signals have a longer period of high polarity than a period of low polarity. Organic light emitting display device. The method of claim 29, Each of the negative AND gates A second power supply set to a first power supply and a voltage value lower than the first power supply; A control transistor positioned between the first power supply and the second power supply, and having an output terminal connected to its first electrode; A plurality of first transistors disposed in parallel between the first electrode of the control transistor and the first power source and receiving different input signals from outside; A plurality of second transistors disposed in parallel between the first electrode and the gate electrode of the control transistor and receiving the different input signals; And a plurality of third transistors disposed in series between the gate electrode of the control transistor and the second power supply and receiving input bar signals having polarities inverted from the input signals. Device. The method of claim 34, And a capacitor connected between the first electrode and the gate electrode of the control transistor. The method of claim 29, Each of the OR gates With control transistors, A second power supply set to a first power supply and a voltage value lower than the first power supply; A plurality of first transistors disposed in series between the first power source and the first node and receiving different input signals from outside; A fourth transistor disposed between the first node and a second power source; A fifth transistor having a first electrode connected to a gate electrode of the fourth transistor, and a second electrode and a gate electrode connected to the second power source; A sixth transistor positioned between the first power supply and the first electrode of the control transistor, the sixth transistor being turned on or off in response to a voltage applied to the first node; A seventh transistor connected between the first electrode and the gate electrode of the control transistor and turned on or off in response to a voltage applied to the first node; And second transistors disposed in series between the gate electrode of the control transistor and the second power source and receiving the input signals different from each other. The method of claim 36, A first capacitor connected between the gate electrode and the first electrode of the fourth transistor; And a second capacitor connected between the gate electrode and the first electrode of the control transistor. The method of claim 29, And the decoders are configured to receive input signals and to receive a high frequency input signal, the decoder being disposed adjacent to the OR gates.

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