KR920003661A - NANDGATE and NOAGATE decoder circuits - Google Patents

NANDGATE and NOAGATE decoder circuits Download PDF

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Publication number
KR920003661A
KR920003661A KR1019900010727A KR900010727A KR920003661A KR 920003661 A KR920003661 A KR 920003661A KR 1019900010727 A KR1019900010727 A KR 1019900010727A KR 900010727 A KR900010727 A KR 900010727A KR 920003661 A KR920003661 A KR 920003661A
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KR
South Korea
Prior art keywords
gate
transistor
series
mos transistor
transistors
Prior art date
Application number
KR1019900010727A
Other languages
Korean (ko)
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KR930007567B1 (en
Inventor
박동명
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019900010727A priority Critical patent/KR930007567B1/en
Publication of KR920003661A publication Critical patent/KR920003661A/en
Application granted granted Critical
Publication of KR930007567B1 publication Critical patent/KR930007567B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

내용 없음No content

Description

낸드게이트 및 노아게이트의 디코더회로NANDGATE and NOAGATE decoder circuits

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명의 디코더 회로도,4 is a decoder circuit diagram of the present invention;

제5도는 제4도의 게이트를 낸드게이트로 사용한 간략도,5 is a simplified diagram using the gate of FIG. 4 as a NAND gate,

제6도는 제4도의 게이트를 노아게이트로 사용한 간략도.6 is a simplified diagram using the gate of FIG. 4 as a noble gate.

Claims (2)

다수의 입력신호(A1- AN)와 인버터게이트(I1- IN)로부터 반전된 신호를 게이트(G1)(G2)에서 디코딩하여 출력하는 디코더회로에 있어서, 상기 게이트(G1) (G2)는 풀업회로(PI1)에 엔-모스트랜지스터(NM1- NMN)를 직렬 연결하여 출력(OUT1)을 얻고, 반전신호()가 인가되는 엔 - 모스트랜지스터(NM1')는 상기 엔 - 모스트랜지스터(NM2- NMN)와 직렬 연결하고, 입력신호가(A1)가 인가되는 엔 - 모스트랜지스터(NM2')는 반전신호()가 인가되는 엔 - 모스트랜지스터(NM3- NMN)와 직렬연결함과 아울러 이와같은 순으로 엔 - 모스트랜지스터를 순차적으로 연결 구성하여 낸드화시킨 것을 특징으로 한 낸드게이트 및 노아게이트의 디코더회로.Inverted signals from a plurality of input signals A 1 -A N and inverter gates I 1 -I N The - (NM N NM 1) - the gate (G 1) in the decoder circuit for decoding the output from the (G 2), the gate (G 1) (G 2) is a pull-up circuit (PI 1) yen the MOS transistor Connect in series to get output (OUT 1 ), and reverse signal ( N-most transistors (NM 1 ') to which n is applied are connected in series with the N -most transistors (NM 2 to NM N ), and n -most transistors (NM 2 ') to which an input signal (A 1 ) is applied. Is the inversion signal ( ) Is connected in series with N -MOS transistor (NM 3 -NM N ) to which N ) is applied, and N- gate transistor and NOR gate decoder circuit is characterized in that N-MOS transistor is sequentially connected and configured in this order. . 제1항에 있어서, 상기 게이트(G1)(G2)는 풀다운회로(PD1)에 다수의 피 - 모스트랜지스터(PM1- PMN)를 직렬 연결하고, 반전신호()가 인가되는 피 - 모스트랜지스터 (PM1')는 피 - 모스트랜지스터(PM2- PMN)와 순차적으로 직렬연결하고, 입력신호(A1)가 인가되는 피-모스트랜지스터(PM2')는 피-모스트랜지스터(PM1")와 직렬 연결한 후 다시 피 - 모스트랜지스터(PM3- PMN)와 순차적으로 직렬 연결하여 노아게이트 조합으로 구성함을 특징으로 한 낸드게이트 및 노아게이트의 디코더회로.The method of claim 1, wherein the gate (G 1 ) (G 2 ) is connected in series to a plurality of P-most transistors (PM 1 -PM N ) to the pull-down circuit (PD 1 ), the inverted signal ( ) Is applied to the P-most transistor (PM 1 ') is connected in series with the P-most transistor (PM 2 -PM N ) in sequence, the P-most transistor (PM 2 ') to which the input signal (A 1 ) is applied. Decoder of NAND gate and NORGATE are characterized in that they are connected to P-MOS transistor (PM 1 ″) and then serially connected to P-MOS transistor (PM 3 -PM N ) and composed of Noah gate combination. Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900010727A 1990-07-14 1990-07-14 Multiinput decoder circuit KR930007567B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900010727A KR930007567B1 (en) 1990-07-14 1990-07-14 Multiinput decoder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900010727A KR930007567B1 (en) 1990-07-14 1990-07-14 Multiinput decoder circuit

Publications (2)

Publication Number Publication Date
KR920003661A true KR920003661A (en) 1992-02-29
KR930007567B1 KR930007567B1 (en) 1993-08-12

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900010727A KR930007567B1 (en) 1990-07-14 1990-07-14 Multiinput decoder circuit

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KR (1) KR930007567B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100748359B1 (en) * 2006-08-08 2007-08-09 삼성에스디아이 주식회사 Logic gate, scan driver and organic light emitting display using the same
KR100748361B1 (en) * 2006-08-08 2007-08-09 삼성에스디아이 주식회사 Logic gate, scan driver and organic light emitting display using the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101182445B1 (en) 2010-04-01 2012-09-12 삼성디스플레이 주식회사 Flat display device and the manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100748359B1 (en) * 2006-08-08 2007-08-09 삼성에스디아이 주식회사 Logic gate, scan driver and organic light emitting display using the same
KR100748361B1 (en) * 2006-08-08 2007-08-09 삼성에스디아이 주식회사 Logic gate, scan driver and organic light emitting display using the same

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Publication number Publication date
KR930007567B1 (en) 1993-08-12

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