KR100738216B1 - Current mirror - Google Patents

Abstract

A current mirror is provided to compensate a current error between transistors by charging a gate voltage and a drain voltage of the transistor through a capacitor, and mirroring a current through the charged voltage. A current mirror includes a constant current source(I2), a first transistor(PM1), a first capacitor(C1), a second transistor(PM2), a second capacitor(C2), loads(C,D), a first switch unit(S1), and a second switch unit(S5). The constant current source(I2) provides a constant current. A drain node of the first transistor(PM1) is connected to an end of the constant current source(I2). The first capacitor(C1) is connected between a gate node and a source node of the first transistor(PM1). A drain node of the second transistor(PM2) is connected to the end of the constant current source(I2) and the drain node of the first transistor(PM1) in common. The second capacitor(C2) is connected between a gate node and a source node of the second transistor(PM2). An end of the loads(C,D) is connected to the end of the constant current source(I2), the drain node of the first transistor(PM1), and the drain node of the second transistor(PM2) in common. The first switch unit(S1) switches on/off a current path of the constant current source(I2), the first transistor(PM1) and the loads(C,D). The second switch unit(S5) switches on/off a current path of the constant current source(I2), the second transistor(PM2), and the loads(C,D).

Description

Current mirror

1 is a circuit diagram of a general current mirror.

2 is a circuit diagram of a current mirror according to the present invention.

FIG. 3 is a diagram for describing an operation of the current mirror shown in FIG. 2.

<Explanation of symbols for main parts of the drawings>

M1, M2, PM1, PM2: PMOS I1, I2: Constant current source

C1, C2: Capacitors A, C, D: Load

The present invention relates to a current mirror, and more particularly, to a current mirror capable of correcting a current error, such as deviation in the manufacturing process, channel length modulation.

In general, current mirrors are the basic circuits for various applications such as differential amplifiers and comparators. Such current mirrors generate current errors between transistors due to variations in the manufacturing process such as threshold voltages, mobility, and channel length modulation of each MOS.

1 illustrates a general current mirror circuit, wherein a grounded current source I1, a first PMOS M1 connected to a source I1 and a source, a gate and a source are connected, and a first PMOS ( It consists of the 2nd PMOS M2 with M1) and gate connected in common. At this time, reference numeral A denotes a circuit block to which a current mirror is applied.

 In the current mirror shown in FIG. 1, the voltage between the drain and the source of the first PMOS M1 is equal to the voltage between the gate and the drain since the gate and the source are connected. On the other hand, the voltage between the drain and the source of the second PMOS M2 changes in the width of the depletion layer near the drain region when the voltage between the drain and the source changes, that is, the channel length is changed. It is different from the voltage between the drain and the source of the first PMOS M1. Therefore, there is a problem that currents flowing in the first PMOS M1 and the second PMOS M2 are different from each other.

The current flowing through the general transistor device is represented by Equation 1 below.

는 n채널 혹은 p채널의 이동도를,

는 트랜지스터의 게이트 절연막의 커패시턴스를,

는 채널의 폭,

은 채널의 길이,

는 게이트-소스 간 전압,

은 문턱 전압,

는 채널 길이 모듈레이션 계수를 각각 나타낸 것이다.At this time, each of the transistors

Is the mobility of n or p channels,

Is the capacitance of the gate insulating film of the transistor,

Is the width of the channel,

Is the length of the channel,

The gate-source voltage,

Silver threshold voltage,

Are the channel length modulation coefficients, respectively.

가 달라짐으로써, 트랜지스터에 흐르는 전류(I) 또한 달라지게 된다. 따라서, 이러한 전류 미러를 적용한 회로 설계시, 불안정한 동작의 원인이 되기도 한다. 특히, 유기 전계 발광 디스플레이와 같이 전류에 의한 데이터 구동이 이루어지는 경우에는 이러한 전류 오차는 전혀 다른 데이터를 구동하므로 심각한 동작 오류를 발생하는 원인이 된다.According to Equation 1, the voltage between the drain and the source of the first PMOS M1 is equal to the voltage value between the gate and the source of the first PMOS M1, whereas the voltage between the drain and the second PMOS M2 is equal to the voltage value. The voltage between the sources may vary in voltage between the drain and the source of the second PMOS M2 due to channel length modulation. Therefore, as shown in Equation 1 above,

By varying, the current I flowing through the transistor also changes. Therefore, when designing a circuit employing such a current mirror, it may cause unstable operation. In particular, in the case of driving data by current such as an organic electroluminescent display, this current error drives a completely different data, which causes a serious operation error.

SUMMARY OF THE INVENTION An object of the present invention for solving the above-mentioned problems is to provide a current mirror and a method for correcting the current error that can correct current errors between transistors caused by variations in the manufacturing process and channel length modulation. have.

Current mirror according to the present invention for achieving the above object of the present invention is a constant current source for supplying a constant current; A first transistor having a drain terminal connected to one end of the constant current source; A first capacitor connected between the gate terminal and the source terminal of the first transistor; A second transistor having a drain terminal commonly connected to one end of the constant current source and the drain end of the first transistor; A second capacitor connected between the gate terminal and the source terminal of the second transistor; A load whose one end is commonly connected to one end of the constant current source, the drain end of the first transistor and the drain end of the second transistor; A first switch unit for interrupting a current path between the constant current source, the first transistor, and the load; And a second switch unit for interrupting a current path between the constant current source, the second transistor, and the load.

The load may include a first load and a second load, one end of which is commonly connected to one end of the constant current source, the drain end of the first transistor, and the drain end of the second transistor, and connected in parallel with each other.

The first switch unit has a first switch, one end of which is connected to one end of the constant current source, a second switch of which one end is connected to the drain terminal of the first transistor, and the other end of which is connected to the other end of the first switch, and one end of the first switch. And a third switch connected in common with the other end of the first switch and the other end of the second switch and the other end connected to one end of the first load.

The second switch part has a fourth switch having one end connected in common with the other end of the first switch, the other end of the second switch, and the one end of the third switch, and one end connected with the drain end of the second transistor and the other end of the second switch. A fifth switch connected to the other end of the fourth switch, and a sixth switch having one end connected in common with the other end of the fourth switch and the other end of the fifth switch, and the other end connected with one end of the second load. It is done.
When the first switch and the second switch is turned on, the voltage is charged to the first capacitor.
When the first switch, the fourth switch and the fifth switch is turned on, the voltage is charged to the second capacitor.
When the second switch, the third switch, the fifth switch and the sixth switch are turned on, the same current flows in the first transistor and the second transistor.
The magnitude of the voltage charged in the first capacitor and the magnitude of the voltage charged in the second capacitor are different from each other.

delete

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 shows a circuit diagram of a current mirror according to the present invention, in which two PMOS transistors PM1 and PM2, two capacitors C1 and C2, a constant current source I2, a load C and D, and It consists of six switch sections.

In detail, the current mirror according to the present invention includes a first transistor PM1 and a first transistor PM1 having a constant current source I2 for supplying a constant current and a drain terminal connected to one end of the constant current source I2. The first capacitor C1 and the drain terminal connected between the gate terminal and the source terminal of the second transistor PM2 and the second transistor are commonly connected to one end of the constant current source I2 and the drain terminal of the first transistor PM1. The second capacitor C2 connected between the gate terminal and the source terminal of the PM2, one end thereof is common to one end of the constant current source I2, the drain end of the first transistor PM1, and the drain end of the second transistor PM2. Between the first switch unit and the constant current source I2, the second transistor PM2, and the load that control the current path between the connected loads C and D, the constant current source I2, the first transistor PM1, and the load It includes a second switch unit for interrupting the current path of.
The first load C and the second load, one end of which is commonly connected to one end of the constant current source I2, the drain end of the first transistor PM1, and the drain end of the second transistor PM2, and connected in parallel with each other ( D).
A first switch S1 having one end connected to one end of the constant current source I2, and one end connected to the drain end of the first transistor PM1 and the other end connected to the other end of the first switch S1. The second switch S2, and the third switch S3 having one end connected in common with the other end of the first switch S1 and the other end of the second switch S2 and the other end connected with one end of the first load C It may include.
One end of the second switch unit is connected to the other end of the first switch S1, the other end of the second switch S2, and one end of the third switch S3, and one end of the second transistor PM2. A fifth switch S5 connected to the drain end of the second switch and the other end connected to the other end of the fourth switch S4, and one end is commonly connected to the other end of the fourth switch S4 and the other end of the fifth switch S5, The other end may include a sixth switch S6 connected to one end of the second load D.
For example, the two PMOS transistors PM1 and PM2 are connected between the gate and the source through the capacitors C1 and C2, respectively. The constant current source I2 is connected to the first transistor PM1 through two switches S1 and S2, and also connected to the second transistor PM2 through three switches S1, S4 and S5. The load C is connected to the first transistor PM1 through two switches S2 and S3, and the second load D is connected to the second transistor PM2 through two switches S5 and S6. Connected.

The operation according to the configuration will be described in detail as follows.

As described above, due to the variation in the manufacturing process of the current mirror, it is impossible to mirror the current of the same size and have a current error between the transistors. Therefore, in a circuit that needs to control precise current, such a current error greatly affects its operation. Therefore, the present invention proposes a method for compensating for current error due to variations in the manufacturing process, channel length modulation, and the like.

In FIG. 2, the constant current by the constant current source I2 is mirrored so that the same amount of current flows through the first and second transistors PM1 and PM2. However, as described above, due to the variation in the manufacturing process, the amount of current by the constant current source I2 may not be equally mirrored to the first and second transistors. Therefore, in order to compensate for the current error, capacitors C1 and C2 are respectively connected between the gate and the source of the first and second transistors PM1 and PM2 and switches S1 to S6 are connected to each current path. At this time, the mirrored transistors PM1 and PM2 may further increase the number.

When the currents flowing in the first and second transistors PM1 and PM2 are referred to as Ip4 and Ip5, respectively, the following equations are used.

, W/L,

등의 서로 다른 값을 갖더라도 게이트와 소스 사이에 연결된 두 개의 커패스터(C1, C2)에 충전되는 전압이 서로 다른

전압으로 충전되므로 두 트랜지스터(PM1, PM2)에 흐르는 전류량은 같아지게 되므로 두 트랜지스터(PM1, PM2) 상호 간의 전류 오차를 보상시킬 수가 있게 된다. In Equation 2, since Ip4 and Ip5 are commonly connected by the constant current source I2, the same current value is the same. As previously discussed, the threshold voltages due to variations in the manufacturing process of each transistor

, W / L,

The voltages charged to the two capacitors C1 and C2 connected between the gate and the source are different even though they have different values such as

Since the voltage is charged with the voltage, the amount of current flowing through the two transistors PM1 and PM2 becomes equal, thereby compensating for the current error between the two transistors PM1 and PM2.

In this case, the switching operation will be described in more detail with reference to FIG. 3.

As shown in FIG. 3, the current mirror according to the present invention operates by being divided into a charging period and a driving period to compensate for the current error.

First, the charging cycle is a cycle in which the capacitors C1 and C2 are charged. In order to perform the charging of the capacitor C1 connected to the first transistor PM1, the switches S1 and S2 are closed during the period A of the charging cycle. That is, when the first switch S1 and the second switch S2 are turned on, the voltage is charged in the first capacitor C1. Therefore, charging of the capacitor C1 is performed during the A period. In addition, during the period B, when the first switch S1, the fourth switch S4, and the fifth switch S5 are turned on, the voltage is charged to the second capacitor C2. As such, the charging cycle in which the gate-source voltage V _GS is charged in each of the first capacitor S1 and the second capacitor S2 ends.

, W/L,

등의 파라미터 값이 서로 다른 제조 공정상의 편차로 인한 오차를 보상하여 제1트랜지스터(PM1) 및 제2트랜지스터(PM2)에 흐르는 전류를 일정하게 할 수 있다. Subsequently, the driving cycle is switched off with the constant current source I2 as the S2 and S4 switches are opened after the charging cycle is finished, and the S2, S3, and S5 and S6 switches are closed, thereby performing the current mirror operation by the charged voltage. That is, when the second switch S2, the third switch S3, the fifth switch S5, and the sixth switch S6 are turned on, the same current flows through the first transistor PM1 and the second transistor PM2. do. As such, different voltages are charged in the first capacitor C1 and the second capacitor C2 so that the threshold voltages of the first transistor PM1 and the second transistor PM2 are described above.

, W / L,

By compensating for errors due to variations in manufacturing processes having different parameter values, the current flowing through the first transistor PM1 and the second transistor PM2 may be constant.

That is, charging is performed by the capacitors C1 and C2 for a relatively short charging period, and thereafter, actual driving is performed by the charging voltage during the driving cycle. can do.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the current mirror according to the present invention is a method of charging the gate and drain voltage of the transistor through the capacitor to the current error caused by the variation in the manufacturing process, channel length modulation, etc. using the charged voltage current mirroring By applying this, there is an effect that it can be corrected.

Claims (8)

A constant current source for supplying a constant current; A first transistor having a drain terminal connected to one end of the constant current source; A first capacitor connected between the gate terminal and the source terminal of the first transistor; A second transistor having a drain terminal commonly connected to one end of the constant current source and the drain end of the first transistor; A second capacitor connected between the gate terminal and the source terminal of the second transistor; A load whose one end is commonly connected to one end of the constant current source, the drain end of the first transistor and the drain end of the second transistor; A first switch unit for interrupting a current path between the constant current source, the first transistor, and the load; And A second switch unit for interrupting a current path between the constant current source, the second transistor, and the load; A current mirror comprising a. The method of claim 1, Said load And a first load and a second load, one end of which is commonly connected to one end of the constant current source, the drain end of the first transistor and the drain end of the second transistor, and connected in parallel with each other. The method of claim 2, The first switch unit A first switch having one end connected to one end of the constant current source, A second switch having one end connected to the drain end of the first transistor and the other end connected to the other end of the first switch; and And a third switch having one end connected in common with the other end of the first switch and the other end of the second switch, and the other end connected with one end of the first load. The method of claim 3, The second switch unit A fourth switch having one end connected in common with the other end of the first switch, the other end of the second switch, and one end of the third switch; A fifth switch having one end connected to the drain end of the second transistor and the other end connected to the other end of the fourth switch; and And a sixth switch having one end connected in common with the other end of the fourth switch and the other end of the fifth switch, and the other end connected with one end of the second load. The method of claim 4, wherein And a voltage is charged in the first capacitor when the first switch and the second switch are turned on. The method of claim 5, And the voltage is charged to the second capacitor when the first switch, the fourth switch, and the fifth switch are turned on. The method of claim 6, And the same current flows in the first transistor and the second transistor when the second switch, the third switch, the fifth switch, and the sixth switch are turned on. The method of claim 6, The magnitude of the voltage charged in the first capacitor and the magnitude of the voltage charged in the second capacitor is different from each other.

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