KR100736602B1 - Channel equalizer for VSB?QAM - Google Patents

Abstract

VSB / QAM Versatile Channel Equalizer, especially for channel equalization of received signals, depending on whether the received signal is a VSB signal, a QAM signal, and whether it is symbol or fine intervals, real channel equalization or complex channel equalization By generating filter coefficients and controlling the flow of the signal in each case, it is possible to perform channel equalization for VSB and QAM signals with a single equalizer, thus greatly reducing the hardware area for implementing the equalizer. have. In addition, when operating as a fine interval channel equalizer, each circuit element is operated at a symbol frequency or an inverted symbol frequency to omit the decimation operation, or place a decimator located at the output end of the equalizer in the data delay unit. By operating the data delayer twice as fast as the symbol clock only when operating as a finely spaced channel equalizer, the power of the receiver can be reduced.

VSB / QAM combined, symbol / fine spacing, channel equalization

Description

PS / AMA combined channel equalizer {Channel equalizer for VSB ／ QAM}

1 is a block diagram showing a typical VSB signal generation process

2 is a block diagram illustrating a general QAM signal generation process

3 is a block diagram of a typical symbol spacing real channel equalizer for VSB

4 is a block diagram of a typical finely spaced real channel equalizer for VSB

5 is a block diagram of a typical symbol interval complex channel equalizer for VSB

Fig. 6 is a block diagram of a typical finely spaced complex channel equalizer for VSB.

7 is a block diagram of a typical symbol interval complex channel equalizer for QAM

8 is a block diagram of a typical fine-spaced complex channel equalizer for QAM

9A to 9D are overall operation timing diagrams of a VSB / QAM dual-purpose channel equalizer according to the first embodiment of the present invention.

10 is a signal flow diagram when the VSB / QAM dual-purpose channel equalizer according to the first embodiment of the present invention operates as a finely spaced channel equalizer.

11 is a signal flow diagram when the VSB / QAM dual-purpose channel equalizer according to the first embodiment of the present invention operates as a symbol interval channel equalizer.

12 is a block diagram of an overall configuration of a VSB / QAM dual-purpose channel equalizer according to the first embodiment of the present invention.                 

13 is a signal flow diagram when the VSB / QAM dual-purpose channel equalizer of FIG. 12 is used as a real channel equalizer for VSB.

14 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 12 is used as a complex channel equalizer for VSB.

15 is a signal flow diagram when the VSB / QAM dual-purpose channel equalizer of FIG. 12 is used as a complex channel equalizer for QAM.

16 is a block diagram showing the overall configuration of a VSB / QAM dual-purpose channel equalizer according to a second embodiment of the present invention.

17 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 16 is used as a symbol spacing real channel equalizer for VSB.

18 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 16 is used as a finely spaced real channel equalizer for VSB.

19 is a signal flow diagram when the VSB / QAM dual-purpose channel equalizer of FIG. 16 is used as a symbol interval complex channel equalizer for VSB.

20 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 16 is used as a finely spaced complex channel equalizer for VSB.

21 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 16 is used as a symbol spacing complex channel equalizer for QAM.

22 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 16 is used as a finely spaced complex channel equalizer for QAM.                 

Explanation of symbols for main parts of the drawings

102-1 to 102-4: Data delay unit 103-1 to 103-4: Coefficient calculator

104: decision feedback equalizer 105: adder

106: I channel signal output section 107: Q channel signal output section

108-1 to 108-4: Decimator

The present invention relates to a versatile adaptive channel equalizer that can be commonly used in digital VSB receivers and quadrature amplitude modulation (QAM) receivers.

In general, amplitude modulation of a baseband signal to a single carrier yields an output signal having the same information on the upper and lower bands around the carrier on the frequency spectrum. It is not desirable to transmit this output signal in the transmission channel as it is in terms of frequency band utilization efficiency. Therefore, a modulation scheme for transmitting only one sideband of an upper sideband or a lower sideband is required. The method is a single side band (SSB) or a VSB modulation scheme. These two schemes are very similar. In the VSB scheme, additional transmission of some of the remaining sidebands is significantly different from SSB scheme in order to facilitate demodulation at the receiver side.

Meanwhile, digital TV reception technology, which is currently being developed in response to various media (terrestrial wave, cable), is gradually being developed as an integrated system structure, and has a single receiver to receive digital TV transmission signals regardless of the media. Efforts are being made.

Digital TV transmission methods according to such media are largely classified into VSB transmission method using terrestrial wave and QAM transmission method using cable.

In this case, the VSB transmission method loads a desired signal only on a real channel. That is, the input signal is carried only on the I channel. Therefore, Hilbert transforms the I channel signal to produce a Q channel signal. Therefore, the Q channel signal is dependent on the I channel signal.

In the QAM transmission method, a desired signal is loaded on a real channel and an imaginary channel, respectively. That is, different input signals are loaded on the I channel and the Q channel, respectively. Therefore, the I channel signal and the Q channel signal are independent of each other.

FIG. 1 is a block diagram illustrating the generation of such a VSB signal. The VSB baseband input signal x (t) is called an I channel signal.

반송파를 곱하여 가산기(102)로 출력한다.At this time, the I-channel signal is output to the multiplier 101 and to the Hilbert transformer 103. The multiplier 101 cos the I channel signal.

The carriers are multiplied and output to the adder 102.

반송파를 곱하여 가산기(102)로 출력한다.On the other hand, the Hilbert converter 103 inverts the I channel signal by 90 degrees and outputs the result to the multiplier 104. In this case, the I channel signal x ^h (t) inverted 90 degrees by the Hilbert transform unit 103 is commonly referred to as a Q channel signal. The multiplier 104 adds sin to the Q channel signal.

The carriers are multiplied and output to the adder 102.

반송파로 변조된 I 채널 신호와

반송파로 변조된 Q 채널 신호를 더하여 전송하는데, 상기 가산기(102)의 출력 신호 v(t)는 다음의 수학식 1과 같다.The adder 102

Carrier-modulated I-channel signals

A carrier modulated Q channel signal is added and transmitted. The output signal v (t) of the adder 102 is expressed by Equation 1 below.

In this case, the modulated I, Q channel signals are related to each other in the frequency spectrum, except for a part of the center, the lower band has the same value as the I and Q channel signals, and the upper band has the same magnitude and opposite signs. Has a value of. Therefore, when I and Q channel components are added to each other, only a part of the lower wave and the upper wave remain. That is, the bandwidth of the signal is cut in half.

2 is a block diagram illustrating the generation of the QAM signal, in which the QAM baseband input signal x (t) is sent to the I channel and y (t) is sent to the Q channel.

반송파를 곱하여 가산기(203)로 출력하고, 곱셈기(202)는 상기 Q 채널 신호 y(t)에

반송파를 곱하여 가산기(203)로 출력한다.At this time, the multiplier 201 is applied to the I channel signal x (t).

The carrier wave is multiplied and output to the adder 203, and the multiplier 202 is applied to the Q channel signal y (t).

The carriers are multiplied and output to the adder 203.

반송파로 변조된 I 채널 신호와

반송파로 변조된 Q 채널 신호를 더하여 전송하는데, 상기 가산기(203)의 출력 신호 v'(t)는 다음의 수학식 2와 같다.The adder 203 is

Carrier-modulated I-channel signals

A carrier modulated Q channel signal is added and transmitted. The output signal v '(t) of the adder 203 is expressed by Equation 2 below.

In this case, since the above-described QAM transmission method transmits both sidebands together, it requires twice the bandwidth of the VSB transmission method. However, within this double bandwidth, there are independent signals, x (t) and y (t), so the amount of information is also doubled. That is, the QAM transmission method and the VSB transmission method have the same amount of information in the same bandwidth. In addition, since x (t) and y (t) are modulated by carriers that are orthogonal to each other, it is possible to recover the original signal using this orthogonality without any difficulty on the receiving side.

On the other hand, the signal transmitted from the transmitting end is caused various distortions through the transmission channel. Factors that cause the distortion include Gaussian thermal noise, addition due to fading, or distortion due to multiplication noise, frequency variation, nonlinearity, time dispersion, and the like. Such distortion appears as a deterioration in image quality due to distortion in an existing analog TV system, but in a digital transmission system, a bit detection error occurs at a receiving side, and data restoration is impossible or unexpected. In particular, multiple paths due to time delay and phase change of a transmission signal cause severe intersymbol interference, which is a major cause of bit detection error. The technique of reducing the bit detection error at the receiving side by compensating for distortion caused by the non-ideal transmission channel is called channel equalization. That is, the channel equalizer removes the ghost when the original signal is changed in magnitude and phase due to channel distortion and a time delayed ghost signal is received together with the original signal during signal transmission.

However, since the channel is variable by various factors such as the location, distance, terrain, buildings, weather, etc. of the transceiver, an equalization technique that can be adaptively substituted for the variable channel is required. This technique is called adaptive channel equalization.

In this case, the digital VSB receiver generally uses a symbol interval real adaptive channel equalizer as shown in FIG. 3.

3, N data delays 11-1 to 11-N for delaying the input data x (n) by one symbol, the input data x (n) and the data delays 11-1 to 11 are shown. N + 1 coefficient arithmetic units 12-0 to 12-N for performing coefficient updating by using each output of N and the error value e (n), and each of the coefficient arithmetic units 12-0 to 12-N. An output of the slicer 14 at the output of the adder 13, a slicer 14 estimating an error value e (n) using the output of the adder 13, and an output of the adder 13 The adder 15 calculates an error value e (n) by subtracting the multiplier. In this case, a multiplier 16 for multiplying the output of the adder 15 by the step size μ may be connected to the output terminal of the adder 15. .

Here, the N data delay units 11-1 to 11-N and the N + 1 coefficient calculating units 12-0 to 12-N may include a feed forward filter equalization that cancels the influence of a close ghost; FFE).

Each of the configurations of the coefficient calculating units 12-0 to 12-N is the same, and the first coefficient calculating unit 12-0 is an example of the input data x (n) and the error value e (n). Multiplier (01) to multiply, adder (02) for outputting updated filter coefficients by adding the previous coefficient (c ₁ ) fed back to the output of the multiplier (01), and adder (02) after storing the output of the adder (02) ) Is a multiplier (04) that feeds back to the previous coefficient c ₁ , a multiplier (04) which multiplies the input data x (n) with an updated filter coefficient output through the delay unit (03), and outputs the result to the adder (13). It is composed of

In FIG. 3 configured as described above, input data x (n) is an I channel signal input to the symbol interval real channel equalizer, and x (n-i) is an i symbol delayed value through a data delay.

At this time, the output y (n) of the VSB symbol interval real channel equalizer of FIG.

Where y (n) is the channel equalizer, i.e. the output of adder 13,

        x (n) is the input data,

        c (n) is the channel equalizer coefficient at the current time,

        c (n + 1) is the channel equalizer coefficient of the next time, that is, the updated filter coefficient,

        e (n) is the error value,                         

        μ is the step size.

The step size μ is used to improve the speed of convergence. In other words, in the initial stage, before the adaptive channel equalizer still converges, a large value of step size μ is used to update the coefficient of the equalizer to achieve fast convergence. Use size μ.

In order to update the coefficient of the filter by substituting the error value e (n) obtained by the difference between the signal input from the adder 15 to the slicer 14 and the signal sliced and output from the slicer 14 A multiplier for multiplying e (n) by the input value of the filter is required in each coefficient calculating section 12-0 to 12-N. For example, the multiplier 01 corresponds to the first coefficient calculating unit 12-0.

In addition, the error value e (n) and the output of the slicer 14 are input to a Decision Feedback Equalizer (DFE) 17, which cancels out the influence of distant ghosts, and filtered by the DFE 17. The signal is output to the adder 13 and added. In this case, the DFE may receive only the determined data.

On the other hand, if the phase θ of the ghost is not 0, the demodulated signal has x ^h (t-τ) which is a Hilbert transformed component of the signal x (t-τ) delayed by the delay time τ.

However, these ghost components may not be sufficiently removed by the real channel equalizer and the channel equalizer may not be able to sufficiently follow the channel change.

Accordingly, in order to improve the performance of the receiver, a symbol interval complex channel equalizer for VSB such as FIG. 5 using not only an I channel signal but also a Q channel signal may be used.

Although FIG. 3 performs channel equalization only for the I channel signal, FIG. 5 performs channel equalization not only for the I channel signal but also for the imaginary part of the Q channel signal.

A major difference in configuration with the symbol spacing real channel equalizer of FIG. 3 is that the computation part for the imaginary part is further added. That is, FIG. 5 further adds a filter having the same structure as that of FIG. 3 to channel equalize the Q channel signal. At this time, the output of each coefficient calculating section filtering the I channel signal and the output of each coefficient calculating section filtering the Q channel signal are added to the adder and then output to the slicer. The output of the slicer is output to the DFE and simultaneously to the adder to obtain an error value.

In this case, each of the data delay units of the symbol interval real or complex channel equalizers and the delay units, that is, flip-flops, of the coefficient calculating unit operates by receiving a symbol clock generated in a symbol period.

On the other hand, a typical symbol spacing channel equalizer is equipped with a filter tap of a sufficient length and easily removes interference between symbols by appropriately compensating for distortion of a channel caused by a long time ghost in an external environment. Short ghosts can't be rewarded. In addition, if the symbol time recovery circuit does not operate completely, there is a disadvantage in that performance is deteriorated by symbol time noise.

Therefore, there is a need to use a finely spaced channel equalizer in some cases.                         

In other words, if the input sample takes data oversampled at N times the symbol rate (N> 1.0) and uses N times the finely spaced channel equalizer with N tap coefficients at one symbol position, Degradation is not severe, and relatively short ghosts can be relatively removed compared to symbol interval equalizers.

FIG. 4 is a block diagram illustrating an example of a finely spaced real channel equalizer for a typical VSB. The difference from FIG. 3 is that each delay of the data delay unit and the coefficient operation unit, that is, flip-flops, operates at an N times symbol clock. will be. In FIG. 4, when N is set to 2, the data delay unit and the coefficient calculating unit of FIG. 4 operate twice as fast as the symbol time. That is, the flip-flops of the data delay unit and the coefficient operation unit operate at two times the symbol frequency (that is, 1/2 symbol period).

Therefore, the output of the adder that adds all the data output from each coefficient calculating section has two data for each symbol. One of these is symbol data, and the other is virtual data between symbols. Therefore, if the output of the adder is directly input to the slicer, the slicer malfunctions. To prevent this, the output of the adder is output to an adder that obtains an error value through a decimator for extracting symbol data from two pieces of data per symbol.

That is, the decimator is a 2: 1 decimator extracting only a symbol sample from two samples. When the output of the adder passes through the decimator, data of only the instant of the symbol time comes out. As a result, the slicer, the multiplier that generates the error value, and the DFE portion operate in symbol periods.                         

In this case, the data input to the channel equalizer is data sampled at twice the symbol frequency.

FIG. 6 is a block diagram illustrating an example of a general spacing complex channel equalizer for VSB. The basic configuration is the same as the symbol spacing complex channel equalizer for VSB of FIG. 5. The difference from FIG. 5 is that the data delay and each coefficient operation unit operate in synchronization with a double symbol clock as shown in FIG. 4, which adds a decimator between the adder and the slicer.

Meanwhile, in the digital QAM receiver, the symbol interval complex channel equalizer as shown in FIG. 7 or the fine interval complex channel equalizer as shown in FIG. 8 is used for the reasons mentioned above. In this case, in the case of the QAM transmission method, since the Q channel includes data independent of the I channel, channel equalization for the imaginary part as well as the real part must be performed. That is, no real channel equalizer is used in the QAM receiver.

In this case, the output of the QAM channel equalizer and the coefficient update equation are as shown in Equation 4 below.

Where y (n) is the channel equalizer output,

x _I (n) is the input real data,

x _Q (n) is the input imaginary data,

c _I (n) is the real channel equalizer coefficient at the current time,

c _Q (n) is the imaginary channel equalizer coefficient at the current time,

        c (n + 1) is the channel equalizer coefficient of

e _I (n) is the real error value,

e _Q (n) is the imaginary error value,

        μ is the step size.

The channel equalizer described so far is summarized as follows.

That is, the VSB receiver performs channel equalization using any one of symbol interval real channel equalizer, symbol interval complex channel equalizer, fine interval real channel equalizer, and fine interval complex channel equalizer, and the QAM receiver performs symbol interval complex number. Channel equalization is performed using either a channel equalizer or a finely spaced complex channel equalizer.

However, digital TV reception technology is currently being developed as an integrated system structure integrating various media (ground wave, cable), and each channel equalization described above in an integrated system structure for receiving both VSB modulated signals and QAM modulated signals. The adoption of these features leads to complex hardware, bulky systems, and increased costs.                         

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to control a signal flow so that one channel equalizer is a symbol interval real channel equalizer for VSB, a fine interval real channel equalizer for VSB, a symbol interval for VSB The present invention provides a VSB / QAM multi-purpose channel equalizer operated by any one of a complex channel equalizer, a fine-interval complex channel equalizer for VSB, a symbol-interval complex channel equalizer for QAM, and a fine-interval complex channel equalizer for QAM.

Another object of the present invention is to provide a VSB / QAM dual purpose channel equalizer which reduces power of a receiver by operating each circuit element at a symbol frequency even when operating as a finely spaced channel equalizer.

It is still another object of the present invention to provide a VSB / QAM dual purpose channel equalizer that reduces the power of the receiver by placing a decimator at the output end of the equalizer in the data delay.

In order to achieve the above object, the VSB / QAM dual-purpose channel equalizer according to the present invention includes N data for outputting I channel data or Q channel data by delaying one symbol according to a symbol clock or an inverted symbol clock. Retarder; After multiplying the error value according to the time difference between the I channel or Q channel data output from the data delay unit and the I channel or Q channel symbol interval, and adding the tap coefficient of the previous I or Q channel data fed back to the multiplication result, the symbol N coefficient calculation units outputting a delay of one symbol according to a clock or an inverted symbol clock; A coefficient output unit for adding all of the tap coefficients of the N I or Q channel data updated and output by the N coefficient calculating units, respectively; After slicing the output of the coefficient output unit, an I channel error value is estimated from the difference between the pre-slice signal and the subsequent signal, and the decimation extracts only the data of the symbol position even when the channel equalizer is used as the finely spaced channel equalizer. I-channel signal output unit not to; After slicing the output of the coefficient output unit, the Q channel error value is estimated from the difference between the pre-slice signal and the subsequent signal, and the decimation extracts only the data of the symbol position even when the channel equalizer is used as the fine interval channel equalizer. It characterized in that it comprises a Q channel signal output unit that does not perform.

When the channel equalizer is used as a finely spaced channel equalizer, the data delay unit and the coefficient operation unit input the odd-numbered (or even-numbered) I or Q channel data by delaying one symbol in synchronization with a symbol clock and then perform coefficient update. The I-channel or Q-channel data input in even-numbered (or odd-numbered) bits are delayed by one symbol in synchronization with the inverted symbol clock, and then coefficient updating is performed.

When the channel equalizer is used as a fine interval channel equalizer, the data delay unit and the coefficient calculating unit operate in synchronization with a symbol clock or an inverted symbol clock alternately for each unit using four taps.

In the case of symbol intervals, each of the data delay unit and the coefficient calculating unit delays I-channel or Q-channel data by one symbol in synchronization with the symbol clock, and performs coefficient update.

The VSB / QAM dual-purpose channel equalizer according to the present invention, when the channel equalizer is used as a symbol interval channel equalizer, delays input I channel or Q channel data in synchronization with a symbol clock, and converts the signal into an M fine interval channel equalizer. N data delays which, when used, delay the I channel or Q channel data in synchronization with the symbol clock M times faster; N decimators for extracting and outputting only data of a symbol position among data delayed and output from the N data delay units; The I-channel or Q-channel data output from each decimator is multiplied by an error value according to the time difference between the input I-channel or Q-channel symbol intervals, and added to the multiplication result and the tap coefficient of the previous I or Q channel data fed back to the symbol. N coefficient calculators delayed by a clock and outputted; A coefficient output unit for adding all of the tap coefficients of the N I or Q channel data updated and output by the N coefficient calculating units, respectively; An I channel signal output unit which slices an output of the coefficient output unit and estimates an I channel error value from a difference between a pre-slice signal and a subsequent signal; And a Q channel signal output unit configured to slice the output of the coefficient output unit and estimate a Q channel error value from a difference between a pre-slice signal and a subsequent signal.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention controls signal flow so that one channel equalizer is a symbol spacing real channel equalizer for VSB, a fine spacing real channel equalizer for VSB, a symbol spacing complex channel equalizer for VSB, a fine spacing complex channel equalizer for VSB, and QAM A symbol interval complex channel equalizer and a QAM fine interval complex channel equalizer are operated in one of the embodiments. In particular, the first embodiment operates each circuit element at a symbol frequency even when operating as a fine interval channel equalizer. The second embodiment is to reduce the power of the receiver by placing a decimator at the output end of the equalizer in the data delay.

First embodiment

In the second embodiment of the present invention, a symbol clock having two phases different from each other is used without using a symbol clock (2X) even in fine interval equalization in order to reduce power usage. Such an overall timing diagram and signal flow are shown in FIGS. 9 to 11.

As can be seen from FIG. 9, two data for one symbol of FIG. 9B generated by 2X (Symbol clock) of FIG. 9A are respectively input to the input of the equalizer by two symbol clocks having different phases. That is, odd-numbered data includes data generated by the symbol clock of FIG. 9C, and even-numbered data contains data not generated by the not (Symbol clock) clock, that is, the inverted symbol clock of FIG. 9D.

However, in the present invention, since the tap must be used as a QAM channel equalizer, four taps form one complex tap at the time of QAM channel equalization so that data is alternately entered by four taps.

FIG. 10 is a signal flowchart when operating as a fine interval equalizer, and it can be seen that data is entered by a symbol clock and an inverted symbol clock alternately by four taps. That is, if the 4-tap channel equalization operates with the symbol clock, the next 4-tap channel equalization operates with the inverted symbol clock, and this process is repeated four taps alternately. This eliminates the need for a 2: 1 decimator in fine-space channel equalization.

11 is a signal flow diagram when operating as a symbol interval equalizer, where all tap channel equalizations operate as a symbol clock.

12 is a block diagram showing the overall configuration of a VSB / QAM dual-purpose channel equalizer according to the present invention, in which N data delays 102-1 to 102- output the I channel signal or the Q channel signal by one symbol delay. 4) N coefficient calculating units 103-1 to 103-4 for performing coefficient updating by using each output of the data delay units 102-1 to 102-4 and the error values Ierror and Qerror of the I and Q channels. ), An error value Ierror of an I channel is estimated and output by using the adder 105 and the output of the adder 105, which add up all of the outputs of the coefficient calculating units 103-1 to 103-4. I channel signal output unit 106 for outputting channel signal Ioutput and Q channel signal output for estimating and outputting an error value Qerror of the Q channel using the output of the adder 105 and outputting an equalized Q channel signal Qoutput. It is comprised including the part 107. 12 includes a DFE 104 that receives Ierror, Qerror, a sliced I channel signal, and a sliced Q channel signal to cancel the influence of distant ghosts.

In this case, the mux 201 in the data delay unit 102-2 selects an I channel signal Idata or a Q channel signal Qdata and outputs it to the flip-flop 202, and the flip-flop 202 is the mux 201. ) Output is delayed by 1 symbol.                     

Incidentally, the aforementioned data delays 102-3 and 102-4 also have the same configuration as the data delays 102-3 described above.

At this time, when the multi-purpose channel equalizer is used as a complex channel equalizer, the mux 401 of the data delay 102-1 and the data delay 102-4 outputs the I channel signal Idata, and the data delay 102 The muxes 201 and 301 of -2,102-3 selectively output the Q channel signal Qdata.

In the meantime, the MUX 501 selects an Ierror or Qerror signal and outputs it to the multiplier 502. The multiplier 502 outputs an I-channel delayed by one symbol in the data delay 102-1. The signal is multiplied by the signal output through the mux 501 and output to the adder 503.

The adder 503 adds the output of the multiplier 502 and the previous filter coefficient fed back to the adder 504. The adder 504 multiplies the Q channel signal by the I error value (Qdata * Ierror) and the output of the adder 503 and outputs the result to the mux 505. The mux 505 selects the output of the adder 503 when the channel equalizer is used for VSB, and selects the output of the adder 504 when the channel equalizer is used for VSB and outputs it to the flip-flop 506. The flip-flop 506 delays the output of the mux 506 by one symbol and outputs the result to the multiplier 507 and the adder 503. The multiplier 507 multiplies the I-channel signal delayed by one symbol by the data delay 102-1 of the flip-flop 506 and outputs the multiplier 105 to the adder 105.

On the other hand, the mux 601 of the coefficient calculating unit 103-2 selects an Ierror or Qerror signal and outputs the result to the multiplier 602, and the multiplier 602 is output through the data delay unit 102-2. The I or Q channel signal is multiplied by the signal output through the mux 601 and output to the adder 603. At this time, if the Q channel error value Qerror is output from the mux 601, the Q channel signal Qdata is output from the data delayer 102-1, and the output of the multiplier 602 is Qdata * Qerror, the Qdata * Qerror signal is The adder 803 of the coefficient calculating unit 103-4 is output.

The adder 603 adds the output of the multiplier 602 and the filter coefficient of the current time fed back to the flip-flop 604. The flip-flop 604 delays the output of the adder 603 by one symbol and outputs the result to the mux 605. The mux 605 selects the output of the flip-flop 604 when the channel equalizer is used for VSB, and the output of the mux 506 of the previous coefficient calculating unit 102-1 when the channel equalizer is used for VSB. Is selected and output to the multiplier 606. The multiplier 606 multiplies the output of the MUX 605 by the I or Q channel signal output through the data delayer 102-2 and outputs the multiplier 105 to the adder 105.

The multiplier 701 of the coefficient calculator 103-3 multiplies the Ierror signal by the I or Q channel signal output through the data delayer 102-3 and outputs the multiplier 702 to the adder 702. In this case, if the Q channel signal Qdata is output from the data delayer 102-3 and the output of the multiplier 701 is Qdata * Ierror, the Qdata * Ierror signal is added to the adder 504 of the coefficient calculating unit 103-1. Is output.

The adder 702 adds the output of the multiplier 701 and the filter coefficient of the current time fed back to the flip-flop 703. The flip-flop 703 delays the output of the adder 702 by one symbol and outputs the result to the mux 704 and the adder 702. The mux 704 selects the output of the flip-flop 703 when the channel equalizer is used for VSB, and the flip-flop 805 of the coefficient calculating unit 102-4 of the next stage when the channel equalizer is used for the VSB. ) Is output to the multiplier 705.

The multiplier 705 multiplies the output of the MUX 704 by the I or Q channel signal output through the data delay 102-3 and outputs the multiplier 105 to the adder 105.

The multiplier 801 of the coefficient calculating unit 103-4 multiplies the Ierror signal by the I or Q channel signal output through the data delay unit 103-4 and outputs the multiplier 802 to the adder 802.

The adder 802 adds the output of the multiplier 801 and the filter coefficient of the current time fed back to the adder 803. The adder 803 adds the Qdata * Qerror signal output from the multiplier 602 of the coefficient calculator 103-2 and the output of the adder 802 to output to the mux 804. The mux 804 selects the output of the adder 802 when the channel equalizer is used for VSB, and selects the output of the adder 803 when the channel equalizer is used for VSB and outputs it to the flip-flop 805. The flip-flop 805 delays the output of the mux 804 by one symbol and outputs the result to the multiplier 806, the adder 802, and the mux 704 of the coefficient calculating unit 103-3. The multiplier 806 multiplies the output of the flip-flop 805 by the I or Q channel signal output through the data delayer 102-4 and outputs the multiplier 105 to the adder 105.                     

The adder 105 adds both the outputs of the coefficient calculators 103-1 to 103-4 and the outputs of the DFE unit 104 to add the I channel signal output unit 106 and the Q channel signal output unit 107. Will output

The I channel signal output unit 106 receives an output of the adder 105 and obtains and slices an input / output signal difference between the slicer 106-1 and the slicer 106-1 and outputs the difference as an I channel error value Ierror. It consists of the adder 106-2. In other words, the output of the adder 105 becomes the final I channel signal Ioutput with channel equalization. The slicer 106-1 determines the signal output from the adder 105 as the signal level closest to the distance, outputs the signal to the adder 106-2, and simultaneously outputs the signal to the DFE unit 104. For example, the slicer 106-1 selects a value closest to the output of the adder 105 from eight values if the transmission scheme is 8 VSB, and outputs the adder 105 from 256 values if the QQ is 256 QAM. Select the value closest to. The adder 106-2 obtains the difference between the input / output signals of the slice and outputs the error value Ierror of the I channel. In this case, a multiplier 106-3 may be connected to an output terminal of the adder 106-2 to multiply the output of the adder 106-2 by a step size μ.

The Q channel signal output section 107 also has the same structure as the above-described I channel output section 106, and its role is also the same. However, the Q channel signal output section 107 operates only when the channel equalizer is used for the QAM. That is, even when the channel equalizer is used as a complex channel equalizer for VSB, the Q channel signal output section 107 does not operate. This is because the Q-channel signal of the VSB transmission method is only a signal obtained by Hilbert transforming the I-channel signal.

13 to 15 show the VSB / QAM combined channel equalizer of FIG. 12, the symbol spacing real channel equalizer for VSB, the fine spacing real channel equalizer for VSB, the symbol spacing complex channel equalizer for VSB, and the fine spacing complex channel for VSB. Each signal flow diagram when using either an equalizer, a symbol interval complex channel equalizer for QAM, or a fine interval complex channel equalizer for QAM is shown.

1) VSB Real Channel Equalizer

Figure 13 shows a signal flow diagram when the multi-purpose channel equalizer according to the present invention is used as a symbol interval or fine interval real channel equalizer for VSB. In this case, the signals used are indicated by bold lines, and the signals not used are indicated by dotted lines.

That is, when the multi-purpose channel equalizer is used as a symbol interval or fine interval real channel equalizer for VSB, the output equation of the channel equalizer and the update coefficient of the filter coefficient are the same as in Equation 3 above, Same as

Where y (n) is the channel equalizer output,

        x (n) is the input data,

        c (n) is the channel equalizer coefficient at the current time,                     

        c (n + 1) is the channel equalizer coefficient of the next time, that is, the updated filter coefficient,

        e (n) is the error value,

        μ is the step size.

As shown in Fig. 13, the flip-flops of the respective data delayers 102-1 through 102-4 output an I-channel signal delayed by one symbol. The first multipliers of the coefficient calculating units 103-1 to 103-4 multiply the Ierror signal by the I-channel signals output from the data delayers 102-1 to 102-4, and output them to the next stage adder.

For example, referring to the first coefficient calculator 103-1, the I channel error value Ierror output through the mux 501 is multiplied by the I channel signal in the multiplier 502 and output to the adder 503. The adder 503 adds the output signal Ierror * Idata of the multiplier 502 and the current filter coefficient fed back, and this added signal is output to the flip-flop 506 through the mux 505 and delayed by one symbol. The signal delayed by one symbol in the flip-flop 506, that is, the filter coefficient, is output to the multiplier 507 and fed back to the adder 503. This operation is similarly performed in the coefficient calculating units 102-2 to 102-4.

In this case, when the channel equalizer operates as a fine interval real channel equalizer, the channel equalizer alternately receives a symbol clock and an inverted symbol clock by four taps.

In the case of FIG. 13, for example, only four taps are shown. However, if there are no divisions but the number of taps is four or more taps, the data delay and counting units of the next four taps are operated when the data delay and counting units of the first four taps are operated as symbol clocks. Operates as an inverted symbol clock. This process is repeated every four taps. That is, the symbol spacing and the fine spacing real channel equalizer have the same signal flow in a block within four taps.

As a result, no 2: 1 decimator is needed since the 2X (symbol clock) is not used even for fine interval channel equalization.

2) VSB Complex Channel Equalizer

Fig. 14 shows a signal flow diagram when the multi-purpose channel equalizer according to the present invention is used as a symbol interval or fine interval complex channel equalizer for VSB. In this case, the signals used are indicated by bold lines, and the signals not used are indicated by dotted lines.

The operation of the data delay when the multi-purpose channel equalizer is used as a symbol interval or fine interval complex channel equalizer for VSB is similar to that of the data delay of FIG. 13 described above, except that the data delays 102-2 and 102-3 are different. ) Selects Q channel data instead of I channel data and outputs it with 1 symbol delay. At this time, the data delay units 102-1 and 102-4 receive an I channel signal and delay one symbol.

Therefore, when the multi-purpose channel equalizer is used as a symbol interval or fine interval complex channel equalizer for VSB, the output equation of the channel equalizer and the update of the filter coefficients are as follows.                     

Where y _I (n) is the channel equalizer output,

x _I (n) is the input real data,

x _Q (n) is the input imaginary data,

c _I (n) is the real channel equalizer coefficient at the current time,

c _Q n) is the imaginary channel equalizer coefficient of the current time,

        c (n + 1) is the channel equalizer coefficient of

e _I (n) is the real error value,

        μ is the step size.

이 따로 필요없고, 오류값도 실수 오류값 즉, Ierror만이 사용되기 때문이다.
As can be seen from Equation 6, the complex update equation of the VSB case and the QAM case is different. The reason is that both are channel equalizers defined on the complex plane, but the Q channel output of the VSB is only Hilbert transformed, not data independent of the I channel.

This is not necessary, and the error value is a real error value, that is, only Ierror is used.

3) QAM Complex Channel Equalizer                     

Figure 15 shows a signal flow diagram when the multi-purpose channel equalizer according to the present invention is used as a symbol interval or fine interval complex channel equalizer for QAM. In this case, the signals used are indicated by bold lines, and the signals not used are indicated by dotted lines. In the case of FIG. 15, Ierror and Qerror signals are obtained through the I channel signal output unit 106 and the Q channel signal output unit 107.

Accordingly, when the multi-purpose channel equalizer is used as a symbol interval or fine interval complex channel equalizer for QAM, the output equation of the channel equalizer and the update of the filter coefficients are as follows.

Where y (n) is the channel equalizer output,

x _I (n) is the input real data,

x _Q (n) is the input imaginary data,

c _I (n) is the real channel equalizer coefficient at the current time,

c _Q n) is the imaginary channel equalizer coefficient of the current time,

        c (n + 1) is the channel equalizer coefficient of

e _I (n) is the real error value,

e _Q (n) is the imaginary error value,

        μ is the step size.

At this time, the data delay units 102-1 and 102-4 delay the input I channel data Idata by one symbol, and the data delay units 102-2 and 102-3 output the delayed Q channel data Qdata by one symbol. do.

The multiplier 502 of the coefficient calculating unit 103-1 multiplies the Q channel error value Qerror by Idata output through the data delay unit 102-1 and outputs the multiplier 503 to the adder 503. The adder 503 adds the previous coefficient fed back from the flip-flop 506 and the output of the multiplier 502 to output to the adder 504. The adder 504 adds the Qdata * Ierror signal output from the coefficient calculating unit 103-3 and the output of the adder 503, delays one symbol through the mux 505 and the flip-flop 506, and adds a multiplier ( 507 is output to the adder 503 and the mux 605 of the coefficient calculating section 103-2. The multiplier 507 multiplies the output of the flip-flop 506 by Idata, which is delayed by one symbol from the data delayer 102-1, and outputs the multiplier 105 to the adder 105.

The multiplier 602 of the coefficient calculator 103-2 multiplies the Qdata output through the mux 201 and the flip-flop 202 of the data delayer 102-2 with the Q channel error value Qerror. Output to the adder 803 of -4). Also, the mux 605 multiplies the Q coefficient Qcoef output from the flip-flop 506 of the coefficient calculating unit 103-1 and the Qdata output from the mux 202 of the data delayer 102-2 to add an adder ( 105).                     

The multiplier 701 of the coefficient calculating unit 103-3 multiplies the Qdata outputted through the mux 301 and the flip-flop 302 of the data delay unit 102-3 with the I channel error value Ierror and counts the coefficient calculating unit 103. Output to the adder 503 of -1). In addition, the mux 704 multiplies the I coefficient Icoef output from the flip-flop 805 of the coefficient calculating unit 103-4 and the Qdata output from the mux 302 of the data delayer 102-3 to add an adder ( 105).

The multiplier 801 of the coefficient calculating unit 103-4 multiplies the I channel error value Ierror by the mux 401 of the data delayer 102-4 and the Idata output through the flip-flop 402 to add the adder 802. Will output The adder 802 adds the previous coefficient fed back from the flip-flop 805 and the output of the multiplier 801 to output to the adder 803. The adder 803 adds the Qdata * Qerror signal output from the coefficient calculating unit 103-2 and the output of the adder 802, and delays one symbol through a mux 804 and a flip-flop 805 to multiply the multiplier ( 806, the adder 802, and the mux 704 of the coefficient calculating section 103-3. The multiplier 806 multiplies the output of the flip-flop 805 by Idata, which is delayed by one symbol from the data delayer 102-4, and outputs the result to the adder 105.

The adder 105 adds all the outputs of the coefficient calculators 103-1 to 103-4 and the DFE 104, and then slices 106 of the I channel signal output unit 106 and the Q channel signal output unit 107. -1,107-1) respectively.

The slicer 106-1 of the I channel signal output unit 106 determines the signal output from the adder 105 as the signal level closest to the distance and outputs the determination result to the adder 106-2. At the same time, it outputs to the DFE unit 104. The adder 106-2 subtracts the output of the slicer 106-1 from the output of the adder 105 to obtain an error value Ierror of the I channel. The I channel error value Ierror is multiplied by the step size μ in the multiplier 106-3.

The Q channel signal output unit 107 has the same operation as the I channel signal output unit 106 except for outputting the channel equalized Q signal Qoutput and the Q channel error value Qerror.

Second embodiment

The present invention places a 2: 1 decimator at the output end of the equalizer just behind the data delay to reduce receiver power.

16 has a structure similar to that of the channel equalizer of FIG. The difference is that the decimators 108-1 through 108-4 are connected to the output terminals of the respective data delays 102-1 through 102-4. In this case, when the channel equalizer is used as a symbol interval channel equalizer, data delayed by one symbol in the data delay units 102-1 through 102-4 are bypassed by the decimators 108-1 through 108-4. The multipliers of the coefficient calculating units 103-1 to 103-4 are output.

On the other hand, when the channel equalizer is used as a finely spaced channel equalizer, the data delayed by one symbol in the data delay units 102-1 through 102-4 is obtained by the symbol positions in the decimators 108-1 through 108-4. Only data is selected and output to the multipliers of the coefficient calculating units 103-1 to 103-4. Thus, when the channel equalizer is used as an N (e.g., N = 2) fine spacing channel equalizer, only the data delays 102-1 to 102-4 operate at twice the symbol clock, and the remaining blocks are symbols. Operate with a clock.

In other words, the difference between the symbol interval channel equalizer and the fine interval channel equalizer is that the data delays 102-1 to 102-4 operate at twice the symbol clock when used as the fine interval channel equalizer. In a typical finely spaced channel equalizer (see eg, Figures 4, 6 and 8), every block in front of the 2: 1 decimator at the end of the equalizer output operates at twice the symbol clock. Therefore, a lot of power is consumed and the hardware is complicated.

However, referring to the structure of FIG. 4 (the same applies to FIGS. 6 and 8), the output of the equalizer generated twice every symbol clock is used by only one of the two outputs by a 2: 1 decimator. In addition, it can be seen that the generated error value is generated only once every symbol clock.

Therefore, it can be seen that, as in the second embodiment of the present invention, placing the 2: 1 decimator immediately after the data delay units 102-1 to 102-4 has no effect on the output.

By doing so, all the blocks except the data delayers 102-1 through 102-4, where the channel equalizer acts as a fine interval channel equalizer, operate at a symbol clock, resulting in a much smaller amount than the conventional fine interval channel equalizer. Will use power.

1) VSB symbol spacing and fine spacing real channel equalizers

17 is a signal flow diagram when the multipurpose channel equalizer according to the present invention is used as a symbol spacing real channel equalizer for VSB, and FIG. 18 is a signal flow diagram when the multipurpose channel equalizer according to the present invention is used as a fine spacing real channel equalizer for VSB. to be. In this case, signals used are indicated by a thick line, and signals not used are indicated by a dotted line.

When the multi-purpose channel equalizer is used as a symbol interval or fine interval real channel equalizer for VSB, the output equation of the channel equalizer and the update of the filter coefficients are as shown in Equation 5 above.

That is, when the channel equalizer is used as a symbol interval channel equalizer, the flip-flops of the data delayers 102-2 to 102-4 output an I signal delayed by one symbol in synchronization with the symbol clock as shown in FIG. At this time, the one-signal delayed I-channel signal bypasses decimators 108-1 through 108-4. That is, the one-channel delayed I channel signal is directly output to each coefficient calculating section 103-1 to 103-4.

In the case where the channel equalizer is used as an N (N = 2) fine interval channel equalizer, as shown in FIG. 18, the flip-flops of the data delayers 102-2 to 102-4 are synchronized with the symbol clock twice as fast. Output a symbol delayed I signal. At this time, the one-channel delayed I-channel signal is extracted from the decimators 108-1 to 108-4, and only the data of the symbol positions are output to the coefficient calculating units 103-1 to 103-4.

The coefficient calculating units 103-1 to 103-4 have the same signal flow when used as fine-space real channel equalizers and when used as fine-space real channel equalizers, and each flip-flop operates in synchronization with a symbol clock.                     

That is, the first multipliers of the coefficient calculating units 103-1 to 103-4 are outputted from the Ierror signal and each of the data delay units 102-1 to 102-4 or the decimators 108-1 to 108-4. Multiply the channel signal and output it to the next stage adder.

2) 1) VSB symbol spacing and fine spacing complex channel equalizers

19 is a signal flow diagram when the multipurpose channel equalizer according to the present invention is used as a symbol interval complex channel equalizer for VSB, and FIG. 20 is a signal flow diagram when the multipurpose channel equalizer according to the present invention is used as a fine interval complex channel equalizer for VSB. to be. In this case, the signals used are indicated by bold lines, and the signals not used are indicated by dotted lines.

The operation of the data delay when the versatile channel equalizer is used as a symbol spacing or fine spacing complex channel equalizer for VSB is similar to the operation of the data delay of FIGS. 17 and 18 described above. 2, 102-3) selects Q channel data instead of I channel data and outputs one symbol delay. At this time, the data delay units 102-1 and 102-4 receive the I channel signal and delay one symbol.

In addition, the difference between when the multi-purpose channel equalizer is used as a symbol interval complex channel equalizer for VSB and when it is used as a fine interval complex channel equalizer is different from the data delay unit 102-1 to 102- when the channel equalizer is used as a fine interval complex channel equalizer. 4) operates in synchronization with the symbol clock twice as fast.

That is, when the channel equalizer is used as a symbol interval complex channel equalizer for VSB, the I channel signal delayed by one symbol in synchronization with the symbol clock as shown in FIG. 19 bypasses the decimators 108-1 through 108-4. It is immediately output to each coefficient calculating section 103-1 to 103-4.

When the channel equalizer is used as an N (N = 2) finely spaced channel equalizer, an I signal delayed by one symbol in synchronization with a symbol clock twice as fast as shown in FIG. 20 is transmitted from the decimators 108-1 to 108-4. Only the data of the symbol position is extracted and then output to the coefficient calculating units 103-1 to 103-4.

In this case, when the multi-purpose channel equalizer is used as a symbol interval or fine interval complex channel equalizer for VSB, the output equation of the channel equalizer and the update of the filter coefficients are as shown in Equation 6 above.

이 따로 필요없고, 오류값도 실수 오류값 즉, Ierror만이 사용되기 때문이다.
As can be seen, the complex update expression is different in the VSB and QAM cases. The reason is that both are channel equalizers defined on the complex plane, but the Q channel output of the VSB is only Hilbert transformed, not data independent of the I channel.

This is not necessary, and the error value is a real error value, that is, only Ierror is used.

3) QAM Complex Channel Equalizer

21 is a signal flow diagram when the multi-purpose channel equalizer according to the present invention is used as a symbol interval complex channel equalizer for QAM, and FIG. 22 is a signal flow diagram when the multi-purpose channel equalizer according to the present invention is used as a QAM fine interval complex channel equalizer. Is showing. In this case, the signals used are indicated by bold lines, and the signals not used are indicated by dotted lines. 21 and 22, the Ierror and Qerror signals are obtained through the I channel signal output section 106 and the Q channel signal output section 107.

When the multipurpose channel equalizer is used as a symbol interval or fine interval complex channel equalizer for QAM, the output equation of the channel equalizer and the update of the filter coefficients are as shown in Equation (7).

In this case as well, when the multi-purpose channel equalizer is used as a symbol interval complex channel equalizer for QAM, the flip-flops of the data delayers 102-1 to 102-4 operate in synchronization with the symbol clock as shown in FIG. However, when the multi-purpose channel equalizer is used as a fine interval complex channel equalizer for QAM, the flip-flops of the data delayers 102-1 to 102-4 operate in synchronization with the symbol clock twice as fast as shown in FIG.

At this time, the data delay units 102-1 and 102-4 delay and output the I channel data Idata inputted in synchronization with the symbol clock or the symbol clock twice as fast, and the data delay units 102-2 and 102-3 output the symbols. The Q-channel data Qdata inputted in synchronization with a clock or twice as fast as a symbol clock is delayed by one symbol and output.

And a coefficient calculating section 103-1 to 103-4, an adder 105, an I channel signal output section 106, and a Q channel when the channel equalizer operates as a QAM symbol interval or fine interval complex channel equalizer. Since the operation of the signal output unit 107 is the same as that of the QAM complex channel equalizer of the first embodiment described above, detailed description thereof will be omitted.

 As described above, according to the QAM / VSB multi-purpose channel equalizer according to the present invention, when equalizing a received signal, the received signal is a VSB signal, a QAM signal, and whether the equalization interval is a symbol interval, a fine interval, or a real channel equalization. By generating the corresponding filter coefficients according to whether they are complex channel equalization and controlling the flow of the signal in each case, real or complex channel equalization of the VSB and QAM signals with a single equalizer is performed at symbol interval or fine interval. can do. Therefore, the hardware area for implementing the channel equalizer can be greatly reduced.

In addition, even when operating as a fine interval channel equalizer, each circuit element is operated at a symbol frequency or an inverted symbol frequency, thereby omitting a decimation process of extracting only data at a symbol position, thereby reducing power of a receiver. In addition, the power of the receiver can be reduced by placing the decimator at the output end of the equalizer in the data delay and then operating the data delay twice as fast as the symbol clock only when operating as a fine interval channel equalizer.

And, by supporting all the methods of the conventional LMS equalizer can be very useful in the chip development stage.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (7)

In the channel equalizer for channel equalizing the I channel data and the Q channel data input by the VSB transmission method or QAM transmission method at a symbol interval or a fine interval smaller than the symbol interval, N data delayers for delaying the input I channel data or the Q channel data by one symbol according to a symbol clock or an inverted symbol clock and outputting the same; After multiplying the error value according to the time difference between the I channel or Q channel data output from the data delay unit and the I channel or Q channel symbol interval, and adding the tap coefficient of the previous I or Q channel data fed back to the multiplication result, the symbol N coefficient calculation units outputting a delay of one symbol according to a clock or an inverted symbol clock; A coefficient output unit for adding all of the tap coefficients of the N I or Q channel data updated and output by the N coefficient calculating units, respectively; After slicing the output of the coefficient output unit, an I channel error value is estimated from a difference between a pre-slice signal and a subsequent signal, and decimation extracts only data of a symbol position even when the channel equalizer is used as a fine interval channel equalizer. I-channel signal output unit not to; And After slicing the output of the coefficient output unit, the Q channel error value is estimated from the difference between the signal before and after the slice, and the decimation extracts only the data at the symbol position even when the channel equalizer is used as a fine interval channel equalizer. VSB / QAM dual-purpose channel equalizer characterized in that it comprises a Q-channel signal output unit that does not. The method of claim 1, When the channel equalizer is used as a fine interval channel equalizer, the data delay unit and the coefficient calculating unit The I-channel or Q-channel data input in the odd-numbered (or even-numbered) is delayed by one symbol in synchronization with the symbol clock to perform coefficient update, and the I-channel or Q-channel data input in the even-numbered (or odd-numbered) Is a VSB / QAM dual-purpose channel equalizer characterized by performing a coefficient update after delaying one symbol in synchronization with an inverted symbol clock. The method of claim 1, wherein the data delay unit and the coefficient calculation unit When the channel equalizer is used as a finely spaced channel equalizer, VSB / QAM dual-purpose channel equalizer characterized in that the four taps as a unit, and operates in synchronization with the symbol clock or the inverted symbol clock alternately for each unit. The coefficient calculating unit of claim 3, wherein the coefficient calculating unit comprises four taps as one unit. A multiplier for multiplying an error value according to a time difference between input I channel or Q channel data and input I channel or Q channel symbol interval, A first adder for adding the tap coefficients of previous I or Q channel data fed back with the output of the multiplier; A second adder which, when used for QAM, adds the multiplication result of the Q channel data and the I channel error value or the multiplication result of the Q channel data and the Q channel error value and the output of the first adder; A first delayer for delaying the output of the first adder or the second adder by one symbol in synchronization with a symbol clock or an inverted symbol clock; And a multiplier for multiplying the I channel data or the Q channel data output through the data delay unit and outputting the multiplier to the coefficient output unit. The coefficient calculating unit of claim 4, wherein the coefficient calculating unit of the second and third taps comprises four taps as a unit. A multiplier for multiplying an error value according to a time difference between input I channel or Q channel data and input I channel or Q channel symbol interval, and outputting the multiplier to the second adder of the coefficient calculating unit of the first or fourth tap; A third adder for adding the tap coefficients of previous I or Q channel data fed back with the output of the multiplier; A second delay unit for delaying the output of the third adder by one symbol in synchronization with a symbol clock or an inverted symbol clock; Select to output the output of the second delay if the channel equalizer is used for VSB, and output the output of the first delay of the coefficient operator of the first or fourth tap if used for QAM. Wealth, And a multiplier for multiplying the I channel data or the Q channel data output through the data delay unit and outputting the coefficient output unit to the coefficient output unit. The method of claim 1, wherein each of the data delay unit and the coefficient calculating unit In the case of the symbol interval, VSB / QAM dual-purpose channel equalizer characterized in that the coefficient update is performed after delaying the I channel or Q channel data by one symbol in synchronization with the symbol clock. In the channel equalizer for channel equalizing the I channel data and Q channel data input by VSB transmission method or QAM transmission method at symbol interval or M fine interval, When the channel equalizer is used as a symbol interval channel equalizer, the input I channel or Q channel data is delayed in synchronization with a symbol clock. When the channel equalizer is used as an M fine channel equalizer, the I channel or Q channel data is M. N data delays for delaying in synchronization with the symbol clock twice as fast; N decimators for extracting and outputting only data of a symbol position among data delayed and output from the N data delay units; The I-channel or Q-channel data output from each decimator is multiplied by an error value according to the time difference between the input I-channel or Q-channel symbol interval, and added to the multiplying tap coefficients of the previous I or Q channel data fed back to the multiplication result. N coefficient calculators delayed by a clock and outputted; A coefficient output unit for adding all of the tap coefficients of the N I or Q channel data updated and output by the N coefficient calculating units, respectively; An I channel signal output unit which slices an output of the coefficient output unit and estimates an I channel error value from a difference between a pre-slice signal and a subsequent signal; And And a Q channel signal output unit for estimating a Q channel error value from a difference between a pre-slice signal and a subsequent signal after slicing an output of the coefficient output unit.

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