KR100729423B1 - 622Mbps level Packet over SDH equipment with ATM interworking function - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a 622 megabytes PS packet over SD processing apparatus having an asynchronous transfer mode interworking function.

2. The technical problem to be solved by the invention

The present invention is a system of a structure using an ATM cell switch routing system that can be easily applied to a high-capacity system environment by being able to utilize a high-speed ATM switch structure with ATM quality of service (QoS) and bandwidth management functions. To provide a 622Mbps packet over SDH processing unit with ATM interworking function suitable for the network.

3. Summary of Solution to Invention

The present invention provides an optical transmission / reception means for optically interfacing with the outside through a single mode optical fiber; Clock / data recovery means for reproducing a clock from the optical reception data received by the optical transmission / reception means and recovering data corresponding to the clock; Performs the line termination function, the path termination function, and the data engine function with the data transmitted from the clock / data recovery means, attaches a Point-to-Point Protocol (PPP) header, and generates a high level data link control (HDLC) frame. Packet over SDH (Synchronous Digital Hierarchy) for loading on the Synchronous Transfer Module-4 (STM-4) Paylord, generating path overhead and line overhead, and then optically transmitting to the outside through the optical transmission / reception means ) Framing means; Segmentation / combining means for segmenting Internet Protocol (IP) packet data into an Asynchronous Transfer Mode (ATM) cell form and reassembling the ATM cell into IP packet data; ATM layer processing means for attaching a routing tag or removing a routing tag to the ATM cell received from the partitioning / combining means to connect with the ATM switch; And interfacing means for interfacing to interwork with an ATM switch.

4. Important uses of the invention

The present invention is used for IP delivery system and the like.

Asynchronous delivery mode, packet over SDH, POS, STM-4

Description

622 Megabyte PS packet over SDH processing unit with asynchronous transfer mode interworking function {622Mbps level Packet over SDH equipment with ATM interworking function}             

1 is a configuration diagram of an embodiment of a 622Mbps packet over SDH device having an ATM interworking function according to the present invention.

FIG. 2 is a diagram illustrating an embodiment of loading a PPP / HDLC frame onto an SDH STM-4 frame according to the present invention. FIG.

3 is a diagram illustrating an embodiment of an AAS process of a 622 Mbps packet-over SDH device having an ATM interworking function according to the present invention;

4 is a diagram illustrating an embodiment of a POS interface data format structure of FIG. 3 and a data format structure between AAS and ALP4;

5 is an embodiment flow diagram for a process of creating a CPCS-PDU according to the present invention;

6 is a diagram illustrating an embodiment of the CPCS-PDU data format structure.

7 is an exemplary view of the timing between AAS and ALP4 in accordance with the present invention.

8 is an exemplary diagram for timing between an SDH POS Framer and an AAS according to the present invention.                 

* Explanation of symbols for the main parts of the drawings

100: Optical Transceiver 200: CDR

300: SDH POS Framer 400: AAS

410: RxLANCAM 420: SRAM

430: TxLANCAM 500: ALP4

510, 520: SRAM 600: SFI

700: LCPI

The present invention relates to a 622 Mbps packet over SDH processing device having an asynchronous transfer mode (ATM) and interworking functions, and a 622 Mbps class (STM-4 level) packet over SDH (POS) device having an ATM interworking function. Compared to the existing IP over ATM (IPoA) over SDH based network, ATM overhead is reduced by 18-25%, and the SDH transmission base widely used in the network can be utilized. The present invention relates to a 622Mbps packet over SDH processing device having an ATM interworking function suitable for a structure using an ATM cell switch that is not based on IP as a routing method that can provide excellent scalability and reliability by using protection switching capability.

The technical field of the present invention is a technology recently utilized in routers as an IP transmission technology field.

In other words, the Internet backbone network is built on the existing SDH transport network using the Point-to-Point Protocol (PPP) / High Level Data Link Control (HDLC) protocol between the Internet Protocol (IP) layer and the Synchronous Digital Hierarchy (SDH) transport layer. When configuring router-to-router IP only, POS (Packet Over SDH) is mainly used as IP basic by using existing SDH transmission network 155Mbps and 622Mbps link.

However, in the POS, IP packets are transmitted using the PPP / HDLC protocol over SDH, so that only the best-effort IP service can be provided, and there is no quality of service (QoS) and bandwidth management. There is a problem that the forwarding engine function is not separated and is not suitable for a large capacity high speed router environment.

The present invention has been proposed to solve the problems described above, and can be easily applied to a high-capacity system environment by being able to utilize a high-speed ATM switch structure with an ATM level of QoS and bandwidth management. It is an object of the present invention to provide a 622Mbps packet over SDH processing apparatus having an ATM interworking function suitable for a system using an ATM cell switch for routing.

An apparatus of the present invention for achieving the above object is, 622Mbps class packet over SDH processing apparatus having an asynchronous transfer mode (ATM) interworking function, comprising: optical transmission / reception means for optical interface with the outside via a single mode optical fiber; Clock / data recovery means for reproducing a clock from the optical reception data received by the optical transmission / reception means and recovering data corresponding to the clock; Performs the line termination function, the path termination function, and the data engine function with the data transmitted from the clock / data recovery means, attaches a Point-to-Point Protocol (PPP) header, and generates a high level data link control (HDLC) frame. Packet over SDH (Synchronous Digital Hierarchy) for loading on the Synchronous Transfer Module-4 (STM-4) Paylord, generating path overhead and line overhead, and then optically transmitting to the outside through the optical transmission / reception means ) Framing means; Segmentation / combining means for segmenting Internet Protocol (IP) packet data into an Asynchronous Transfer Mode (ATM) cell form and reassembling the ATM cell into IP packet data; ATM layer processing means for attaching a routing tag or removing a routing tag to the ATM cell received from the partitioning / combining means to connect with the ATM switch; And interfacing means for interfacing to interwork with the ATM switch.

By inventing the 622Mbps packet over SDH processing unit with ATM interworking function suitable for the system using ATM cell switch as the routing method, it can utilize the high speed ATM switch structure with ATM quality of service (QoS) and bandwidth management function. It is characterized by consisting of a 622Mbps packet over SDH processing unit having an asynchronous transfer mode (ATM) interworking function to be easily applied to a high-capacity system environment.

The 622 Mbps STM-4 level packet over SDH (POS) device with ATM interworking function of the present invention reduces the ATM overhead compared to the existing IP over ATM (IPoA) over SDH based network. It has 25% bandwidth improvement, and also has the advantage of utilizing the SDH transmission base widely used in the current network and providing excellent scalability and reliability by using the protection switching capability of the ring.

An object of the present invention is to invent a 622Mbps packet over SDH processing apparatus having an ATM interworking function suitable for a structure using an ATM cell switch instead of IP based routing.

Therefore, by inventing a 622Mbps packet-over SDH processing device having an ATM interworking function suitable for a system using an ATM cell switch as a routing method, a high-speed ATM switch structure with ATM quality of service (QoS) and bandwidth management functions is provided. It can be easily applied to high-capacity system environment by making it available.

In addition, the present invention is an essential function in the system to use the core switch to ATM cell switch system and the system to apply the POS card while using the ATM core switch in a high capacity (more than gigabit) router. Therefore, the 622Mbps packet over SDH processing device having the ATM interworking function proposed in the present invention is applied to the interworking function between the ATM method of the switch and the IP method of the line side, and the packet over WDM technology The present invention can have application power.                     

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of an embodiment of a 622Mbps packet over SDH device having an ATM interworking function according to the present invention.

As shown in FIG. 1, a packet over SDH device according to the present invention has an external and optical interface function through a single mode fiber using a 622 mega optical optical transceiver 100. .

First, looking at the optical reception direction side, the CDR (Clock and Data Recovery) 200 regenerates a clock from the optical reception data, recovers data corresponding to the clock, and transmits the data to the SDH POS Framer 300. The SDH POS Framer 300 performs a line termination function, a path termination function, and a data engine function, and is connected to the AAS (ATM AAL5 SAR) 400 in a 16-bit parallel interface (Enhanced Utopia Mode). In the AAS 400, IP packet data is segmented into an ATM cell. The ATM layer processor STM-4 level (ALP4) 500 attaches a routing tag to the ATM cell received from the AAS 400 and connects to the ATM switch through the switch fabric interface (SFI) 600.

Next, in the optical transmission direction, the ATM cell received from the ATM switch passes through the Switch Fabric Interface (SFI) 600 to remove the routing tag from the ALP4 (ATM Layer Processor STM-4 Level) 500, and the ATM cell. It is connected to the AAS 400 in the form. ATM AAL5 SAR (AAS) 400 reassembles ATM cells to IP packet data, sends them to SDH POS Framer 300, attaches PPP headers, generates HDLC frames, and loads them into STM-4 payloads. After generating the overhead and the line overhead has a function to optically transmit to the outside through the 622M optical transceiver (100 optical transceiver) (100).

And, it has a Local Processor Processor (hereinafter referred to as "LCPI") 700 that can control each function.

2 is a diagram illustrating an embodiment of loading a PPP / HDLC frame onto an SDH STM-4 frame according to the present invention.

IP packets are controlled through Point-to-Point Point-to-Point Protocol (PPP) protocol, which accepts PPP packets in a structure similar to HDLC framing, encapsulates multi-protocol datagrams on point-to-point links, It has error checking and link initialization functions.

The PPP protocol architecture negotiates information about the Link Control Protocol (LCP) function, which establishes, releases, tests, and manages data links between connected systems, and protocols of various network layers such as IP, IPX, and DECnet as upper layers. There is also a Network Control Protocol (NCP) function to maintain these connections.

The principle of operation of PPP is to first send and receive link control protocol (LCP) frames to form a link control protocol (LCP) link, and the various communication options for the link control protocol (LCP) can be determined when establishing a connection. The system negotiates link parameters and the like. After the link control protocol (LCP) connection is established between the two systems, the network control protocol (NCP) frames are exchanged to exchange information about the network protocol to be used with each other. At this time, more than one network protocol can be set up on the same link and exchange IP address using IPCP (IP control protocol) subprotocol, and after connection is established, data from upper protocol (ie network protocol packet) Passed through the link.

HDLC frames contain data packets after address, control / protocol fields, 16 / 32-bit frame check sequence (FCS) protects the entire frame, and flag 7E indicates the end of the frame and the beginning of the next frame. Is used between frames.

Thus, the formed HDLC frame is mapped to the STM-4 VC-4c payload and transmitted.

3 is a diagram illustrating an embodiment of an AAS process of a 622Mbps packet-over SDH device having an ATM interworking function according to the present invention.

The AAS 400 is located in the middle of the SDH POS framer 300 shown in FIG. 1 and ALP4 500 which is an ATM layer processor, and is a destination address (DA) of an IP packet input from the SDH POS framer 300. To match the ATM's Virtual Path Identifier (VPI) / VCI (Virtual Channel Identifier) to convert IP packets to ATM AAL5 and vice versa.

The IP Header Processor 440 is connected to the SDH POS framer 300 via a 16-bit bus interface. The IP Header Processor 440 generates a 4-byte ATM header corresponding to an ATM destination address as an ATM address through the RxLANCAM interface 444. do.                     

The AAL5 Segmentation Processor 450 performs AAL5 CPCS generation and AAL5 segmentation 451, and attaches an ATM header received from the TxLANCAM interface 444 to form an ATM cell.

The ATM Layer interface 460 has a function of connecting to ALP4 via a 16-bit bus interface. In the reverse direction, the ATM Header Processor 470 is connected to the ALP4 via a 16-bit bus interface. The ATM header processor 470 matches the VPI / VCI values of the ATM cells input from the ALP4 interface with the SRAM address through the TxLANCAM interface 474 and outputs the SRAM address. It performs the function.

The AAL5 Reassembly Processor 480 collects the cells input from the ALP4 from the SRAM interface 483 into a complete IP packet.

POS interface 490 has a function of connecting to SDH POS Framer 300 via a 16-bit bus interface.

The POS interface 490 of the AAS 400 is connected to an enhanced UTOPIA 16-bit data bus interface and a timing diagram is shown in FIG. 8 below, and the data format structure of FIG. 4-A]. This will be described in more detail with reference to FIGS. 4 and 8.

Meanwhile, the IP Header Processor 440 is connected to the POS interface 490 through a 622 Mbps enhanced UTOPIA level 2 16-bit bus interface, and has a 16:32 conversion to connect the 16-bit bus to the 32-bit FIFO. Convert to a 32-bit bus via 441 and start reading the Rx1 FIFO 442 after the empty signal goes low via the Rx1 FIFO Control & POS interface 443.

After the SOP (Start of Packet) signal, the start signal of the packet, the first 4 bits of the first data are checked to check the IP version. If the version is not 4, the packet is discarded. The second data of the packet refers to the total length of the IP packet. The total packet length (TPL) value is stored in a 16-bit register, which is used when generating a Common Part Convergence Sublayer Protocol Data Unit (CPCS-PDU) and AAL5 segmentation.

After the start of packet (SOP), the 19th and 20th data means the destination address of the IP. First, it is stored in two 16-bit registers so that the RxLANCAM interface 444 can be used to match the VPI / VCI. The RxLANCAM interface 444 compares the input 32-bit IP destination address with 4 bytes of ATM header area (eg, Generic Flow Control (GFC), VPI / VCI, Payload Type (PT), and Cell Loss Priority) It is responsible for outputting the result. It takes about 9 clocks to enter the destination address and retrieve the matched VPI / VCI value from the RxLANCAM interface 444. The 4-byte ATM header containing the matched VPI / VCI is a 16-bit register. Once stored in four, they are used as ATM headers in AAL5 segmentation.

The RxLANCAM 410 receives an IP destination address (32 bits) and generates a 4-byte ATM header corresponding to the address. The CAM consists of 64 bits of memory width and uses the upper 32 bits as the comparison area and the lower 32 bits as the area where the comparison results are stored. The comparison result area is the VPI / VCI value corresponding to the IP address, 4-bit GFC (default '0000'), 3-bit PT area ('0' or '1'), and 1-bit CLP (default '0'). Consists of This is shown in [Table 1].

Meanwhile, the AAL5 segmentation processor 450 of FIG. 3 performs AAL5 CPCS generation and AAL5 segmentation in the AAL5 segmentation unit 451.

When the start of packet (SOP) starts, the cyclic redundancy check (CRC-32) calculation for the packet begins in the 32-bit CRC CAC unit 452 and the packet length stored in the 16-bit register in the IP header processor 440. The TPL value is calculated as a 2-byte word using a byte value of, and a CPCS-PDU is generated by an algorithm as shown in FIG. 5, and cell segmentation is performed at the same time. And, the data format of the CPCS-PDU is shown in FIG. This will be described in more detail with reference to FIGS. 5 and 6.

The AAL5 segmentation unit 451 divides the CPCS-PDU input from the AAL5 CPCS-PDU generator into units of 48 bytes and attaches the ATM head from the RxLANCAM 410. The ATM header is a six-byte ATM head with four bytes including GFC, VPI / VCI, PT, and CLP received from RxLANCAM 410, plus two bytes of headers including HEC (Header Error Control) and UDF (User Defined Field). Becomes After splitting the CPCS-PDU input, the ATM head is pasted, and when the last segmented packet arrives, the PT header of the ATM header is set to '001' to indicate that this cell is the last cell of one packet.

Meanwhile, the ATM Layer interface 460 is an interface for connecting to ALP4, which is connected to a UTOPIA level2 16-bit bus interface. It converts into a bus and is connected to the ALP4 through the control of the Tx1 FIFO Control & ALP4 interface 463 at the Tx1 FIFO 462. The data format with ALP4 is shown in [4-B] of FIG. 4 below, and the interface timing diagram is shown in [7-B] of FIG. 7 below.

The ATM Header Processor 470 is connected to the ALP4 and UTOPIA level2 16-bit bus interfaces, and the 16-bit bus is converted through a 16:32 conversion (471) to connect to the FIFO with a 32-bit bus. The Rx2 FIFO (472) It is connected to ALP4 via control of the Rx2 FIFO Control & ALP4 interface 473. The interface data format with ALP4 is UTOPIA LEVEL2 16-bit 27 word structure. [4-B] in FIG. 4 and timing diagram are as shown in [7-A] in FIG.

When a cell arrives at the FIFO, it reads the ATM cell header (3 words-6 bytes). Read the VPI / VCI and Payload Type Identifier (PTI) area from the ATM cell header, and store the VPI / VCI in the upper 32-bit comparison area of the TxLANCAM 430. Read the PTI area and read the PTI area. It is determined whether it is ") or the last cell (" 001 ").                     

The TxLANCAM interface 474 matches the VPI / VCI value of the ATM cell inputted from the ALP4 interface with the address of the SRAM and outputs an SRAM address. The upper 32 bits of the 64-bit CAM area are used as the 24-bit VPI / VCI area as the comparison area, and the remaining 8 bits are left empty. The lower 32-bit comparison result area is filled with the SRAM address area. This is shown in [Table 2].

The memory area of the SRAM 430 connected to the AAL5 Reassembly Processor 480 is divided into a connection memory (CM) area and a data memory (DM) area. And this is shown in the following [Table 3].

The start address of the CM region corresponding to the VPI / VCI connection is obtained from the SRAM 420 address read from the TxLANCAM 420, and the connection information is read. The DMSA (Data Memory Start Address) and CA (Current Address) of the DM area corresponding to the VPI / VCI are found from the connection information. The payload of the ATM cell is sequentially stored in the DM area of the SRAM 420. At the same time, the CRC-32 of the packet stored in the DM is calculated, stored in the CM area, and the CA of the CM area is updated. If the PT (Payload Type) area is recognized as "001", first, the FIFO controller sets the availability to "High" so that ALP4 no longer transmits the cell. At this time, if stored in the SRAM 420 in the higher order and read sequentially from the DMSA to the CA, one CPCS-PDU is completed, and when the reading of the packet is completed, the ALP4 is set to enable the cell availability. Try cell transmission.

Upon receiving one CPCS-PDU from the SRAM interface 483, first check the CRC-32 in the 32-bit CRC CAC Unit 482 for the CPCS-PDU to confirm that the packet has been received normally, and then It reads the packet total length part and counts it as much as the packet length and stores it in TxFIFO. The SRAM interface 483 collects cells input from ALP4 to form one complete IP packet.

The POS interface 490 is connected to the Enhanced UTOPIA level2 16-bit bus interface, which converts the 32-bit bus via 32:16 conversion (491) to connect to the FIFO as a 16-bit bus, and 16-bit. A wide Tx2 FIFO 492 is connected to the SDH POS Framer 300 through the Tx2 FIFO Control & POS Interface 493 control. An interface timing diagram with the SDH POS Framer 300 is shown in FIG. 8.

FIG. 4 is a diagram illustrating an embodiment of a POS interface data format structure of FIG. 3 and a data format structure between AAS and ALP4.

[4-A] of FIG. 4 is the POS interface data format structure of FIG. 3, where "IP version" indicates an IP version and supports only version 4 (IPV4).

"Header Length" indicates the length of the packet header including the Option Pad, "Type of Service" indicates the type of service, and "Total Packet Length" indicates the total IP packet length. And, "Header Checksum" is used to determine the error of IP head.

[4-B] of FIG. 4 is a data format structure between the AAS 400 and the ALP4 500, and includes 27 words in total.

5 is a flowchart illustrating an embodiment of a process for creating a CPCS-PDU according to the present invention.

As shown in FIG. 5, it is determined whether the TPL is greater than or equal to '40' by receiving a total packet length (TPL) as an input.

As a result of the check, if the value is not '40' or more, the value obtained by subtracting the TPL + 8 value from '48' in the PAD is performed, and the final cell segment processing is performed.

As a result of the check, if it is' 40 'or more, the TPL is once again checked to be' 48 'or more, and if' 48 'or more, the cell segment processing is performed, subtracting' 48 'from the TPL, and the TPL is' Proceed to check if it is over 40 '.

If the TPL is not '48' or more, the TPL is set to '0', and the PAD1 enters a '48 -TPL 'value and performs a Last1 Cell Segment Processing procedure.

6 is a diagram illustrating an embodiment of the CPCS-PDU data format structure.

In the figure, " CPCS-UU " of an 8-byte CPCS-PDU TRAILER is a CPCS User-to-User Indication and occupies one byte (" 00000000 ").

"CPI" is a common part indicator and occupies one byte ("00000000"). The length is 2 bytes as TPL, and the CRC is CRC-32 of CPCS-PDU and 4-byte CPCS TRAILER.                     

7 is an exemplary diagram for timing between AAS and ALP4 according to the present invention.

[7-A] of FIG. 7 shows a transmission side timing diagram between AAS and ALP4, and [7-B] shows a reception side timing diagram, respectively.

8 is an exemplary diagram for timing between an SDH POS Framer and an AAS according to the present invention.

[8-A] of FIG. 8 shows a transmission side timing diagram between the SDH POS Framer and the AAS, and [8-B] shows a reception side timing diagram, respectively.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention shows a tendency to use a core switch as an ATM cell switch method in a high-capacity (terra-class or higher) router as part of IP over fiber technology. It is an essential function in the system that intends to apply POS (Pocket Over SDH) technology to line cards using ATM core switch. Therefore, the 622Mbps packet over SDH processing apparatus with ATM interworking function is applied to the interworking function between the ATM method of the switch and the IP method of the line side, and the present invention is also applicable to the packet over WDM technology. There is an effect that can have.

Claims (4)

In the 622Mbps packet over SDH processing device having an asynchronous transfer mode (ATM) interworking function, Optical transmission / reception means for optical interfacing with the outside via single-mode optical fibers; Clock / data recovery means for reproducing a clock from the optical reception data received by the optical transmission / reception means and recovering data corresponding to the clock; Performs the line termination function, the path termination function, and the data engine function with the data transmitted from the clock / data recovery means, attaches a Point-to-Point Protocol (PPP) header, and generates a high level data link control (HDLC) frame. Packet over SDH (Synchronous Digital Hierarchy) for loading on the Synchronous Transfer Module-4 (STM-4) Paylord, generating path overhead and line overhead, and then optically transmitting to the outside through the optical transmission / reception means ) Framing means; Segmentation / combining means for segmenting Internet Protocol (IP) packet data into an Asynchronous Transfer Mode (ATM) cell form and reassembling the ATM cell into IP packet data; ATM layer processing means for attaching a routing tag or removing a routing tag to the ATM cell received from the partitioning / combining means to connect with the ATM switch; And Interfacing means for interfacing to interwork with ATM switches Packet over SDH processing device comprising a. The method of claim 1, The dividing / combining means, Located between the SDH framing means and the ATM layer processing means, a destination address (DA) of an IP packet input from the SDH framing means is converted into a virtual path identifier (VPI) / VCI (Virtual Channel) of the ATM. Packet over SDH processing device, characterized in that the IP packet is converted / inverted into an ATM adaptation layer 5 (AAL5) form of an ATM by matching with an identifier. The method according to claim 1 or 2, The dividing / combining means, The 16-bit bus output from the SDH framing means is converted into a 32-bit bus to connect with FIFO (First In First Out), and the 32-bit wide data is read by a packet over SDH interface control signal. IP header processing means for; Cyclic Redundancy Check-32 (CRC-32) calculation is performed on the packet to generate Common Part Convergence Sublayer Protocol Data Unit (CPCS-PDU) data with the byte value of the packet length stored in the 16-bit register in the IP header processing means. Division processing means for performing cell segmentation; ATM layer interfacing means for interfacing the ALP4 (ATM Layer Processor STM-4 Level) data output from the partition processing means; ATM header processing means for reading a VPI / VCI and PTI area from an ATM cell header, storing the VPI / VCI in an upper 32-bit area of TxLANCAM, and confirming a start address of a static random access memory (SRAM); Receives one CPCS-PDU from an SRAM interface, performs CRC-32 calculation on the CPCS-PDU, checks whether a packet is normally received, and collects cells input from ALP4 into a complete IP packet. AAL5 recombination processing means for; And Enhanced UTOPIA level2 Connected via a 16-bit bus interface, converts the 32-bit bus via 32:16 conversion to access the FIFO with a 16-bit bus, and controls the Tx2 FIFO control in a 16-bit wide FIFO. POS interfacing means for connecting to the SDH framing means via POS interface control Packet over SDH processing device comprising a. The method of claim 3, wherein The TxLANCAM, Packet over SDH processing apparatus, characterized in that for outputting the SRAM address by matching the VPI / VCI value of the ATM cell input from the ALP4 interface and the SRAM address.

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