KR100729019B1 - Lead frame for semiconductor device and manufacturing methode thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device and a method for manufacturing the same, and a technical problem to be solved is to manufacture and supply a lead frame at low cost while having excellent material characteristics of the lead frame.

To this end, the gist of the solution method according to the present invention is an alloy base material consisting of iron (Fe) and chromium (Cr), a first plating layer which is plated with a predetermined thickness on at least one surface of the alloy base material to improve adhesion, and the first Disclosed is a lead frame for a semiconductor device comprising a second plating layer on a surface of a plating layer thicker than a thickness of the first plating layer, and simultaneously bonding a semiconductor die and a wire to allow a predetermined current to flow.

Leadframe, Alloy, Iron, Chrome, Plating Layer

Description

Lead frame for semiconductor device and manufacturing method thereof

1A is a cross-sectional view showing a lead frame for a semiconductor device according to the present invention, and FIG. 1B is a plan view showing an example of a lead frame stamped or etched.

2 is a flowchart illustrating a method of manufacturing a lead frame for a semiconductor device according to the present invention.

3A to 3D are explanatory views showing a method of manufacturing a lead frame for a semiconductor device according to the present invention.

4A illustrates a plating thickness measurement position in a lead frame for a semiconductor device according to the present invention. FIG. 4B is a photograph showing a peeling test result after forming a first plating layer, and FIG. 4C is a peeling test result after forming a second plating layer. It is a photograph showing.

5A and 5B are photographs showing a die-off test result after performing a die bonding process on a lead frame for a semiconductor device according to the present invention. FIGS. 5C and 5D show a wire pull test result after performing a wire bonding process. It is a photograph showing.

6A is a photograph after performing a forming process on a lead frame for a semiconductor device, and FIG. 6B is a photograph after performing a forming process on a lead frame for a semiconductor device according to the present invention.

7A to 7C are graphs comparing various characteristics of a semiconductor device using a lead frame according to the present invention and a semiconductor device using a conventional lead frame.

<Description of Symbols for Main Parts of Drawings>

100; Lead frame for semiconductor device according to the present invention

110; Alloy base material 112; Passivation oxide

120; First plating layer 130; 2nd plating layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device lead frame and a method for manufacturing the same, which are excellent in various material properties and can be manufactured at low cost.

In general, a lead frame for a semiconductor device is a continuous metal strip manufactured by a mechanical stamping or chemical etching method, the role of the lead connecting the semiconductor die and the external device. And, it refers to performing the role of the frame (frame) for fixing the semiconductor device to the external device at the same time.

These lead frames for semiconductor devices are largely copper based (copper: iron: phosphorus = 99.8: 0.01: 0.025), copper alloy series (copper: chromium: tin: zinc = 99: 0.25: 0.25: 0.22), and alloy 42 series. (Iron: nickel = 58:42), and the like. Here, the copper series is mainly used for leadframes with a thickness of 0.15 mm or more, the copper alloy series and the alloy 42 series are mainly used for leadframes of 0.1 to 0.15 mm, and the alloy 42 series is mainly used for leads of about 0.1 mm. Used for frames. However, the metal series is not absolutely determined by the thickness of the lead frame, and a suitable metal series is determined as the lead frame according to various material properties.

Meanwhile, in a semiconductor device using such a lead frame, the lead frame accounts for approximately 30 to 60% of the cost. Moreover, the lead frame made of the alloy 42, which is mainly used for semiconductor devices in recent years, is extremely expensive, and it is no exaggeration to say that it occupies most of the cost of the semiconductor device. Here, the material for the cost of the semiconductor device is mainly an epoxy molding compound, gold wire and the like in addition to the lead frame.

Therefore, in recent years, many researches and developments have been conducted to find new materials for leadframes by changing the expensive leadframe materials as described above, while reducing the cost share and various material properties being the same as or better than those of the prior art.

Although the number of metals currently used industrially is innumerable, not all of these metals can be used as leadframes. Therefore, in order for a metal to be used as a lead frame, certain conditions must be satisfied according to the requirements of the lead frame or the semiconductor device.

As described above, in order for a predetermined metal to be used as a lead frame, two conditions must be satisfied.

First, it must have good material properties suitable for leadframes. These material properties can be classified into four categories: mechanical, physical, electrical, and thermal properties. The mechanical properties include tensile strength, elongation, elastic modulus and hardness, electrical properties include electrical conductivity, thermal properties include thermal expansion coefficient, thermal conductivity and softening temperature, physical properties include specific gravity and lead Attachment is included. That is, in order for a metal to be used as a lead frame, all of the above 10 items or specifications must be satisfied.

Secondly, even if a given metal satisfies the above various material properties, it should not be more expensive than the price of a conventional lead frame (for example, Alloy 42). That is, the predetermined metal should be able to be manufactured and supplied at a significantly lower price than conventional leadframes. For example, when a lead frame of alloy 42 is used for a semiconductor device, the cost share of the lead frame of alloy 42 in the semiconductor device is considerably high, resulting in an increase in the cost of the semiconductor device itself. Therefore, in order to lower the price of the semiconductor device, it is necessary to be able to manufacture and supply a new lead frame at a price about 10 to 60% lower than that of the alloy 42, which has the largest cost ratio.

SUMMARY OF THE INVENTION The present invention has been made in view of the above conventional needs, and an object of the present invention is to provide a lead frame for a semiconductor device and a method of manufacturing the same, which are excellent in various material properties and can be manufactured and supplied at low cost.

In order to achieve the above object, a lead frame for a semiconductor device according to the present invention is an alloy base material consisting of iron (Fe) and chromium (Cr) and a first plated with a predetermined thickness on at least one surface of the alloy base material to improve adhesion. A plating layer and a surface of the first plating layer may include a second plating layer which is plated to a thickness thicker than the thickness of the first plating layer and simultaneously bonds a semiconductor die and a wire to allow a current to flow.

Here, the alloy base material is 80 to 84w% of iron, 13 to 18w% of chromium, 0.12 to 0.15w% of carbon (C), 0.8 to 1.0w% of silicon (Si), 0.8 to 1.2w of manganese (Mn) %, Phosphorus (P) may be made of 0.020 ~ 0.060w%, sulfur (S) 0.015 ~ 0.045w%, nickel (Ni) 0.1 ~ 0.7w%.

In addition, the alloy base material further includes nickel (Ni), wherein the iron is 65.5 ~ 72.0w%, the chromium is 18 ~ 20w%, the nickel is 8 ~ 12w% at the same time, the carbon (C) 0.06 ~ 0.1 w%, Silicon (Si) 0.8 ~ 1.0w%, Manganese (Mn) 1-3w%, Phosphorus (P) 0.020 ~ 0.060w%, Sulfur (S) 0.015 ~ 0.045w%, Nitrogen (N) 0.08 ~ 0.1w It may consist of%.

In addition, the alloy base material may have a thickness of 0.1 ~ 0.15mm.

In addition, the first plating layer may be made of nickel.

In addition, the first plating layer may have a thickness of about 0.2 μm to about 0.8 μm.

In addition, the second plating layer may be formed of any one selected from copper (Cu), silver (Ag), gold (Au), or palladium (Pd) / gold (Au).

In addition, the second plating layer may have a thickness of 3 μm to 6 μm.

In addition, the alloy base material has a tensile strength of 260 ~ 650 N / mm ² , elongation 10 ~ 35%, hardness 110 ~ 210Hv, electrical conductivity 3 ~ 92% IACS, coefficient of thermal expansion 4 ~ 21 (× 10 ^-6 ) K, thermal conductivity 12 It may be ~ 390W / Mk, specific gravity 7 ~ 9g / cm ³ .

In addition, the alloy base material may be made of a stainless steel series.

In addition, the alloy base material may be any one selected from stainless steel (SUS) 430, stainless steel (SUS) 410L, or stainless steel (SUS) 304.

In addition, when the NPN or the PNP transistor is mounted on the second plating layer, an Ic-hFE characteristic curve, an Ic-Vce (sat) characteristic curve, and a PT-Rtn characteristic curve are different from those when the alloy base material is alloy 42. Can match within ± 1% of range.

In addition, the method of manufacturing a lead frame for a semiconductor device according to the present invention in order to achieve the above object is an alloy base material preparing step of preparing an alloy base material consisting of iron (Fe) and chromium (Cr), and the alloy base material chemical solution Removing the passivation oxide film formed on the surface of the alloy base material by immersing it out after a predetermined time, and then immersing the alloy base material from which the passivation oxide was removed in the first plating solution and then taking it out. A first plating layer forming step of forming a first plating layer, and a second plating layer forming step of forming a second plating layer having a predetermined thickness by immersing the alloy base material on which the first plating layer is formed after being immersed in a second plating solution. can do.

Here, the alloy base material preparing step may be such that the thickness of the alloy base material is 0.1 ~ 0.15mm.

In addition, the alloy base material preparing step may be made of the alloy base material further comprises nickel (Ni).

In the forming of the first plating layer, the thickness of the first plating layer may be 0.2 to 0.8 μm.

In addition, in the forming of the first plating layer, the first plating layer may be formed of nickel.

In addition, the second plating layer forming step may be such that the thickness of the second plating layer is 3 ~ 6㎛.

In addition, the forming of the second plating layer may allow the second plating layer to be formed of any one selected from copper (Cu), silver (Ag), gold (Au), or palladium (Pd) / gold (Au).

In addition, the alloy base material preparation step may be such that the alloy base material is a stainless steel series.

In addition, the passivation oxide removal step may be made by immersing the alloy base material in hydrochloric acid (HCl) solution of 35 ~ 45vol% concentration at room temperature for 5 to 10 minutes.

In addition, the first plating layer forming step is immersing the alloy base material in a plating solution consisting of a mixture of HCl 125g / l solution and NiCl ₂ · 6H ₂ O 240g / l solution at room temperature, the cathode current density is 5 ~ 10A / dm ² , The voltage is 6V, the anode can be made by performing for 20 to 120 seconds under the conditions of nickel plate and carbon plate.

In the forming of the second plating layer, the alloy base material on which the first plating layer is formed is immersed in a plating solution formed by mixing H ₂ SO ₄ 45-80 g / l solution and CuSO ₄ 150-250 g / l solution at room temperature, and the cathode The current density is 1 ~ 8A / dm ² , the anode current density is 0.5 ~ 5A / dm ² , the anode is made of copper plated, chlorine ion concentration can be made by performing for 10 minutes to 30 minutes under the conditions of 20 ~ 120ppm.

As described above, the lead frame according to the present invention is similar to or better than the conventional lead frame, for example, Alloy 42, that is, mechanical properties (tensile strength, elongation, modulus of elasticity and hardness) and physical properties (specific gravity). And lead tackiness).

Further, the lead frame according to the present invention has an effect of having better electrical characteristics (electric conductivity) and thermal characteristics (thermal conductivity) than the conventional lead frame of alloy 42, for example. That is, the lead frame according to the present invention increases not only the response speed of the semiconductor die but also the generation of Joule heat due to the improvement of the electrical characteristics (electric conductivity), thereby increasing the thermal efficiency. Of course, this reduces the thermal degradation of the semiconductor die, thereby enabling the mounting of high power devices. In addition, due to the improvement of the thermal characteristics (thermal conductivity), the lead frame according to the present invention releases Joule heat generated during operation of the semiconductor die to the outside as quickly as possible, thereby minimizing the performance degradation of the semiconductor die.

Moreover, the lead frame according to the present invention can be purchased and manufactured at a price of almost 50% or less cheaper than the lead frame of the conventional alloy 42, for example. Therefore, by lowering the price of the lead frame, which occupies the most cost among semiconductor devices, to almost half or less, there is an economic effect that the price of the overall semiconductor device can be considerably lowered.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.

1A, there is shown a cross-sectional view of a leadframe for a semiconductor device in accordance with the present invention, and with reference to FIG. 1B an example of a stamped or etched leadframe is shown as a plan view.

As shown in FIG. 1A, a lead frame 100 for a semiconductor device according to an exemplary embodiment of the present invention includes an alloy base material 110 having a predetermined thickness and a first plating layer 120 having a predetermined thickness on at least one surface of the alloy base material 110. And a second plating layer 130 formed on a surface of the first plating layer 120 to have a predetermined thickness.

As shown in FIG. 1B, the stamped or etched leadframe 100 may include a frame 171 for maintaining a predetermined shape, and a die paddle connected to the frame 171 and bonded with a semiconductor die during a semiconductor device manufacturing process. 172 and a lead 173 connected to the frame 171 and simultaneously bonded with a wire during a semiconductor device manufacturing process. However, the present invention is not limited to the shape of the lead frame shown in FIG. 1B, and it is obvious that the lead frame according to the present invention may be manufactured in any form.

The alloy base material 110 may be made of iron (Fe) and chromium (Cr). Here, the alloy base material 110 may be 80 ~ 84w% of iron, 13 ~ 18w% of chromium. When the chromium is 13w% or less, the corrosion resistance and high temperature hardness of the leadframe 100 are poor, and when the chromium is 18w% or more, the mechanical, electrical, thermal, and physical properties of the leadframe 100 are generally Can be lowered.

In addition, the alloy base material 110 has carbon (C) 0.12 ~ 0.15w%, silicon (Si) 0.8 ~ 1.0w%, manganese (Mn) 0.8 ~ 1.2w%, phosphorus (P) 0.020 ~ 0.060w% and sulfur (S) 0.015 ~ 0.045w%, nickel (Ni) may be further included 0.1 ~ 0.7w%. As is well known, the greater the amount of carbon, the better the hardenability, but the lower the corrosion resistance. Therefore, the smaller the alloy base material 110, the better. In addition, the higher the amount of silicon, the higher the strength, but this is because the silicon contained in the ore is formed by melting the iron when iron is extracted from the iron ore, the smaller this is better. The larger the amount of manganese, the better the hardness and high temperature strength, but the smaller the better. The phosphorus and sulfur are originally impurities which should not be present in iron, but are inevitably added during the smelting process for removing manganese, and the smaller the smaller the better.

In addition, the alloy base material 110 may be made of iron, chromium and nickel. At this time, the alloy base material 110 may include iron 65.5 ~ 72.0w%, chromium 18 ~ 20w% and nickel 8 ~ 12w%. Here, when the chromium is 18 w% or less, or the nickel is 8 w% or less, corrosion resistance and high temperature hardness deteriorate. In addition, when the chromium is 20w% or more, or the nickel is 12w% or more, the mechanical, electrical, thermal, and physical properties of the leadframe 100 may be generally reduced. In addition, the alloy base material 110 has carbon (C) 0.06 ~ 0.10w%, silicon (Si) 0.8 ~ 1.0w%, manganese (Mn) 1 ~ 3w%, phosphorus (P) 0.020 ~ 0.060w% and sulfur ( S) 0.015 to 0.045w% and nitrogen (N) 0.08 to 0.1w% may be further added.

In addition, the alloy base material 110 may use stainless steel (SUS), which is commonly distributed in the market. For example, austenitic SUS303, SUS304, SUS305, SUS316, SUS321, ferritic SUS405, SUS410L, SUS430, SUS434, and martensitic SUS403, SUS410L, SUS416, SUS420, and SUS440 can be used as the alloy base material 110. In particular, the stainless steel ferritic SUS430 made of a ratio of approximately 82w% and 18w% of iron and chromium may be used as the alloy base material 110 of the present invention. In addition, the ferritic SUS410L is also made of a ratio of about 88w% and 12w% of iron and chromium may be used as the alloy base material 110 of the present invention. Of course, the stainless steel austenitic stainless steel SUS304 is composed of approximately 74w%, 18w% and 8w% of iron, chromium and nickel may be used as another alloy base material 110.

In addition, the alloy base material 110 is preferably such that the thickness is about 0.1 ~ 0.15mm to satisfy the thickness required by most of the lead frame 100 or the semiconductor device. That is, when the thickness of the alloy base material 110 is 0.1mm or less or 0.15mm or more, it is not good because a problem occurs in workability during the stamping process of the lead frame 100.

The first plating layer 120 is formed on at least one surface of the alloy base material 110 to have a predetermined thickness. Since the adhesion between the second plating layer 130 to be described below and the alloy base material 110 is not good, the first plating layer 120 is formed for improving adhesion. The first plating layer 120 may use nickel having excellent adhesion to the alloy base material 110 and the second plating layer 130 to be described below. In addition, the thickness of the first plating layer 120 may be formed about 0.2 ~ 0.8㎛. When the thickness of the first plating layer 120 is 0.2 μm or less, the adhesion to the second plating layer 130 is inferior, and when the thickness of the first plating layer 120 is 0.8 μm or more, high adhesion despite securing sufficient adhesion strength Phosphorus nickel is too good to be used.

The second plating layer 130 is formed on the surface of the first plating layer 120 to have a predetermined thickness. Since the second plating layer 130 is a region in which a predetermined current flows through the semiconductor die and the wire, etc., copper (Cu), silver (Ag), gold (Au), and palladium / gold (Pd / Au) having excellent electrical conductivity are excellent. ) Or any one thereof, or an alloy thereof.

  In addition, the thickness of the second plating layer 130 may be formed to about 3 ~ 6㎛. If the thickness of the second plating layer 130 is 3 μm or less, current efficiency is not very good. If the thickness of the second plating layer 130 is 6 μm or more, expensive copper or silver may be too high despite sufficient current efficiency. Not used much

On the other hand, the physical properties of the lead frame 100 as described above and the physical properties of the alloy material of the conventional alloy 42 or copper-based is as follows.

Here, since the thickest part of the lead frame 100 is the alloy base material 110, various physical properties in Table 1 below may be regarded as physical properties of the alloy base material 110. In addition, in Table 1 below, Alloy 42 is a material of the lead frame 100 that is typically used in the prior art, the present invention 1 is the case of the alloy base material 110 is made of iron and chromium, the present invention 2 is an alloy It shows that the base material 110 is made of iron, nickel and chromium. Further, the first, second and third comparative examples are mainly copper-based alloy series used in low cost semiconductor devices.

"Selection criteria" described in Table 1 above shows the conditions of the lead frame 100 that is typically used. The selection criteria are at least 500 for tensile strength, at least 10 for elongation, at least 180 for hardness, at least 30 for electrical conductivity, near 4.3 for thermal expansion coefficient, near 12 for thermal conductivity, near 8 for specific gravity, In the case of material costs, it is required to be 200 or less. It is understood that the alloy base material 110 is made of iron and chromium (Invention 1), as shown in Table 1, which satisfies all these conditions most ideally. Of course, it is also possible that the alloy base material 110 is made of iron, nickel and chromium (the present invention 2).

The alloy base material 110 will be described in more detail with an example of iron and chromium.

In the tensile strength, which is one of the mechanical properties, both Alloy 42 and the present invention satisfy the criteria of 500 or more. In addition, in the elongation which is one of mechanical characteristics, although the alloy 42 is 8, this invention is 22, and this invention satisfy | fills 10 or more selection criteria. In addition, in alloy hardness, which is one of mechanical properties, both Alloy 42 and the present invention satisfy the criteria of 180 or more.

On the other hand, in the electrical conductivity which is one of the electrical characteristics, the alloy 42 does not satisfy the selection criterion 30 as 3, but the present invention satisfies the selection criterion 30 as 30. Of course, it can be seen that the electrical properties of the semiconductor die can be improved due to such electrical conductivity.

In addition, although the present invention has an inferior value in comparison with the alloy 42 in the thermal expansion coefficient, which is one of the thermal characteristics, it is not necessary to worry about the problem occurrence in the semiconductor device as the size of the semiconductor die becomes smaller. In addition, although the alloy 42 and the present invention both satisfy the selection criteria of 12 or more in thermal conductivity, which is one of the thermal characteristics, the present invention has a significantly larger 26.1 than the alloy 42. It can be seen that the joule heat can be discharged to the outside quickly.

Finally, in the material cost, alloy 42 is 469, but the present invention is 163. When using the lead frame 100 according to the present invention, it can be seen that the material cost can be reduced to almost 50% or less.

For reference, in bold type in Table 1 shows a value that does not meet the selection criteria according to the present invention, which means that the material having any one of these values is inappropriate as the lead frame (100).

Next, the manufacturing method of the lead frame 100 for semiconductor devices by this invention is demonstrated.

Referring to FIG. 2, a method of manufacturing a lead frame 100 for a semiconductor device according to the present invention is illustrated by a flow chart. Referring to FIGS. 3A to 3D, the lead frame 100 for a semiconductor device according to the present invention is illustrated. The manufacturing method of is shown by way of illustration.

As shown in the drawing, the method for manufacturing a lead frame 100 for a semiconductor device according to the present invention includes an alloy base material preparing step S1, a passivation oxide removing step S2, a first plating layer forming step S3, It includes a two plating layer forming step (S4).

In the alloy base material preparing step (S1), an alloy base material 110 made of iron (Fe) and chromium (Cr) is prepared. The alloy base material 110 is to have a thickness of 0.1 ~ 0.15mm as described above. In addition, the alloy base material 110 may further include nickel in addition to iron, chromium. In addition, the alloy base material 110 may use stainless steel. Since the type, composition ratio, and the like of the alloy base material 110 are all described above, further description thereof will be omitted here (see FIG. 3A).

Subsequently, in the passivation oxide removal step S2, the thin passivation oxide film 112 formed on the surface of the alloy base material 110 is removed using a predetermined chemical solution. That is, a passivation oxide film 112 of about 20-40 nm, which is known to be formed of Cr ₂ O ₃ , is formed on the surface of the alloy base material 110, and is removed using a predetermined chemical solution. . The reason why the passivation oxide layer 112 is removed is that the die bonding or the wire bonding process is impossible during the semiconductor device manufacturing process (see FIG. 3B). For example, the passivation oxide layer 112 may be formed of the alloy. The base material 110 may be removed by immersing the hydrochloric acid (HCl) solution in a concentration of 35 to 45 vol% for about 5 to 10 minutes at room temperature.

Subsequently, in the first plating layer forming step (S3), the alloy base material 110 from which the passivation oxide film has been removed is immersed in the first plating solution for a predetermined time, and then taken out, so that the first plating layer 120 having a predetermined thickness is made of the alloy base material. It is formed on at least one surface of (110) (see Figure 3c). For example, the first plating layer 120 may be formed of nickel having excellent adhesion. In addition, the thickness of the first plating layer 120 is to be 0.2 ~ 0.8㎛. In addition, the first plating layer 120 may use a nickel strike plating method that can obtain a relatively uniform thickness among various methods of nickel plating. Table 2 below lists the chemical solution, temperature, cathode current density, voltage, time, and anode conditions for nickel strike plating.

Subsequently, in the second plating layer forming step S4, the second plating layer 130 having a predetermined thickness is formed on the first plating layer 120. For example, the second plating layer 130 may be formed of any one selected from copper, silver, or an equivalent thereof or an alloy having excellent electrical conductivity. In addition, the thickness of the second plating layer 130 is to be approximately 3 ~ 6㎛ (see Figure 3d). In addition, the second plating layer 130 has less pollution, less cost and smoothness of the various methods of copper plating. This excellent copper sulfate plating method is used. The copper sulfate plating method has a lower coating power than the alkaline (copper cyanide) plating method. However, since the first plating layer 120 is first formed of nickel as described above, this disadvantage is solved. Table 3 below lists various chemical solutions for copper sulfate plating, temperature, cathode current density, anode current density, anode and time, and the like.

Hereinafter, as described above, the alloy base material 110 is substantially stainless steel (SUS), and the first plating layer 120 is formed on the surface of the alloy by the nickel strike plating method, and the second plating layer 120 is formed on the first plating layer 120 by the copper sulfate plating method. Various test results of the lead frame 100 on which the plating layer 130 is formed will be described.

First, the evaluation method and the result about plating thickness are demonstrated.

As shown in Figure 4a, the evaluation of the plating thickness was carried out a total of nine places each of the three parts, three points at both ends and the center at approximately 50cm intervals, the results are summarized in Table 4 below.

As shown in Table 4 above, the first plating layer 120 and the second plating layer 130 formed on the alloy base material 110 can be confirmed that both the appearance and the plating thickness are satisfactory.

Next, the peeling evaluation method and result are demonstrated.

Table 5 sequentially describes the peeling evaluation method for determining whether the first plating layer 120 and the second plating layer 130 are properly formed.

Meanwhile, referring to FIG. 4B, the result of peeling evaluation (plating adhesion evaluation) after the first plating layer 120 is formed in the lead frame for the semiconductor device according to the present invention is shown in a photograph. Referring to FIG. 4C, the second plating layer The results of peeling evaluation after formation of 130 are shown in the photograph. In the drawing, reference numeral 122 denotes a mark in which the first plating layer 120 is cut by a knife, and reference numeral 132 denotes a mark in which the second plating layer 130 is cut by a knife.

As shown in FIG. 4B and FIG. 4C, since the peeled state of the first plating layer 120 or the second plating layer 130 was hardly found, all of the peeling evaluation results were observed to be good.

Then, the stamping fairness evaluation method and result are demonstrated.

Stamping fairness evaluation is an item that depends on the mechanical properties such as tensile strength, hardness and modulus of the material. As a result of stamping on the leadframe 100 of the present invention, it was observed that all of the basic characteristics of the conventional leadframe were satisfied.

Table 6 below lists the dimensions and appearance inspection results after stamping.

Next, the bonding fairness evaluation and the result will be described.

5A and 5B are photographs illustrating die off test results after a die bonding process is performed on a lead frame 100 for a semiconductor device according to the present invention. FIGS. 5C and 5D illustrate a wire bonding process. Photo shows full test results. Here, the photograph of FIG. 5A has a semiconductor die size of 0.29 × 0.29 mm ^2, and the photograph of FIG. 5B has a semiconductor die size of 0.65 × 0.65 mm ² .

Bonding processability evaluation is related to the plating properties and workability of the material for the weldability and QC (Quality Control) item of the lead frame 100. In the case of die bonding, the fracture location was found to be bulky. The residual amount of silicon after breaking was 70% or more. In FIG. 5A and FIG. 5B, reference numeral 140 'denotes a residual amount of silicon.

In addition, in the case of wire pull, the breaking shape was C-mode (breaking about the middle part of the wire loop rather than the ball bonding area or the wedge bonding area of the wire, meaning that the wire bonding was the strongest) and the breaking strength Was approximately 5 g or more, satisfying the level required for a conventional semiconductor device. In addition, chip popping, which was expected to occur when the size of the semiconductor die was large, did not occur. In FIG. 5C and FIG. 5D, reference numeral 140 is a semiconductor die and 150 is a wire.

Next, molding fairness evaluation and a result are demonstrated.

The main evaluation items during the evaluation of molding fairness are lead press and bleed / flash. Lead pressing causes lead pressing when the thermal expansion coefficient difference is large. When the bleed / flash is low in the alloy material and the plating thickness, the resin or filler component of the epoxy molding compound is excessively leaked out of the mold after the mold operation. In the lead frame 100 according to the present invention, such lead pressing and bleed / flash states were observed at the same level as before.

Next, forming processability evaluation and a result are demonstrated.

Forming is an item related to mechanical properties such as tensile strength, hardness, elasticity, and elongation of the lead frame. When the tensile strength of the lead frame 100 is less than or equal to the standard specification, the breakage of the lead may occur during forming. It must be maintained. In the case of hardness, when the hardness is less than the reference specification, the shape abnormality (depression, etc.) of the lead frame may occur during forming, and when the hardness is higher than the reference specification, cracking may occur. If the elastic modulus is too high, it is difficult to return to the original state or maintain the desired shape without maintaining a constant shape even after the forming process. If the elongation is lower than the reference specification, lead breakage occurs. The lead frame 100 according to the present invention satisfies all these standard specifications, and the forming results also satisfied all the forming specifications. Table 7 summarizes these results, and a side view of the semiconductor device using the lead frame according to Figs. 6A (Prior Art) and 6B (Invention) is shown, respectively. In the figure, reference numeral 160 denotes an epoxy molding compound.

Finally, the results of the electrical and thermal characteristics evaluation are described.

As a result of evaluating the electrical and thermal characteristics evaluation results, the entire level of the electrical characteristics compared to the lead frame 100 made of the conventional alloy 42 exhibited the same or higher level characteristics. It is judged that no electrical deterioration occurs because the electrical conductivity of the alloy base material 110 used in the present invention as described above is slightly better than that of the conventional alloy 42. In addition, the excellent Pdmax (maximum power consumption of the product at the ambient temperature Ta of approximately 25 ° C.) is believed to be due to the higher thermal conductivity than the conventional alloy 42. In the thermal characteristics, it is determined that the lead frame 100 according to the present invention is equivalent to or superior to the lead frame 100 of the conventional alloy 42. Table 8 below compares the electrical characteristics of the semiconductor device using the lead frame of the conventional alloy 42 and the semiconductor device using the lead frame according to the present invention. In addition, Table 9 below compares the thermal characteristics of the semiconductor device using the lead frame of the conventional alloy 42 and the semiconductor device using the lead frame according to the present invention.

Here, the abbreviation which shows the characteristic in Table 8 is demonstrated briefly as follows.

 VFBE: Base-Emitter Forward Voltage

BVCEO: Base Open Collector-Emitter Breakdown Voltage

BVCBO: Emitter Open Collector-Base Breakdown Voltage

BVEB: Collector Open Emitter-Base Breakdown Voltage

ICBO: Emitter Open Collector-Base Current

IEB: Collector Open Emitter-Base Current

HFE: Defined as output current (IC) / input current (IB), and amplification degree of transistor.

VECsat: Collector-emitter voltage, base current IB and collector current IC typically have VCE values at IC / IB = 10

VBEsat: Saturation voltage between base and emitter

VFBC: Forward voltage between base and collector

ICER: Collector-Emitter Reverse Current

 7A to 7C, graphs comparing various characteristics of a semiconductor device using a lead frame for a semiconductor device according to the present invention and a semiconductor device using a conventional lead frame are shown.

Here, in the lead frame 100 according to the present invention, for example, after the NPN or PNP transistor is mounted on the second plating layer 130, a predetermined region of the transistor and the lead frame 100 is bonded with wires to form a semiconductor device. Can be.

As in the Ic-hFE characteristic curve shown in FIG. 7A, the Ic-Vce (sat) characteristic curve shown in FIG. 7B, and the PT-Rtn characteristic curve shown in FIG. 7C, the semiconductor device using the leadframe 100 according to the present invention. And the semiconductor device using the lead frame 100 of the conventional alloy 42 can be confirmed that all the characteristics match within the error range ± 1%. Here, PT is an abbreviation of Power Duration Time, and means power duration applied to measure Rth (thermal resistance). In addition, Rtn is an abbreviation of Routine and means "currently applied."

As described above, the lead frame according to the present invention is similar to or better than the conventional lead frame, for example, Alloy 42, that is, mechanical properties (tensile strength, elongation, modulus of elasticity and hardness) and physical properties (specific gravity). And lead tackiness).

Further, the lead frame according to the present invention has an effect of having better electrical characteristics (electric conductivity) and thermal characteristics (thermal conductivity) than the conventional lead frame of alloy 42, for example. That is, the lead frame according to the present invention increases not only the response speed of the semiconductor die but also the generation of joule heat due to the improvement of the electrical characteristics (electric conductivity), thereby increasing the thermal efficiency. Of course, this reduces the thermal degradation of the semiconductor die, thereby enabling the mounting of high power devices. In addition, due to the improvement of the thermal characteristics (thermal conductivity), the lead frame according to the present invention releases Joule heat generated during operation of the semiconductor die to the outside as quickly as possible, thereby minimizing the performance degradation of the semiconductor die.

Moreover, the lead frame according to the present invention can be purchased at a price of almost 50% or more lower than, for example, a conventional lead frame of alloy 42. Therefore, by lowering the price of the lead frame, which occupies the most cost among the semiconductor devices, to almost half or less, there is an economic effect that the price of the overall semiconductor device can be considerably lowered.

What has been described above is only one embodiment for implementing the lead frame for a semiconductor device and a method of manufacturing the same according to the present invention, and the present invention is not limited to the above-described embodiment, and is claimed in the following claims. As described above, any person having ordinary knowledge in the field of the present invention without departing from the gist of the present invention will have the technical spirit of the present invention to the extent that various modifications can be made.

Claims (23)

delete An alloy base material composed of iron (Fe) and chromium (Cr), a first plating layer coated on at least one surface of the alloy base material with a predetermined thickness to improve adhesion, and a thickness of the first plating layer on a surface of the first plating layer. A second plating layer which is plated to a thicker thickness and at the same time a semiconductor die and a wire are bonded to allow a predetermined current to flow; The alloy base material is 80-84w% of iron, 13-18w% of chromium, 0.12-0.15w% of carbon (C), 0.8-1.0w% of silicon (Si), 0.8-1.2w% of manganese (Mn), Phosphorus (P) 0.020 to 0.060 w%, sulfur (S) 0.015 to 0.045 w% and nickel (Ni) 0.1 to 0.7 w%, The alloy base material has a tensile strength of 260 ~ 650 N / mm ² , elongation 10 ~ 35%, hardness 110 ~ 210Hv, electrical conductivity 3 ~ 92% IACS, coefficient of thermal expansion 4 ~ 21 (× 10 ^-6 ) K, thermal conductivity 12 ~ 390W Lead frame for semiconductor devices, characterized in that / Mk, specific gravity 7 ~ 9g / cm ³ . An alloy base material composed of iron (Fe) and chromium (Cr), a first plating layer coated on at least one surface of the alloy base material with a predetermined thickness to improve adhesion, and a thickness of the first plating layer on a surface of the first plating layer. A second plating layer which is plated to a thicker thickness and at the same time a semiconductor die and a wire are bonded to allow a predetermined current to flow; The alloy base material further includes nickel (Ni), wherein the iron is 65.5-72.0w%, the chromium is 18-20w%, the nickel is 8-12%, and the carbon (C) 0.06 ~ 0.10w% , Silicon (Si) 0.8 ~ 1.0w%, manganese (Mn) 1-3w%, phosphorus (P) 0.020 ~ 0.060w%, sulfur (S) 0.015 ~ 0.045w% and nitrogen (N) 0.08 ~ 0.10w% At the same time, The alloy base material has a tensile strength of 260 ~ 650 N / mm ² , elongation 10 ~ 35%, hardness 110 ~ 210Hv, electrical conductivity 3 ~ 92% IACS, coefficient of thermal expansion 4 ~ 21 (× 10 ^-6 ) K, thermal conductivity 12 ~ 390W Lead frame for semiconductor devices, characterized in that / Mk, specific gravity 7 ~ 9g / cm ³ . The lead frame for a semiconductor device according to claim 2 or 3, wherein the alloy base material has a thickness of 0.1 to 0.15 mm. 4. The leadframe for semiconductor device according to claim 2 or 3, wherein the first plating layer is made of nickel. 4. The lead frame for semiconductor device according to claim 2 or 3, wherein the first plating layer has a thickness of 0.2 to 0.8 mu m. The semiconductor device according to claim 2 or 3, wherein the second plating layer is formed of any one selected from copper (Cu), silver (Ag), gold (Au) or palladium (Pd) / gold (Au). Leadframe. 4. The lead frame for semiconductor device according to claim 2 or 3, wherein the second plating layer has a thickness of 3 to 6 mu m. delete delete delete According to claim 2 or 3, when the NPN or PNP transistor is mounted on the second plating layer Ic-hFE characteristic curve, Ic-Vce (sat) characteristic curve and PT-Rtn characteristic curve is the alloy base material alloy leadframe for semiconductor devices, characterized in that it is within the range of error ± 1% with alloy 42. An alloy base material preparation step of preparing an alloy base material consisting of iron (Fe) and chromium (Cr), and a passivation step of removing the passivation oxide film formed on the surface of the alloy base material by removing the alloy base material after being immersed in a chemical solution for a predetermined time. Removing the oxide film and immersing the alloy base material from which the passive oxide film has been removed in a first plating solution, and then removing the oxide film to form a first plating layer having a predetermined thickness; and an alloy base material on which the first plating layer is formed. The second plating layer forming step of forming a second plating layer having a predetermined thickness by immersing in the second plating solution and then taken out, The passivation oxide removal step is made by immersing the alloy base material in hydrochloric acid (HCl) solution of 35 ~ 45vol% concentration at room temperature for 5 to 10 minutes In the forming of the first plating layer, the alloy base material is immersed in a plating solution in which Hg 125g / l solution and NiCl ₂ · 6H ₂ O 240g / l solution are mixed at room temperature, and a cathode current density is 5 to 10 A / dm ² , and a voltage Silver 6V, the anode is made by performing for 20 to 120 seconds under the conditions of nickel plate and carbon plate, In the forming of the second plating layer, the alloy base material on which the first plating layer is formed is immersed in a plating solution in which H ₂ SO ₄ 45-80 g / l solution and CuSO ₄ 150-250 g / l solution are mixed at room temperature. 1 ~ 8A / dm ² , anode current density is 0.5 ~ 5A / dm ² , anode is copper-containing plate, chlorine ion concentration is 20 ~ 120ppm for 10 ~ 30 minutes Method of preparation. The method of manufacturing a lead frame for a semiconductor device according to claim 13, wherein in the preparing of the alloy base material, the thickness of the alloy base material is 0.1 to 0.15 mm. The method of manufacturing a lead frame for a semiconductor device according to claim 13, wherein the alloy base material preparing step further comprises nickel (Ni). The method of claim 13, wherein the forming of the first plating layer is such that the thickness of the first plating layer is 0.2 to 0.8 μm. 15. The method of claim 13, wherein the forming of the first plating layer causes the first plating layer to be formed of nickel. The method of claim 13, wherein the forming of the second plating layer is such that the thickness of the second plating layer is 3 to 6 μm. The method of claim 13, wherein the forming of the second plating layer is such that the second plating layer is formed of any one selected from copper (Cu) and silver (Ag). The method of claim 13, wherein the preparing of the alloy base material comprises the alloy base material being stainless steel based. delete delete delete

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