JPH10261754A - Blank sheet for terminal and its manufacture - Google Patents

Blank sheet for terminal and its manufacture

Info

Publication number
JPH10261754A
JPH10261754A JP6432197A JP6432197A JPH10261754A JP H10261754 A JPH10261754 A JP H10261754A JP 6432197 A JP6432197 A JP 6432197A JP 6432197 A JP6432197 A JP 6432197A JP H10261754 A JPH10261754 A JP H10261754A
Authority
JP
Japan
Prior art keywords
surface layer
terminal
underlayer
substrate
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6432197A
Other languages
Japanese (ja)
Inventor
Hiroshi Yamada
廣志 山田
Yoshikazu Yamasako
義和 山迫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Daido Steel Co Ltd
Original Assignee
Daido Steel Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Daido Steel Co Ltd filed Critical Daido Steel Co Ltd
Priority to JP6432197A priority Critical patent/JPH10261754A/en
Publication of JPH10261754A publication Critical patent/JPH10261754A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Laminated Bodies (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain high corrosion resistance by covering the surface of a board composed of Fe based alloy with a surface layer of Pd or the like, regarding a blank sheet plate becoming a terminal member of a lead frame or the like. SOLUTION: In blank sheets 8, 10 for terminals, at least one surface of a board 1 composed of Fe-Ni based alloy or Fe-Cr based alloy is covered with a surface layer 6 for bonding which is composed of Pd or the like via substratum layers 2, 4 composed of Cu, Ni, etc. For obtaining the blank sheet plate 8 or the like, a manufacturing method is contained wherein the surfaces of the board 1 are covered with the substratum layers 2, 4 by using plating, the obtained intermediate blank sheet 3 is subject to cold rolling, and the surfaces of the substratum layers 2, 4 are covered with the surface layers 6 for bonding by using plating.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子を用い
た集積回路や配線基板等におけるリードフレーム等、各
種の電子・電気部品、電子・電気機器の接続用端子材を
得るために用いる耐食性に優れた端子用素板とその製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to corrosion resistance used to obtain various electronic and electric parts and terminal materials for connection of electronic and electric equipment, such as lead frames in integrated circuits and wiring boards using semiconductor elements. The present invention relates to an excellent terminal plate and a method of manufacturing the same.

【0002】[0002]

【従来の技術】一般に、端子材であるリードフレームの
材料には42%のNi(ニッケル)を含むFe−Ni系合
金やCu(銅)系合金が使用されている。そして、集積回
路等に内蔵され、配線基板上に実装する際やプリント基
板等のマザーボード上に接続する際、集積回路等から突
出するリードフレームとマザーボード側等の接続用端子
とを、半田付けして互いに導通させている。この場合、
上記リードフレームにおいて半田付けされるアウターリ
ードの表面には、予め半田がメッキ等により被覆されて
いる。
2. Description of the Related Art Generally, an Fe-Ni alloy containing 42% of Ni (nickel) or a Cu (copper) alloy is used as a material of a lead frame as a terminal material. Then, when mounting on a wiring board or connecting to a motherboard such as a printed circuit board, a lead frame protruding from the integrated circuit or the like and a connection terminal on the motherboard or the like are soldered when mounted on an integrated circuit or the like. Are electrically connected to each other. in this case,
The surface of the outer lead to be soldered in the lead frame is previously coated with solder by plating or the like.

【0003】一方、近年では環境保護の観点からPb
(鉛)の使用を規制する動きが出始めており、係るPbを
含む半田付けが敬遠される場合もある。このため、上記
リードフレームにおけるアウターリードの表面にも半田
以外のロウ付け用材料の被覆が検討されている。例え
ば、Cu系又はNi系の合金からなるリードフレームの
表面に、Pd(パラジウム)を薄くメッキ等にて被覆し
た接合用表面層を形成することにより、各種のロウ材を
用いてマザーボード側の接続用端子とロウ付けすること
が試みられている。
On the other hand, recently, from the viewpoint of environmental protection, Pb
There has been a movement to restrict the use of (lead), and soldering including such Pb may be avoided. For this reason, coating of a brazing material other than solder on the surface of the outer lead in the lead frame has been studied. For example, by forming a bonding surface layer in which Pd (palladium) is thinly coated by plating or the like on the surface of a lead frame made of a Cu-based or Ni-based alloy, the connection on the motherboard side using various brazing materials. It has been attempted to braze the terminal for use.

【0004】しかしながら、Fe−30〜50%Ni
系、又はFe−6〜16%Cr系等のFe系合金からな
るリードフレームの表面にPdをメッキすると、そのP
dのメッキ層はポーラスな組織であるため、腐食を生じ
る場合がある。この腐食は、リードフレーム本体のFe
系合金とPdのメッキ層との電位差が大きいことにより
形成される腐食電池が原因である。即ち、電位的にFe
は卑で、且つPdは貴であると共に、Pdのメッキ層の
ポーラスな組織内に両者を導通させる水分等の導体が存
在すると、これらの3者間において所謂腐食電池が形成
されるため、貴なPdから水素ガスが発生し、卑なFe
の表面からはFe2+が溶出してFe系合金が腐食するも
のである。
However, Fe-30 to 50% Ni
When Pd is plated on the surface of a lead frame made of an Fe-based alloy or an Fe-based alloy such as Fe-6 to 16% Cr,
Since the plating layer of d has a porous structure, corrosion may occur. This corrosion is caused by the Fe
The cause is a corrosion battery formed due to a large potential difference between the base alloy and the Pd plating layer. That is, the potential of Fe
Is base and Pd is noble, and if there is a conductor such as moisture in the porous structure of the Pd plating layer that conducts the two, a so-called corrosion battery is formed between these three members. Hydrogen gas is generated from Pd
Fe 2+ is eluted from the surface of the alloy and the Fe alloy is corroded.

【0005】[0005]

【発明が解決すべき課題】本発明は、以上のような従来
の技術における問題点を解決し、Fe系合金からなるリ
ードフレーム等の端子板の表面に、Pd等からなる接合
用表面層を被覆した耐食性に優れた端子用素板とその製
造方法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems in the prior art and provides a joining surface layer made of Pd or the like on the surface of a terminal plate such as a lead frame made of an Fe-based alloy. It is an object of the present invention to provide a coated terminal plate excellent in corrosion resistance and a method for producing the same.

【0006】[0006]

【課題を解決するための手段】本発明は、上記の課題を
解決するため、Fe系合金からなるリードフレーム等の
端子材の表面に、Cu等の下地層を介してPd等からな
る接合用表面層を被覆することに着想して成されたもの
である。即ち、本発明の端子用素板は、Fe−Ni系、
又はFe−Cr系の合金からなる基板と、この基板の少
なくとも一方の表面にCu,Ni,Sn,Au,又はAg
の何れかの少なくとも一層以上からなる下地層を介して
Pd等の白金族に属する金属又はこれらの金属をベース
とする合金からなる接合用表面層を被覆したことを特徴
とする。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method for joining Pd or the like to the surface of a terminal material such as a lead frame made of an Fe-based alloy via an underlayer of Cu or the like. This was made with the idea of coating the surface layer. That is, the terminal plate of the present invention is a Fe-Ni-based
Or a substrate made of an Fe—Cr alloy, and Cu, Ni, Sn, Au, or Ag on at least one surface of the substrate.
And a bonding surface layer made of a metal belonging to the platinum group such as Pd or an alloy based on these metals, via an underlayer made of at least one of the above.

【0007】また、上記下地層の厚さが少なくとも0.
3μm以上である端子用素板、或いは上記接合用表面層
の厚さが少なくとも0.03μm以上である端子用素板
も含まれる。下地層が0.3μm未満では前記腐食電池
の形成が阻止し難くくなり、表面層が0.03μm未満で
はロウ材との接合(濡れ)性が不足し得るためである。こ
れらの構成によれば、下地層によってFe系の基板とP
d等の接合用表面層との間における前記腐食電池が解消
されるため、優れた耐食性を有する端子用素板を提供す
ることができる。しかも、上記接合用表面層は薄く均一
に被覆されるので、各種のロウ材を用いて相手側の接続
用端子と容易且つ確実に接合できる。尚、上記下地層の
厚さの上限は、5μm以下、望ましくは3μm以下であ
る。また、この下地層の組織は緻密である程望ましく、
該組織内部の空孔等が占める割合は、面積率で10%以
下、より望ましくは5%以下である。更に、上記表面層
の厚さの上限は、0.5μm以下、望ましくは0.3μm
以下である。又、上記端子用素板全体の厚さは0.1mm
乃至0.5mmの範囲内である。
[0007] The thickness of the underlayer may be at least 0.1 mm.
A terminal plate having a thickness of 3 μm or more, or a terminal plate having a thickness of the bonding surface layer of at least 0.03 μm is also included. If the underlayer is less than 0.3 μm, it is difficult to prevent the formation of the corrosion battery, and if the surface layer is less than 0.03 μm, the bonding (wetting) property with the brazing material may be insufficient. According to these structures, the Fe-based substrate and the P
Since the corrosion battery between the bonding surface layer such as d and the like is eliminated, a terminal plate having excellent corrosion resistance can be provided. In addition, since the bonding surface layer is coated uniformly and thinly, the bonding surface layer can be easily and reliably bonded to the mating connection terminal using various brazing materials. The upper limit of the thickness of the underlayer is 5 μm or less, preferably 3 μm or less. Further, it is desirable that the structure of the underlayer is dense,
The proportion occupied by pores and the like inside the tissue is 10% or less in area ratio, and more preferably 5% or less. Further, the upper limit of the thickness of the surface layer is 0.5 μm or less, preferably 0.3 μm.
It is as follows. The overall thickness of the terminal plate is 0.1 mm.
Within a range of 0.5 mm to 0.5 mm.

【0008】更に、上記端子用素板を得るため、Fe−
Ni系、又はFe−Cr系の合金からなる基板の少なく
とも一方の表面に、Cu,Ni,Sn,Au,又はAg
の何れかの少なくとも一層以上からなる下地層をメッキ
により被覆し、得られた中間素板に対し圧下率5%以上
の冷間圧延を施した後、上記下地層の表面にPd等の白
金族に属する金属又はこれらの金属をベースとする合金
をメッキして接合用表面層を被覆することを特徴とする
端子用素板の製造方法も含まれる。係る構成によれば、
メッキによるポーラスな下地層は内部の空孔を押圧さ
れ、緻密で均一な厚さにされた状態で、その表面上に接
合用表面層を被覆する。このため、下地層は基板と接合
用表面層との間に薄く均一、緻密に被覆されるので、従
来のような腐食電池の形成を確実に阻止、又は抑制する
ことが可能となる。
[0008] Further, in order to obtain the terminal plate, the Fe-
Cu, Ni, Sn, Au, or Ag is formed on at least one surface of a substrate made of a Ni-based or Fe-Cr-based alloy.
And then subjecting the obtained intermediate base plate to cold rolling at a rolling reduction of 5% or more, and then forming a platinum group such as Pd on the surface of the base layer. And a method for producing a base plate for a terminal, wherein the surface layer for joining is coated by plating a metal belonging to the above or an alloy based on these metals. According to such a configuration,
The porous underlayer formed by plating presses the internal pores, and covers the surface with a bonding surface layer in a state of a dense and uniform thickness. For this reason, since the underlayer is thinly and uniformly and densely coated between the substrate and the bonding surface layer, it is possible to reliably prevent or suppress the formation of the conventional corrosion battery.

【0009】上記冷間圧延の圧下率を5%以上としたの
は、これ未満では下地層中に空孔が残留して、基板と表
面層との間に前記腐食電池を形成し得るため、これを防
ぐためである。このため、望ましい圧下率は10%以
上、より望ましくは20%以上、最も望ましくは50%
以上である。尚、前記メッキには主に電解メッキを用い
るが、溶融浸漬メッキや気相メッキ等も含まれる。加え
て、上記冷間圧延の後、更に真空中又はAr等の不活性
ガス中で拡散焼鈍を施す製造方法も含まれる。これによ
ると、下地層と基板は両者の接触面において相互に拡散
し合い下地層のCu等が基板中に侵入して両者間の電位
差を緩和し、耐食性も一層向上すると共に、上記表面層
も安定した被覆状態とすることが可能となる。尚、上記
焼鈍は約700〜1100℃で、約1〜30分程行われ
る。
The reason why the rolling reduction of the cold rolling is set to 5% or more is that if the rolling reduction is less than 5%, pores remain in the underlayer and the corrosion cell can be formed between the substrate and the surface layer. This is to prevent this. Therefore, the desired rolling reduction is 10% or more, more preferably 20% or more, and most preferably 50%.
That is all. In addition, although electroplating is mainly used for the plating, hot dipping plating and vapor phase plating are also included. In addition, a manufacturing method in which after the above-mentioned cold rolling, diffusion annealing is further performed in a vacuum or in an inert gas such as Ar is included. According to this, the underlayer and the substrate are mutually diffused at the contact surface between them, and Cu or the like of the underlayer penetrates into the substrate to reduce the potential difference between the two, and the corrosion resistance is further improved, and the surface layer is also improved. A stable coating state can be obtained. The annealing is performed at about 700 to 1100 ° C. for about 1 to 30 minutes.

【0010】[0010]

【実施の形態】以下において、本発明の実施に好適な形
態を図面と共に説明する。図1は本発明の端子用素板を
得るための製造工程を示す。同図(A)に示すように、所
定の組成に調整したFe−Ni系、又はFe−Cr系の
合金を真空溶解等により溶解し、所定形状のインゴット
を得る(ステップ1,以下S1のように記する)。次に1
000℃以上で上記インゴットを熱間鍛造し、約20mm
の厚板とする(S2)。この厚板の表面に生成したスケー
ルをグランダーや酸洗等により除去し(S3)た後、再び
1000℃以上に加熱して熱間圧延を施し、厚さ数mmの
薄板とする(S4)。この薄板の表面におけるスケールを
再度除去(S5)した後、冷間圧延(S6)とこの圧延によ
る内部歪を除く焼鈍(S7)を所要回数に渉って繰り返
し、図2(A)に示すような厚さ約0.5mm程度の基板1
を得る。
Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a production process for obtaining a terminal plate of the present invention. As shown in FIG. 1A, an Fe-Ni-based or Fe-Cr-based alloy adjusted to a predetermined composition is melted by vacuum melting or the like to obtain an ingot of a predetermined shape (Step 1, hereinafter referred to as S1). ). Then 1
Approximately 20mm
(S2). The scale formed on the surface of the thick plate is removed by a glander, pickling, or the like (S3), and then heated again to 1000 ° C. or higher and subjected to hot rolling to form a thin plate having a thickness of several mm (S4). After the scale on the surface of the thin plate is removed again (S5), cold rolling (S6) and annealing (S7) for removing the internal strain due to the rolling are repeated for a required number of times, as shown in FIG. 2 (A). Substrate 1 with a thickness of about 0.5mm
Get.

【0011】この基板1の一方又は両表面にCu,N
i,Sn,Au,又はAgの何れかの少なくとも1層以
上からなる下地層を例えば電解メッキ(S8)して被覆し
て下地層2とする(図2(B)参照)。得られた中間素板3
に対し圧下率5%以上の冷間圧延(S9)を施し、内部の
空孔を押圧しつつ上記メッキによるポーラスな下地層2
を薄く緻密にする。次いで、この下地層2の表面にPd
等の白金族に属する金属又はこれらの金属をベースとす
る合金を例えば電解メッキによりメッキ(S10)するこ
とで、接合用表面層6を被覆して端子用素板8を得る
(図2(C)参照)。或いは、図1(B)に示すように、上記
冷間圧延(S9)を行った後、真空中か又はAr,N2,H4
等の不活性ガス中で拡散焼鈍(S11)を行い、下地層2
と基板1との接触面において相互に拡散させて、両者間
の組成の傾斜濃度を緩やかにした後、上記下地層2の表
面にPd等をメッキ(S12)して、接合用表面層6を被
覆することにより端子用素板8とすることもできる。
On one or both surfaces of the substrate 1, Cu, N
An underlayer made of at least one of i, Sn, Au, and Ag is coated, for example, by electrolytic plating (S8) to form an underlayer 2 (see FIG. 2B). Intermediate blank 3 obtained
Is subjected to cold rolling (S9) with a rolling reduction of 5% or more, and the porous underlying layer 2 formed by the plating is pressed while pressing the internal holes.
Thin and dense. Next, Pd is applied to the surface of the underlayer 2.
By plating a metal belonging to the platinum group or an alloy based on such a metal, for example, by electrolytic plating (S10), the joining surface layer 6 is covered to obtain the base plate 8 for a terminal.
(See FIG. 2 (C)). Alternatively, as shown in FIG. 1 (B), after the cold rolling (S9) is performed, a vacuum or Ar, N 2 , H 4
Diffusion annealing (S11) in an inert gas such as
Are diffused with each other at the contact surface between the substrate and the substrate 1 to moderate the gradient concentration of the composition between the two, and then the surface of the underlayer 2 is plated with Pd or the like (S12) to form the bonding surface layer 6 By coating, the base plate for terminal 8 can be obtained.

【0012】以上のように、本発明の端子用素板8は、
Fe−Ni系、又はFe−Cr系合金の基板1とPd等
の接合用表面層6との間に、Cu等からなる緻密な組織
の下地層2を介在させているので、基板1と表面層6間
の電位差は2段階に緩和され、従来における腐食電池の
形成を確実に予防できる。従って、種々の環境下におい
ても長期に渉って優れた耐食性を有する端子材を提供す
ることが可能となる。また、図2(D)に示すように、上
記下地層2の表面上に更に別個の金属又は合金による下
地層4をメッキした後、上記同様に冷間圧延(S9)、必
要に応じて拡散焼鈍(S11)を行って、図2(E)に示す
ように、Pd等のメッキ(S10,12)により接合用表面
層6を被覆した端子用素板10とすることもできる。係
る二層の下地層2,4やそれ以上の下地層を基板1と表
面層6との電位差に対応して徐々に緩和させるような順
序で被覆することにより、一層優れた耐食性を有する端
子材を提供することも可能となる。
As described above, the terminal base plate 8 of the present invention comprises:
Since the underlayer 2 having a dense structure made of Cu or the like is interposed between the substrate 1 made of an Fe-Ni or Fe-Cr alloy and the bonding surface layer 6 made of Pd or the like, The potential difference between the layers 6 is reduced in two stages, and the formation of a conventional corrosion battery can be reliably prevented. Therefore, it is possible to provide a terminal material having excellent corrosion resistance over a long period of time even under various environments. Further, as shown in FIG. 2 (D), after further plating an underlayer 4 of a different metal or alloy on the surface of the underlayer 2, cold rolling (S9) as described above, and After annealing (S11), as shown in FIG. 2 (E), it is also possible to obtain the terminal plate 10 in which the joining surface layer 6 is covered by plating (S10, 12) of Pd or the like. A terminal material having more excellent corrosion resistance by coating the two underlayers 2 and 4 or more underlayers in such an order as to gradually relax the underlayer according to the potential difference between the substrate 1 and the surface layer 6. Can also be provided.

【0013】[0013]

【実施例】以下において、本発明の具体的な実施例を説
明すると共に、比較例との間で耐食性等について比較す
る。先ず、Fe−Ni系の合金として、C;0.014
%、Si;0.24%、Mn;0.51%、P;0.00
2%、Ni;41.8%、残部;Feからなる組成に調整
した合金材料を真空溶解(S1)し、所定形状のインゴッ
トにした。このインゴットを1100℃に加熱して熱間
鍛造(S2)を施し、厚さ20mm、幅50mmの厚板とし
た。次いで、この厚板の表面に付着した酸化スケールを
グラインダーで除去し(S3)た後、1100℃に加熱し
て圧下率約90%の熱間圧延(S4)を施し、厚さ2mmの
薄板とした。この薄板の表面の酸化スケールを再度グラ
インダーで除去(S5)した後、冷間圧延(S6)とこれに
よる歪を除去する焼鈍(S7)を所要回数に渉って繰り返
して行い、厚さ0.5mmの基板1を得た。
EXAMPLES In the following, specific examples of the present invention will be described, and corrosion resistance and the like will be compared with comparative examples. First, as an Fe-Ni alloy, C: 0.014
%, Si: 0.24%, Mn: 0.51%, P: 0.00
An alloy material adjusted to a composition of 2%, Ni: 41.8%, balance: Fe was vacuum melted (S1) to form an ingot of a predetermined shape. This ingot was heated to 1100 ° C. and subjected to hot forging (S2) to form a thick plate having a thickness of 20 mm and a width of 50 mm. Next, the oxide scale adhering to the surface of the thick plate was removed by a grinder (S3), and then heated to 1100 ° C. and subjected to hot rolling (S4) with a reduction of about 90% to form a thin plate having a thickness of 2 mm. did. After the oxide scale on the surface of the thin plate is removed again by a grinder (S5), cold rolling (S6) and annealing (S7) for removing the distortion caused by the rolling are repeated by a required number of times to obtain a thickness of 0.1 mm. A substrate 1 of 5 mm was obtained.

【0014】次に、この基板1を所定のサイズ(50×
100mm)に複数枚に切断し、それぞれの両表面に電解
メッキ(S8)を施し、厚さ約3μmのCu、又はNiか
らなる下地層2を被覆した。尚、先にNiをメッキし、
その上面に更にCuをメッキした二層の下地層2,4を
被覆したものも併せて用意した。次いで、これらの中間
素板3を圧下率約70%において冷間圧延(S9)し、厚
さ0.15mmとした。この板の各下地層2,4の表面上
に更に電解メッキを施し(S10)、厚さ約3μmのPd
からなる接合用表面層6を被覆した本発明の端子用素板
8,10を上記下地層2,4の材質別に3種類(Cu;発
明例1,Ni;発明例2,Ni及びCu;発明例3)得た。
また、各発明例について、上記冷間圧延(S9)の後、約
1000℃で5分間の拡散焼鈍(S11)を真空中で行う
と共に、それぞれについて電解メッキ(S12)を施し
て、厚さ約3μmのPdからなる接合用表面層6を被覆
した端子用素板8,10も得た。
Next, the substrate 1 is sized to a predetermined size (50 ×
(100 mm), and both surfaces were subjected to electrolytic plating (S8) to cover an underlayer 2 of Cu or Ni having a thickness of about 3 μm. In addition, Ni is plated first,
The upper surface was further provided with two layers of underlayers 2 and 4 plated with Cu. Next, these intermediate blanks 3 were cold-rolled (S9) at a rolling reduction of about 70% to a thickness of 0.15 mm. Electrolytic plating is further performed on the surface of each of the base layers 2 and 4 of this plate (S10), and Pd having a thickness of about 3 μm is formed.
The terminal blanks 8 and 10 of the present invention covered with the joining surface layer 6 made of the following three types (Cu; Invention Example 1, Ni; Invention Examples 2, Ni and Cu; Invention) Example 3) obtained.
Further, for each invention example, after the cold rolling (S9), diffusion annealing (S11) was performed at about 1000 ° C. for 5 minutes in a vacuum, and electrolytic plating (S12) was applied to each of them to obtain a thickness of about The terminal blanks 8 and 10 covered with the joining surface layer 6 made of 3 μm Pd were also obtained.

【0015】一方、Fe−Cr系の合金として、C;
0.028%、Si;0.34%、Mn;0.54%、
P;0.004%、S;0.005%、Cr;8.5%、
残部;Feからなる組成に調整した合金材料を真空溶解
(S1)し、所定形状のインゴットにした。係るインゴッ
トを1100℃に加熱して熱間鍛造(S2)を施し、厚さ
20mm、幅100mmの厚板とした。次に、この厚板の表
面に付着した酸化スケールをグラインダーで除去し(S
3)た後、1100℃に加熱して圧下率約90%の熱間
圧延(S4)を施し、厚さ2mmの薄板を得た。この薄板の
表面の酸化スケールを再度グラインダーで除去し(S5)
た後、冷間圧延(S6)とこれによる内部歪を除去するA
rガス中での歪除去焼鈍(S7)を所要回数に渉って繰り
返して行うことによって、厚さ0.5mmの基板1を得
た。
On the other hand, as an Fe—Cr alloy, C:
0.028%, Si; 0.34%, Mn; 0.54%,
P: 0.004%, S: 0.005%, Cr: 8.5%,
Rest: vacuum melting of alloy material adjusted to Fe composition
(S1) to form an ingot of a predetermined shape. The ingot was heated to 1100 ° C. and subjected to hot forging (S2) to obtain a thick plate having a thickness of 20 mm and a width of 100 mm. Next, the oxide scale adhering to the surface of this thick plate is removed with a grinder (S
3) After that, it was heated to 1100 ° C. and subjected to hot rolling (S4) with a reduction of about 90% to obtain a thin plate having a thickness of 2 mm. The oxide scale on the surface of this thin plate is removed again by a grinder (S5).
Then, cold rolling (S6) and A for removing internal strain due to the cold rolling (S6)
The substrate 1 having a thickness of 0.5 mm was obtained by repeatedly performing the strain removal annealing (S7) in r gas for a required number of times.

【0016】更に、この基板1を所定のサイズ(50×
100mm)に複数枚に切断し、それぞれの両表面に電解
メッキ(S8)を施し、厚さ約3μmのCu、又はNiか
らなる下地層2を被覆した。尚、先にNiをメッキし、
その上面に更にCuをメッキした二層の下地層2,4を
被覆したものも併せて用意した。次いで、これらの中間
素板3を圧下率約70%において冷間圧延(S9)し、厚
さ0.15mmとした。この板の各下地層2,4の表面上
に更に電解メッキを施し(S10)、厚さ約3μmのPd
からなる接合用表面層6を被覆した本発明の端子用素板
8,10を上記下地層2,4の材質別に3種類(Cu;発
明例4,Ni;発明例5,Ni及びCu;発明例6)得た。
また、各発明例について、上記冷間圧延(S9)の後、約
750℃で2分間の拡散焼鈍を真空中で行う(S11)と
共に、各々につき電解メッキ(S12)を施し、厚さ約3
μmのPdからなる接合用表面層6を被覆した端子用素
板8等も得た。
Further, the substrate 1 has a predetermined size (50 ×
(100 mm), and both surfaces were subjected to electrolytic plating (S8) to cover an underlayer 2 of Cu or Ni having a thickness of about 3 μm. In addition, Ni is plated first,
The upper surface was further provided with two layers of underlayers 2 and 4 plated with Cu. Next, these intermediate blanks 3 were cold-rolled (S9) at a rolling reduction of about 70% to a thickness of 0.15 mm. Electrolytic plating is further performed on the surface of each of the base layers 2 and 4 of this plate (S10), and Pd having a thickness of about 3 μm is formed.
The terminal blanks 8 and 10 of the present invention coated with the joining surface layer 6 made of the following three types (Cu; Invention Example 4, Ni; Invention Examples 5, Ni and Cu; Invention) Example 6) obtained.
Further, for each invention example, after the cold rolling (S9), diffusion annealing at about 750 ° C. for 2 minutes is performed in a vacuum (S11), and electrolytic plating (S12) is applied to each of them to obtain a thickness of about 3 mm.
A terminal plate 8 and the like coated with a bonding surface layer 6 of Pd having a thickness of μm were also obtained.

【0017】比較例として、前記と同じFe−Ni系、
及びFe−Cr系の合金からなり、同じプロセスによる
基板1をそれぞれ用意し、上記下地層2,4のメッキ
(S8)及び冷間圧延(S9)をせず、各基板1の表面上に
直接電解メッキ(S10)を施し、厚さ約3μmのPdか
らなる接合用表面層6を被覆した端子用素板を用意し
た。上記基板1がFe−Ni系合金のものを比較例1、
Fe−Cr系合金のものを比較例2とした。そして、各
発明例1〜6と比較例1,2の各試験片をそれぞれ20
枚ずつ作成し、それぞれのうちの10枚を塩水噴霧試験
に、残りの10枚をロウ付け試験に使用した。
As a comparative example, the same Fe—Ni system as described above,
And a substrate 1 made of an Fe-Cr alloy and prepared by the same process, and plating the underlayers 2 and 4
(S8) and a raw plate for terminal coated with a bonding surface layer 6 made of Pd having a thickness of about 3 μm by performing electrolytic plating (S10) directly on the surface of each substrate 1 without performing cold rolling (S9). Was prepared. The substrate 1 was made of a Fe—Ni alloy, and Comparative Example 1
An Fe-Cr alloy was used as Comparative Example 2. Then, each test piece of each of Invention Examples 1 to 6 and Comparative Examples 1 and 2 was
Sheets were prepared one by one, ten of which were used for the salt spray test and the remaining ten were used for the brazing test.

【0018】塩水噴霧試験(JIS−Z2371)は次の
ようにして行った。濃度5%の塩水を採取した噴霧液の
量が、各試験片の80cm2の水平採取面積に対し、1時間
当たり平均1〜2リットルとなるよう24時間に渉って噴霧
し、表面に発生する錆の面積を測定し、これを面積率に
よって表したものである。発明例1〜6と比較例1,2
の各試験片10枚の平均値を算出した結果を表1に示
す。尚、発明例1〜6の各右欄は、それぞれについて前
記拡散焼鈍(S11)を行った後に表面層を得る電解メッ
キ(S12)を施したものを示す。
The salt spray test (JIS-Z2371) was performed as follows. Sprayed over a 24-hour period so that the amount of the sprayed liquid from which the 5% concentration of salt water was collected was 1 to 2 liters per hour on an average of 1 to 2 liters per hour on a horizontal sampling area of 80 cm 2 of each test piece. The area of the rust was measured, and this was represented by the area ratio. Invention Examples 1 to 6 and Comparative Examples 1 and 2
Table 1 shows the results of calculating the average value of each of the ten test pieces. In addition, each right column of the invention examples 1-6 shows what performed the electrolytic plating (S12) which obtains a surface layer after performing the said diffusion annealing (S11) about each.

【0019】[0019]

【表1】[Table 1]

【0020】表1の結果から、発明例は何れも比較例
1,2に対して、錆の面積率が格段に低いこと、及び発
明例中においてもCu又はNi単独の下地層2による発
明例1,2,4,5よりも、Ni及びCuの順で二層の
下地層2,4を基板1と接合用表面層6の間に介在させ
た発明例3,6の方が錆の面積率が低いことが判る。ま
た、各発明例毎でも、右欄側の前記拡散焼鈍(S11)を
行った後にPdメッキ(S12)を施したものの方が、や
や面積率が低いことも判る。これらの結果から、各発明
例のものは、緻密な下地層2又は同2,4を基板1と接
合用表面層6の間に介在させたことにより、両者間にお
ける腐食電池の形成を著しく低減したことが容易に理解
される。また、発明例3,6のように、二層の下地層
2,4を介在させて、基板1と接合用表面層6の間にお
ける電位差を一層緩やかに傾斜させることで、更に優れ
た耐食性を得やすくなることも理解される。更に、基板
1と表面層6の間で予め拡散焼鈍(S11)を施すことに
よっても同様に耐食性を一層向上させ得ることも理解さ
れる。
From the results shown in Table 1, it can be seen that the area ratio of rust is much lower in each of the invention examples than in comparative examples 1 and 2, and among the invention examples, the invention examples using the underlayer 2 consisting solely of Cu or Ni. Inventive Examples 3 and 6, in which two underlayers 2, 4 were interposed between the substrate 1 and the bonding surface layer 6 in the order of Ni and Cu, in the order of Ni and Cu, in comparison with 1, 2, 4, and 5, the area of rust was larger. It turns out that the rate is low. Also, in each of the invention examples, it can be seen that the area ratio is slightly lower when the Pd plating (S12) is performed after the diffusion annealing (S11) on the right column side. From these results, in each of the invention examples, the formation of the corrosion battery between the two was significantly reduced by interposing the dense underlayer 2 or 2, 4 between the substrate 1 and the bonding surface layer 6. It is easy to understand what has been done. Further, as in Invention Examples 3 and 6, the two layers of the underlayers 2 and 4 are interposed, and the potential difference between the substrate 1 and the bonding surface layer 6 is more gradually inclined, thereby further improving the corrosion resistance. It is also understood that it becomes easier to obtain. Further, it is understood that the corrosion resistance can be further improved by performing diffusion annealing (S11) between the substrate 1 and the surface layer 6 in advance.

【0021】一方、ロウ付け試験は、ロウ材としてSn
−20%Agを溶融し、係るロウ材の溶湯中に前記発明
例1〜6及び比較例1,2の試験片をそれぞれ10枚ず
つ5秒間浸漬して、各々の表面において上記ロウ材が濡
れて付着した面積を測定し、これを面積率によって表し
たものである。各発明例及び比較例毎の平均値を算出し
た結果を表2に示す。
On the other hand, in the brazing test, Sn
-20% Ag was melted, and the test pieces of Invention Examples 1 to 6 and Comparative Examples 1 and 2 were immersed in a molten metal of the brazing material for 10 seconds each for 5 seconds, and the brazing material was wet on each surface. The area that was adhered to the substrate was measured, and this was represented by the area ratio. Table 2 shows the result of calculating the average value for each invention example and comparative example.

【0022】[0022]

【表2】[Table 2]

【0023】表2の結果から、発明例のものは何れも比
較例と同等又はそれ以上の濡れ面積率を有することが判
る。従って、基板1と接合用表面層6の間に下地層2,
4が介在しても何らロウ付け性には影響しないことが容
易に理解される。更に、表1及び表2の結果を総合する
と、発明例の各素板は、下地層の材質や積層形態に応じ
て優れた耐食性を有すると共に、半導体素子等の電子部
品における端子材として使用されても、係る電子部品を
実装したり、搭載する相手側のマザーボード等の端子材
と容易にロウ付けして接合できることも明白である。
From the results shown in Table 2, it can be seen that all of the invention examples have the same or higher wet area ratio as the comparative example. Therefore, the base layer 2 is provided between the substrate 1 and the bonding surface layer 6.
It is easily understood that the interposition of No. 4 does not affect the brazing property at all. Furthermore, when the results of Tables 1 and 2 are combined, each of the base plates of the invention example has excellent corrosion resistance according to the material of the underlayer and the lamination form, and is used as a terminal material in electronic components such as semiconductor elements. However, it is clear that such an electronic component can be easily mounted or joined to a terminal material such as a motherboard on which the electronic component is mounted by brazing.

【0024】尚、本発明は以上の形態や実施例に限定さ
れるものではない。基板となるFe−Ni系合金は、主
に30〜50wt%Niを含有するものが用いられ、例え
ばFe−36%Ni(インバー)、Fe−45%Ni(パ
ーマロイ)、Fe−32%Ni等や、これらにCu,C
r,Mo,W,Nb等の少なくとも1種以上を1〜4%添
加したものが用いられる。また、基板となるFe−Cr
系合金には、主に6〜18wt%Crを含有するものが用
いられ、例えばFe−13%Cr、Fe−16%Cr等
や、或いはこれらの合金に約1〜3%のNi等を添加し
たものが用いられる。更に、下地層の材質も前記Cu,
Niの他に、それらの合金や、Sn,Au,又はAg、或
いはこれらをベースとする合金を用いることも可能であ
る。また、接合用表面層の材質も前記Pdの他に、Pd
基合金や、Pt,Ru,Os,Rh,Irからなる白金族に
属する金属やこれらをベースとする合金を用いることも
できる。
It should be noted that the present invention is not limited to the above embodiments and examples. As the Fe-Ni-based alloy serving as the substrate, one containing mainly 30 to 50 wt% Ni is used, for example, Fe-36% Ni (Invar), Fe-45% Ni (Permalloy), Fe-32% Ni, etc. Or Cu, C
What added at least 1 type of r, Mo, W, Nb, etc. to 1-4% is used. In addition, Fe-Cr serving as a substrate
As the system alloys, those containing mainly 6 to 18 wt% Cr are used. For example, Fe-13% Cr, Fe-16% Cr, etc., or about 1-3% Ni, etc. are added to these alloys. Is used. Further, the material of the underlayer is also Cu,
In addition to Ni, it is also possible to use alloys thereof, Sn, Au, or Ag, or alloys based on these. Also, the material of the bonding surface layer is Pd in addition to Pd.
A base alloy, a metal belonging to the platinum group consisting of Pt, Ru, Os, Rh, and Ir, and an alloy based on these metals can also be used.

【0025】更に、下地層や接合用表面層は、ロウ付け
すべき相手側の端子材との接合形態に応じて、基板の一
方の表面のみに被覆したり、或いは、例えばリードフレ
ームとして用いる場合、プレスで打ち抜き加工された後
にアウターリードとなる部分の表面のみに被覆するとい
うように、基板の一方又は両方の表面における一部分に
のみ被覆することも可能である。加えて、端子用素板の
用途もリードフレームの他に、ダイオード、コンデン
サ、又は抵抗チップ等の電子部品における外部端子材や
これと内部の端子部分を含む端子材等に適用することも
可能である。
Further, the underlayer and the bonding surface layer may be coated on only one surface of the substrate, or may be used, for example, as a lead frame, depending on the bonding form with the terminal material to be brazed. It is also possible to cover only a part of one or both surfaces of the substrate, for example, to cover only the surface of the part which becomes the outer lead after being punched by a press. In addition, it is also possible to use the terminal plate for an external terminal material in an electronic component such as a diode, a capacitor, or a resistive chip, or a terminal material including the internal terminal portion, in addition to the lead frame. is there.

【0026】[0026]

【発明の効果】以上において説明した本発明の端子用素
板によれば、Fe−Ni系又はFe−Cr系の合金から
なる基板の表面にCu等からなる下地層を介してPd等
の接合用表面層を被覆しているので、該表面層と基板間
の腐食電池の形成を著しく抑制した優れた耐食性を有す
る端子材を提供することが可能となる。また、本発明の
端子用素板の製造方法によれば、上記基板上に緻密な組
織による下地層を介して接合用表面層を被覆させた端子
用素板を確実に且つ所要量に応じて容易に提供すること
が可能となる。
According to the terminal blank of the present invention described above, the bonding of Pd or the like to the surface of a substrate made of an Fe-Ni or Fe-Cr alloy through an underlayer made of Cu or the like. Since the surface layer is coated with the surface layer for use, it is possible to provide a terminal material having excellent corrosion resistance in which formation of a corrosion cell between the surface layer and the substrate is significantly suppressed. In addition, according to the method for manufacturing a terminal element plate of the present invention, the terminal element sheet in which the bonding surface layer is coated on the substrate via the dense base layer with a dense structure is reliably and in accordance with a required amount. It can be easily provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(A)及び(B)は共に、本発明の製造方法を示す
概略の流れ図である。
1 (A) and 1 (B) are schematic flow charts showing a production method of the present invention.

【図2】(A)乃至(C)は本発明の一製造方法の各工程を
示す断面図、(D)及び(E)は別の製造方法の各工程を示
す断面図である。
FIGS. 2A to 2C are cross-sectional views showing respective steps of one manufacturing method of the present invention, and FIGS. 2D and 2E are cross-sectional views showing respective steps of another manufacturing method.

【符号の説明】[Explanation of symbols]

1…………………基板 2,4……………下地層 3…………………中間素板 6…………………接合用表面層 8,10…………端子用素板 DESCRIPTION OF SYMBOLS 1 ... Board | substrate 2, 4 ... Underlayer 3 ... Intermediate base plate 6 ... Bonding surface layer 8, 10 ... Terminal Base plate

【表1】 [Table 1]

【表2】 [Table 2]

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】Fe−Ni系、又はFe−Cr系の合金か
らなる基板と、この基板の少なくとも一方の表面にC
u,Ni,Sn,Au,又はAgの何れかの少なくとも
一層以上からなる下地層を介して、Pd等の白金族に属
する金属又はこれらの金属をベースとする合金からなる
接合用表面層を被覆したことを特徴とする端子用素板。
1. A substrate made of an Fe--Ni-based or Fe--Cr-based alloy, and at least one surface of the substrate
A bonding surface layer made of a metal belonging to the platinum group, such as Pd, or an alloy based on these metals is coated via an underlayer made of at least one of u, Ni, Sn, Au, and Ag. A terminal plate for a terminal.
【請求項2】前記下地層の厚さが少なくとも0.3μm
以上であることを特徴とする請求項1に記載の端子用素
板。
2. The thickness of the underlayer is at least 0.3 μm.
2. The terminal plate according to claim 1, wherein:
【請求項3】前記接合用表面層の厚さが少なくとも0.
03μm以上であることを特徴とする請求項1又は2に
記載の端子用素板。
3. The bonding surface layer has a thickness of at least 0.5.
3. The terminal plate according to claim 1, wherein the terminal plate has a thickness of 03 μm or more. 4.
【請求項4】Fe−Ni系、又はFe−Cr系の合金か
らなる基板の少なくとも一方の表面に、Cu,Ni,S
n,Au,又はAgの何れかの少なくとも一層以上から
なる下地層をメッキにより被覆し、得られた中間素板に
対し圧下率5%以上の冷間圧延を施した後、上記下地層
の表面にPd等の白金族に属する金属又はこれらの金属
をベースとする合金をメッキして接合用表面層を被覆す
ることを特徴とする端子用素板の製造方法。
4. A substrate made of an Fe—Ni-based or Fe—Cr-based alloy, wherein Cu, Ni, S
An underlayer consisting of at least one of n, Au, and Ag is coated by plating, and the obtained intermediate base plate is subjected to cold rolling at a rolling reduction of 5% or more, and then the surface of the underlayer is coated. Plating a metal belonging to the platinum group such as Pd or an alloy based on these metals to cover the joining surface layer.
【請求項5】前記冷間圧延の後、更に真空中又は不活性
ガス中で拡散焼鈍を施すことを特徴とする請求項4に記
載の端子用素板の製造方法。
5. The method according to claim 4, wherein after the cold rolling, diffusion annealing is further performed in a vacuum or an inert gas.
JP6432197A 1997-03-18 1997-03-18 Blank sheet for terminal and its manufacture Withdrawn JPH10261754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6432197A JPH10261754A (en) 1997-03-18 1997-03-18 Blank sheet for terminal and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6432197A JPH10261754A (en) 1997-03-18 1997-03-18 Blank sheet for terminal and its manufacture

Publications (1)

Publication Number Publication Date
JPH10261754A true JPH10261754A (en) 1998-09-29

Family

ID=13254866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6432197A Withdrawn JPH10261754A (en) 1997-03-18 1997-03-18 Blank sheet for terminal and its manufacture

Country Status (1)

Country Link
JP (1) JPH10261754A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005311353A (en) * 2004-04-16 2005-11-04 Samsung Techwin Co Ltd Lead frame and manufacturing method therefor
KR100729019B1 (en) * 2005-10-12 2007-06-14 주식회사 케이이씨 Lead frame for semiconductor device and manufacturing methode thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005311353A (en) * 2004-04-16 2005-11-04 Samsung Techwin Co Ltd Lead frame and manufacturing method therefor
KR100729019B1 (en) * 2005-10-12 2007-06-14 주식회사 케이이씨 Lead frame for semiconductor device and manufacturing methode thereof

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