KR100726094B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR100726094B1
KR100726094B1 KR1020050131275A KR20050131275A KR100726094B1 KR 100726094 B1 KR100726094 B1 KR 100726094B1 KR 1020050131275 A KR1020050131275 A KR 1020050131275A KR 20050131275 A KR20050131275 A KR 20050131275A KR 100726094 B1 KR100726094 B1 KR 100726094B1
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oxide layer
pad oxide
layer
semiconductor device
semiconductor substrate
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KR1020050131275A
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Korean (ko)
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송정균
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

A method of fabricating a semiconductor device is provided to uniformly deposit an oxide on a substrate and thus uniform a thickness of an oxide layer by forming a pad oxide layer on the substrate through a CVD process. A semiconductor substrate having a phosphorous doping region(12) which is formed by implanting POCl3 in the substrate is prepared. A CVD process is performed on the substrate to form a pad oxide layer(13). A mask layer is formed on the pad oxide layer, and then the mask layer is patterned. A LOCOS(Local Oxidation Of Silicon)(16) is formed by using the patterned mask layer.

Description

반도체 소자의 제조 방법{Manufacturing method of semiconductor device}Manufacturing method of semiconductor device

도 1 내지 도 10은 본 발명에 따른 반도체 소자의 제조 방법을 순차적으로 보이는 도면들.1 to 10 are views sequentially showing a method of manufacturing a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10 : 반도체 기판 11 : 산화물 하드 마스크10 semiconductor substrate 11 oxide hard mask

12 : 인 도핑 영역 13 : 패드 산화층12 phosphorus doped region 13 pad oxide layer

14 : 질화물층 15 : 포토레지스트14 nitride layer 15 photoresist

16 : 로코스16: Locos

본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 더욱 상세히는, 로코스 구조가 형성된 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a locos structure.

일반적으로 반도체 소자에서는 로코스(local oxidation of silicon, LOCOS) 방법으로 소자를 격리시킨다. 로코스 방법은 선택 산화법(selective oxidation method)으로, 실리콘 표면의 필요한 부분만을 선택적으로 산화시켜, 소자를 분리시키는 방법이다.In general, in a semiconductor device, the device is isolated by a local oxidation of silicon (LOCOS) method. The LOCOS method is a selective oxidation method that selectively oxidizes only the necessary portion of the silicon surface to isolate the device.

일반적으로 고압(high voltage, HV) 소자에는 고압에서 안정적으로 구동하기 위하여 웰(well) 구조가 형성된다. 그리고, 깊은 질소이온 웰 구조를 형성하기 위하여, 두꺼운 산화물 하드 마스크(oxide hard mask)가 사용되고, 고온의 노(furnace)에서 POCl3 가스 주입으로 인 도핑(phosphorous doping)이 수행된다.In general, a well structure is formed in a high voltage (HV) device to stably operate at a high voltage. Then, in order to form a deep nitrogen ion well structure, a thick oxide hard mask is used, and phosphorous doping is performed by POCl 3 gas injection in a high temperature furnace.

이 후, 열 산화법에 의해 패드 산화층이 형성되고, 질화물 증착(nitride deposition)이 이루어진다. 그런 다음, 포토 리지스트 마스크가 형성되어, 노광/현상에 의해 질화물만 식각된다. 그런 다음, 노에서 고온 공정의 수행에 의해, 로코스가 형성된다.Thereafter, a pad oxide layer is formed by a thermal oxidation method, and nitride deposition is performed. Then, a photoresist mask is formed so that only nitride is etched by exposure / development. Then, by conducting a high temperature process in the furnace, locos are formed.

상기와 같은 종래의 로코스의 형성 방법에 의하면, 패드 산화층 형성을 위한 일반적인 노의 조건 하에서는, 인 도핑된 실리콘에 산화물이 제대로 형성되지 아니할 수 있다. 그러면, 깊은 질소이온 웰 영역은 질화물 식각 후 서브 실리콘이 손상되는 단점이 있다. According to the conventional method of forming a LOCOS as described above, under the conditions of a general furnace for forming a pad oxide layer, an oxide may not be properly formed in the phosphorus-doped silicon. Then, the deep nitrogen ion well region has a disadvantage in that the sub silicon is damaged after nitride etching.

본 발명은 로코스가 요구되는 구조의 제작 시에, 깊은 질소이온 웰 구조의 형성을 위해 도핑되는 부분에서 발생되는 손상이 방지될 수 있는 로코스의 형성 방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a locus, in which damage occurring at a portion doped to form a deep nitrogen ion well structure can be prevented in fabricating a structure requiring a locus.

본 발명에 따른 반도체 소자의 제조 방법은 반도체 기판을 마련하는 단계; 상기 반도체 기판 위에 화학 기상 증착(CVD)에 의해 패드 산화층을 형성하는 단계; 상기 패드 산화층 위에 마스크층을 형성하는 단계; 상기 마스크층을 패터닝하는 단계; 및 상기 패터닝된 마스크층을 이용하여 로코스를 형성하는 단계;를 포함한다.Method of manufacturing a semiconductor device according to the present invention comprises the steps of preparing a semiconductor substrate; Forming a pad oxide layer on the semiconductor substrate by chemical vapor deposition (CVD); Forming a mask layer on the pad oxide layer; Patterning the mask layer; And forming a LOCOS using the patterned mask layer.

본 발명에 따른 반도체 소자의 제조 방법에 의하면, 반도체 기판 위에 패드 산화층이 화학 기상 증착에 의해 형성되므로, 산화물이 균일하게 증착되어, 패드 산화층의 두께가 균일해질 수 있다. 따라서, 질화물 식각 시에 실리콘이 손상되는 현상이 방지될 수 있다.According to the method of manufacturing a semiconductor device according to the present invention, since the pad oxide layer is formed on the semiconductor substrate by chemical vapor deposition, the oxide is uniformly deposited, so that the thickness of the pad oxide layer can be uniform. Therefore, the phenomenon of damaging silicon during nitride etching can be prevented.

이하에서는 본 발명의 구체적인 실시예를 도면과 함께 상세히 설명한다. 그러나, 본 발명의 사상이 제시되는 실시예에 제한된다고 할 수 없으며, 또다른 구성요소의 추가, 변경, 삭제 등에 의해서, 퇴보적인 다른 발명이나 본 발명 사상의 범위 내에 포함되는 다른 실시예가 용이하게 제안될 수 있다.Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the spirit of the present invention is not limited to the embodiments presented, and other embodiments included within the scope of the present invention and other degenerate inventions are easily proposed by adding, changing, or deleting other elements. Can be.

도 1 내지 도 10은 본 발명에 따른 반도체 소자의 제조 방법을 순차적으로 보이는 도면들이다. 이하에서 도 1 내지 도 10을 참조하여, 본 발명에 따른 반도체 소자의 제조 방법을 설명한다.1 to 10 are views sequentially showing a method of manufacturing a semiconductor device according to the present invention. Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 1 to 10.

먼저, 도 1에 도시된 바와 같이, 반도체 기판(10)를 마련한다. 상기 반도체 기판(10)은 실리콘(Si)으로 이루어질 수 있다.First, as shown in FIG. 1, a semiconductor substrate 10 is prepared. The semiconductor substrate 10 may be made of silicon (Si).

그런 다음, 도 2에 도시된 바와 같이, 상기 반도체 기판(10) 위에 산화물 하드 마스크(11)를 형성한다. 상기 산화물 하드 마스크(11)에는 소정 패턴이 형성되어, 열린 부분과 닫힌 부분이 존재한다.Next, as shown in FIG. 2, an oxide hard mask 11 is formed on the semiconductor substrate 10. A predetermined pattern is formed on the oxide hard mask 11 so that an open portion and a closed portion exist.

그 후, 도 3에 도시된 바와 같이, 상기 산화물 하드 마스크(11)의 열린 부분 을 통해 POCl3를 주입한다. 그러면, 상기 반도체 기판(10) 중 상기 POCl3가 주입된 부분은 인 도핑 영역(12)이 된다.Thereafter, as shown in FIG. 3, POCl 3 is injected through the open portion of the oxide hard mask 11. Then, the portion of the semiconductor substrate 10 into which the POCl 3 is injected becomes the phosphorus doped region 12.

그런 다음, 도 4에 도시된 바와 같이, 상기 산화물 하드 마스크(11)를 제거한다. 그러면, 상기 인 도핑 영역(12)이 부분적으로 형성된 상기 반도체 기판(10)이 개방된다.Then, as shown in FIG. 4, the oxide hard mask 11 is removed. As a result, the semiconductor substrate 10 having the phosphorus doped region 12 partially formed is opened.

그 후, 도 5에 도시된 바와 같이, 상기 반도체 기판(10) 위에 패드 산화층(13)을 형성한다. 본 발명에서는, 상기 패드 산화층(13)이 화학 기상 증착(chemical vapor deposition, CVD)에 의해 형성된다. 그러면, 상기 인 도핑 영역(12) 위에도 산화물이 요구되는 두께만큼 형성될 수 있다. 따라서, 상기 인 도핑 영역(12)을 포함하여 상기 반도체 기판(10) 위에 상기 패드 산화층(13)이 균일하게 형성될 수 있다.Thereafter, as shown in FIG. 5, a pad oxide layer 13 is formed on the semiconductor substrate 10. In the present invention, the pad oxide layer 13 is formed by chemical vapor deposition (CVD). Then, oxides may be formed on the phosphorus doped region 12 to the required thickness. Therefore, the pad oxide layer 13 may be uniformly formed on the semiconductor substrate 10 including the phosphorus doped region 12.

그런 다음, 도 6에 도시된 바와 같이, 상기 패드 산화층(13) 위에 질화물층(14)을 형성한다. 상기 질화물층(14)은 질화물을 증착시킴으로써 형성될 수 있다. 이러한 질화물층(14)은 이후에 패터닝되어, 마스크층의 역할을 한다.6, a nitride layer 14 is formed on the pad oxide layer 13. The nitride layer 14 may be formed by depositing nitride. This nitride layer 14 is then patterned, acting as a mask layer.

그 후, 도 7에 도시된 바와 같이, 상기 질화물층(14) 위에 포토레지스트(photoresist)(15)를 형성한다.Thereafter, as shown in FIG. 7, a photoresist 15 is formed on the nitride layer 14.

그런 다음, 도 8에 도시된 바와 같이, 상기 포토레지스트(15)를 이용하여 노광/현상 공정을 거쳐, 상기 질화물층(14)을 패터닝한다. 이러한 질화물층(14)이 패터닝되는 과정에서, 상기 질화물층(14)과 상기 반도체 기판(10) 사이에는 상기 패 드 산화층(13)이 존재한다. 따라서, 상기 질화물층(14)의 식각에도 불구하고, 상기 반도체 기판(10)이 보호될 수 있다.Next, as shown in FIG. 8, the nitride layer 14 is patterned through the exposure / development process using the photoresist 15. In the process of patterning the nitride layer 14, the pad oxide layer 13 exists between the nitride layer 14 and the semiconductor substrate 10. Thus, despite the etching of the nitride layer 14, the semiconductor substrate 10 may be protected.

그 후, 도 9에 도시된 바와 같이, 상기 포토레지스트(15)를 제거한다.Thereafter, as shown in FIG. 9, the photoresist 15 is removed.

그런 다음, 도 10에 도시된 바와 같이, 노 내에서 고온 공정을 통하여 로코스(16)를 형성시킨다.Then, as shown in FIG. 10, the locus 16 is formed through a high temperature process in the furnace.

상기와 같이 구성되는 본 발명에 따른 반도체 소자의 제조 방법에 의하면, 반도체 기판 위에 패드 산화층이 화학 기상 증착에 의해 형성되므로, 산화물이 균일하게 증착되어, 패드 산화층의 두께가 균일해질 수 있다. 따라서, 질화물 식각 시에 실리콘이 손상되는 현상이 방지될 수 있는 효과가 있다.According to the method of manufacturing a semiconductor device according to the present invention configured as described above, since the pad oxide layer is formed by chemical vapor deposition on the semiconductor substrate, the oxide is uniformly deposited, the thickness of the pad oxide layer can be uniform. Therefore, there is an effect that the phenomenon of damaging the silicon during nitride etching can be prevented.

Claims (2)

인 도핑 영역이 포함된 반도체 기판이 마련되는 단계;Providing a semiconductor substrate including a phosphorus doped region; 상기 반도체 기판 위에 화학 기상 증착(CVD)에 의해 패드 산화층을 형성하는 단계;Forming a pad oxide layer on the semiconductor substrate by chemical vapor deposition (CVD); 상기 패드 산화층 위에 마스크층을 형성하는 단계;Forming a mask layer on the pad oxide layer; 상기 마스크층을 패터닝하는 단계; 및Patterning the mask layer; And 상기 패터닝된 마스크층을 이용하여 로코스를 형성하는 단계;를 포함하는 반도체 소자의 제조 방법.Forming a LOCOS using the patterned mask layer. 제 1 항에 있어서,The method of claim 1, 상기 인 도핑 영역은 POCl3가 주입되어 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.The phosphorus doped region is a method of manufacturing a semiconductor device, characterized in that formed by injection of POCl 3 .
KR1020050131275A 2005-12-28 2005-12-28 Manufacturing method of semiconductor device KR100726094B1 (en)

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KR19990051381A (en) * 1997-12-19 1999-07-05 윤종용 s. Five. Manufacturing method of the SOI element
JPH11274485A (en) 1998-03-25 1999-10-08 Nec Kansai Ltd Insulation gate type semiconductor device and its manufacturing method

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KR970023978A (en) * 1995-10-04 1997-05-30 김주용 Method for manufacturing planar device isolation film of semiconductor device
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JPH11274485A (en) 1998-03-25 1999-10-08 Nec Kansai Ltd Insulation gate type semiconductor device and its manufacturing method

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KR100835432B1 (en) * 2006-12-28 2008-06-04 동부일렉트로닉스 주식회사 Isolation method in a semiconductor manufacturing device

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