CN114899149B - Manufacturing method of semiconductor device and semiconductor structure - Google Patents
Manufacturing method of semiconductor device and semiconductor structure Download PDFInfo
- Publication number
- CN114899149B CN114899149B CN202210418608.0A CN202210418608A CN114899149B CN 114899149 B CN114899149 B CN 114899149B CN 202210418608 A CN202210418608 A CN 202210418608A CN 114899149 B CN114899149 B CN 114899149B
- Authority
- CN
- China
- Prior art keywords
- layer
- well region
- region
- semiconductor
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 28
- 150000002500 ions Chemical class 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 45
- 238000002955 isolation Methods 0.000 claims description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 26
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 229910021332 silicide Inorganic materials 0.000 claims description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 abstract 1
- 230000008569 process Effects 0.000 description 23
- 150000004767 nitrides Chemical class 0.000 description 22
- 238000010586 diagram Methods 0.000 description 21
- 239000000463 material Substances 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- -1 etc. Chemical compound 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000012459 cleaning agent Substances 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910019001 CoSi Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910010093 LiAlO Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 1
- 239000004327 boric acid Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- YQNQTEBHHUSESQ-UHFFFAOYSA-N lithium aluminate Chemical compound [Li+].[O-][Al]=O YQNQTEBHHUSESQ-UHFFFAOYSA-N 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The invention relates to the technical field of semiconductors, and provides a manufacturing method of a semiconductor device and a semiconductor structure, which comprises the following steps: providing a substrate; forming a semiconductor layer on a substrate; forming a dielectric layer on the semiconductor layer; forming a photoresist layer on the dielectric layer; implanting ions into the first well region by using the photoresist layer in the second well region as a mask to form a first doped region, and etching part of the dielectric layer to expose the first gate, the first doped region and part of the first well region; removing the photoresist layer in the second well region; implanting ions into the second well region by using the photoresist layer in the first well region as a mask to form a second doped region, and etching part of the dielectric layer to expose the second gate, the second doped region and the second well region; removing the photoresist layer in the first well region; and forming a capping layer on the exposed region of the semiconductor layer. The manufacturing method of the semiconductor device and the semiconductor structure provided by the invention reduce the preparation time of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor device and a semiconductor structure.
Background
In the manufacturing process of the semiconductor device, the metal silicide region can reduce the series resistance of a circuit and improve the performance of the circuit. Reference may be made to utility model patent publication No. CN 2731718Y. Forming the metal silicide region often requires depositing a barrier layer and then exposing the region where the metal silicide is to be formed by photolithographic etching. However, when the resistance of the resistor is high, the metal silicide of the semiconductor device affects the electrical performance of the device and is high in cost. Therefore, how to improve the electrical performance of the semiconductor device at high impedance and reduce the manufacturing cost has become a problem to be solved.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present application provides a method for manufacturing a semiconductor device and a semiconductor structure, which can improve the electrical performance of the semiconductor device at high impedance and reduce the manufacturing cost.
To achieve the above and other objects, the present application provides a method of manufacturing a semiconductor device, including:
providing a substrate;
forming a semiconductor layer on the substrate, wherein the semiconductor layer comprises a first well region, a second well region, a first grid electrode formed on the first well region and a second grid electrode formed on the second well region;
forming a dielectric layer on the semiconductor layer;
forming a photoresist layer on the dielectric layer;
implanting ions into the first well region by using the photoresist layer on the second well region as a mask to form a first doped region, and etching the dielectric layer to expose the first gate, the first doped region and the first well region;
removing the photoresist layer in the second well region;
implanting ions into the second well region by taking the photoresist layer on the first well region as a mask to form a second doped region, and etching the dielectric layer to expose the second gate, the second doped region and the second well region;
removing the photoresist layer on the first well region; and
a capping layer is formed on the exposed region of the semiconductor layer.
Optionally, the semiconductor layer further includes a first sidewall dielectric layer, a second sidewall dielectric layer, and a gate oxide layer, and the first sidewall dielectric layer and the second sidewall dielectric layer are located on the gate oxide layer.
Optionally, the thickness of the second sidewall dielectric layer is greater than the thickness of the first sidewall dielectric layer.
Optionally, the step of forming the semiconductor layer comprises: and forming an isolation trench structure on the substrate, wherein the isolation trench structure is positioned between the first well region and the second well region.
Optionally, an upper surface of the isolation trench structure is higher than upper surfaces of the first well region and the second well region.
Optionally, the capping layer is a metal silicide layer.
Optionally, the material of the dielectric layer is silicon dioxide.
Optionally, the step of forming the cover layer further comprises: and carrying out multiple times of annealing treatment on the semiconductor device so as to reserve metal silicide on the active region and the polysilicon gate region.
The present invention also provides a semiconductor structure comprising:
a substrate;
the semiconductor layer is positioned on the substrate and comprises a first well region, a second well region, a first grid electrode and a second grid electrode;
wherein the first gate is located over the first well region and the second gate is located over the second well region;
a dielectric layer on the semiconductor layer; and
a capping layer on the exposed region of the semiconductor layer.
Optionally, the capping layer is a metal silicide layer.
In summary, the present application provides a method for fabricating a semiconductor device and a semiconductor structure, in which a metal reacts with a polysilicon and an active region but does not react with a dielectric oxide or a nitride. The semiconductor device salicide block layer is designed and manufactured to meet the electrical performance requirements. The electrical performance of the semiconductor device at high impedance can be improved and the manufacturing cost can be reduced.
Drawings
Fig. 1 is a schematic view of a semiconductor device manufacturing method according to an embodiment of the present application.
Fig. 2 is a schematic diagram of an oxide layer according to an embodiment of the present application.
FIG. 3 is a schematic diagram of a patterned photoresist layer according to an embodiment of the present application.
Fig. 4 is a schematic diagram of an isolation trench in an embodiment of the present application.
FIG. 5 is a schematic view of an insulating medium according to an embodiment of the present application.
Fig. 6 is a schematic view of an isolation trench structure according to an embodiment of the present application.
Fig. 7 is a schematic diagram of a well structure in an embodiment of the present application.
FIG. 8 is a schematic diagram of a gate oxide layer according to an embodiment of the present application.
Fig. 9 is a schematic diagram of a polysilicon layer in an embodiment of the present application.
Fig. 10 is a first schematic view of a sidewall dielectric layer according to an embodiment of the present application.
Fig. 11 is a second schematic view of a sidewall dielectric layer according to an embodiment of the present application.
FIG. 12 is a schematic diagram of a gate in an embodiment of the present application.
FIG. 13 is a schematic diagram of a dielectric layer according to an embodiment of the present application.
FIG. 14 is a photoresist layer of the present application in one embodiment.
FIG. 15 is a first exemplary embodiment of an etching process.
FIG. 16 is a schematic view of a first doped region in an embodiment of the present application.
Fig. 17 is a second etching diagram in an embodiment of the present application.
Fig. 18 is a third schematic etching diagram in an embodiment of the present application.
FIG. 19 is a schematic view of a second doped region in an embodiment of the present application.
FIG. 20 is a schematic view of a doped region of the present application in one embodiment.
Fig. 21 is a first schematic view of a cover layer according to an embodiment of the present disclosure.
Fig. 22 is a second illustration of a cover layer according to an embodiment of the present application.
Description of reference numerals:
100. a substrate;
101. an oxide layer;
102. a nitride layer;
103. patterning the photoresist layer;
110. a first isolation trench;
111. a second isolation trench;
112. a third isolation trench;
113. an insulating medium;
120. a first isolation trench structure;
121. a second isolation trench structure;
122. a third isolation trench structure;
130. a first well region;
131. a second well region;
141. a first gate electrode;
142. a second gate electrode;
210. a gate oxide layer;
220. a polysilicon layer;
230. a first sidewall dielectric layer;
240. a second sidewall dielectric layer;
310. a dielectric layer;
320. a photoresist layer;
410. a first doped region;
420. a second doped region;
500. and (4) a covering layer.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The application provides a manufacturing method of a semiconductor device and a semiconductor structure, and designs and manufactures a self-aligned silicide barrier layer of the semiconductor device so as to meet the requirement of electrical performance. The electrical performance of the semiconductor device at high impedance can be improved and the manufacturing cost can be reduced.
Referring to fig. 1, fig. 1 is a schematic view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. The present application provides a method for manufacturing a semiconductor device, which in this embodiment may include the steps of:
s1, providing a substrate.
And S2, forming a semiconductor layer on the substrate, wherein the semiconductor layer comprises a first well region, a second well region, a first grid electrode formed on the first well region and a second grid electrode formed on the second well region.
And S3, forming a dielectric layer on the semiconductor layer.
And S4, forming a photoresist layer on the dielectric layer.
And S5, implanting ions into the first well region by taking the photoresist layer on the second well region as a mask to form a first doped region, and etching part of the dielectric layer to expose the first grid electrode, the first doped region and part of the first well region.
And S6, removing the photoresist layer in the second well region.
S7, implanting ions into the second well region by taking the photoresist layer on the first well region as a mask to form a second doped region, and etching part of the dielectric layer to expose the second grid electrode, the second doped region and the second well region.
S8, removing the photoresist layer in the first well region.
And S9, forming a covering layer on the exposed area of the semiconductor layer.
Referring to fig. 2, fig. 2 is a schematic diagram of an oxide layer according to an embodiment of the present disclosure. In an embodiment of the present application, the substrate 100 is, for example, a silicon substrate for forming a semiconductor structure. The substrate 100 may include a base material, such as a semiconductor substrate material of silicon (Si), silicon carbide (SiC), sapphire ((Al 2O 3), gallium arsenide (GaAs), lithium aluminate (LiAlO 2), etc., and a silicon layer disposed over the base material, the silicon layer being formed over the base material.
Referring to fig. 2, in one embodiment of the present invention, an oxide layer 101 is formed on a substrate 100. The oxide layer 101 is, for example, a dense silicon oxide or the like, and the oxide layer 101 may be formed on the substrate 100 by a thermal oxidation method, an in-situ water vapor growth method, a chemical vapor deposition method, or the like. In this embodiment, the substrate 100 is placed in a furnace tube at a temperature of, for example, 900 ℃ to 1150 ℃, oxygen is introduced, and the substrate 100 reacts with the oxygen at a high temperature to form the dense oxide layer 101. The thickness of the oxide layer 101 is, for example, 10 to 50nm, specifically, 30nm, 40nm, 45nm, 50nm, or the like.
Referring to fig. 2, in an embodiment of the present invention, a nitride layer 102 may be formed on an oxide layer 101. The nitride layer 102 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide. The oxide layer 101 serves as a buffer layer to improve the stress between the substrate 100 and the nitride layer 102. In the present application, the nitride layer 102 may be formed on the oxide layer 101 by, for example, a Low Pressure Chemical Vapor Deposition (LPCVD) method. In some embodiments, the substrate 100 with the oxide layer 101 may be placed in a furnace filled with dichlorosilane and ammonia gas, and reacted at a pressure ranging from, for example, 2 to 10t and a temperature ranging from, for example, 700 to 800 ℃ to deposit the nitride layer 102. In addition, the thickness of the nitride layer 102 can be adjusted by controlling the heating time. In some embodiments, the nitride layer 102 has a thickness of, for example, 50nm to 200nm, specifically, for example, 60nm, 75nm, 80nm, 100nm, 150nm, 180nm, or 200 nm. The nitride layer 102 may protect the substrate 100 from a Chemical Mechanical Polishing (CMP) process involved in the manufacturing process of the sti structure. The nitride layer 102 may be used as a mask during the shallow trench formation process, and when the substrate 10 is etched, the substrate 10 at other positions is protected from damage.
Referring to fig. 3-5, fig. 3 is a schematic diagram illustrating a patterned photoresist layer according to an embodiment of the present application. Fig. 4 is a schematic view of an isolation trench according to an embodiment of the present application. FIG. 5 is a schematic view of an insulating medium according to an embodiment of the present application. In one embodiment of the present application, a photoresist layer may be formed on the nitride layer 102 by, for example, a spin coating process, and a photoresist pattern may be formed on the photoresist layer by exposure and development processes, and the photoresist pattern is used to locate the shallow trench. After the substrate 100 is etched quantitatively, the photoresist layer is removed to form a first isolation trench 110, a second isolation trench 111, and a third isolation trench 112.
Referring to fig. 3-4, in an embodiment of the present invention, a first isolation trench 110, a second isolation trench 111, and a third isolation trench 112 are sequentially disposed side by side on a substrate 100. A first patterned photoresist layer 103 is obtained on the nitride layer 102, which first patterned photoresist layer 103 may be used to define the location of the trench region. After the first patterned photoresist layer 103 is formed, the nitride layer 102, the oxide layer 101 and a portion of the substrate 100 under the photolithography pattern are quantitatively removed by, for example, dry etching using the first patterned photoresist layer 103 as a mask. After the etching, the first patterned photoresist layer 103 is removed to form a first isolation trench 110, a second isolation trench 111 and a third isolation trench 112.
Referring to fig. 3-5, in an embodiment of the present invention, an insulating dielectric 113 is deposited in the first isolation trench 110, the second isolation trench 111 and the third isolation trench 112. The insulating dielectric 113 may be formed by High Density Plasma CVD (HDP-CVD) or High Aspect Ratio CVD (HARP-CVD), for example. After the insulating medium 113 is deposited, a high temperature (e.g., 800 to 1200 ℃) tempering process may be performed to increase the density and stress of the insulating medium 113. The insulating medium 113 is, for example, silicon oxide having high adaptability to a grinding tool, and in other embodiments, the insulating medium 113 may also be an insulating material such as fluorosilicate glass.
Referring to fig. 5 and 6, fig. 6 is a schematic view of an isolation trench structure according to an embodiment of the present application. In an embodiment of the present application, after the insulating medium 113 is prepared, the insulating medium 113 is planarized. The insulating dielectric 113 and a portion of the nitride layer 102 are planarized, for example, using a Chemical Mechanical Polishing (CMP) process, to achieve a uniform height between the insulating dielectric 113 and the nitride layer 102. The polished nitride layer 102 is then etched and removed, but the method for removing the nitride layer 102 is not limited in this application, and for example, dry etching or wet etching is used. By selecting a larger hot phosphoric acid as an etching liquid for etching the nitride layer 102 and the oxide layer 101, the nitride layer 102 is removed to form a first isolation trench structure 120, a second isolation trench structure 121, and a third isolation trench structure 122. After the nitride layer 102 is removed, an isolation trench step height is formed between the first, second and third isolation trench structures 120, 121 and 122 and the oxide layer 101. In different embodiments, the step height requirements are different, and the step height can be adjusted by etching.
Referring to fig. 6 and 7, fig. 7 is a schematic diagram illustrating a well structure according to an embodiment of the present invention. In one embodiment of the present application, after the isolation trench structure is formed, the substrate 100 is ion implanted to form different well regions. I.e., active regions are formed by isolating the trench structures and then different types of ion doping are performed on the active regions to form the first well region 130 and the second well region 131. In this embodiment, the first well region 130 may be formed by doping an active region with, for example, P-type ions, where the first well region 130 is, for example, a P-type well region, and the doping ions are boron (B) or gallium (Ga). The second well region 131 may be formed by doping the active region with, for example, N-type ions, the second well region 131 is, for example, an N-type well region, and the doping ions are phosphorus (P) or arsenic (As).
Referring to fig. 7 and 8, fig. 8 is a schematic diagram of a gate oxide layer according to an embodiment of the present disclosure. In an embodiment of the present application, after the first well region 130 and the second well region 131 are formed, the oxide layer 101 on the surface of the well regions is removed, for example, by dry etching or wet etching. The gate oxide layer 210 is formed on the surface of the shallow trench structure, which is the well region, and the formation method of the gate oxide layer 210 is not limited in this application, and for example, the gate oxide layer is formed by using a chemical vapor deposition method or a physical vapor deposition method. In the present embodiment, the gate oxide layer 210 is formed by, for example, an In-situ steam Generation (ISSG) method, wherein the material of the gate oxide layer 210 is, for example, silicon oxide. In other embodiments of the present application, the thickness of the gate oxide layer 210 can be set according to actual requirements. The gate oxide layer 210 is inevitably scratched in the shallow trench forming process, and the gate oxide layer 210 can be rearranged to ensure the flatness and defect rate of the gate oxide layer 210 and improve the breakdown and leakage phenomena of the lateral insulated gate bipolar transistor.
Referring to fig. 8 and 9, fig. 9 is a schematic diagram of a polysilicon layer in an embodiment of the present application. In an embodiment of the present invention, a photoresist is formed on the gate oxide layer 210, and then the photoresist is exposed and developed to form a patterned photoresist layer (not shown). The gate oxide layer 210 is then etched by, for example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process. In this embodiment, for example, the gate oxide layer 210 is sequentially anisotropically etched by using a dry etching process, and the substrate 100 may serve as an etching stop layer of the gate oxide layer 210.
Referring to fig. 9, in an embodiment of the present invention, a polysilicon layer 220 is deposited on the gate oxide layer 210. The polysilicon layer 220 may be P-type or N-type, and the doping type of the polysilicon layer 220 is different from that of the substrate 100. In some embodiments of the present application, the thickness of the polysilicon layer 220 may be set according to actual requirements. A photoresist is formed on the polysilicon layer 220, and then the photoresist is exposed and developed to form a patterned photoresist layer (not shown). The polysilicon layer 220 is then etched by, for example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process. In the present embodiment, the polysilicon layer 220 is sequentially anisotropically etched by, for example, a dry etching process, and the gate oxide layer 210 may serve as an etch stop layer for the polysilicon layer 220.
Referring to fig. 10-12, fig. 10 is a first schematic view of a sidewall dielectric layer according to an embodiment of the present application. Fig. 11 is a schematic view of a second sidewall dielectric layer according to an embodiment of the present application. FIG. 12 is a schematic diagram of a gate in an embodiment of the present application. In an embodiment of the present invention, after forming the polysilicon layer 220 and the gate oxide layer 210, a first sidewall dielectric layer 230 is formed on the polysilicon layer 220, the gate oxide layer 210, each well region, and the isolation trench structure, and the material of the first sidewall dielectric layer 230 is, for example, silicon oxide, silicon nitride, or a stacked layer of silicon oxide and silicon nitride. After the first sidewall dielectric layer 230 is formed, for example, an etching process such as a photolithography-etching process may be used to remove the polysilicon layer 220, the gate oxide layer 210, the isolation trench structure, and the first sidewall dielectric layer 230 on each well region, and the first sidewall dielectric layer 230 on the gate oxide layer 210 and on both sides of the polysilicon layer 210 is remained. The height of the first sidewall dielectric layer 230 may be the same as the height of the polysilicon layer 220, and the width of the first sidewall dielectric layer 230 gradually increases from the top to the bottom of the polysilicon layer 220. By arranging the first sidewall dielectric layer 230, the prepared lateral insulated gate bipolar transistor can be prevented from generating a leakage phenomenon. In this embodiment, the shape of the first sidewall dielectric layer 230 is, for example, an arc shape, and in other embodiments, the shape of the first sidewall dielectric layer 230 may also be a triangular shape or an L shape. After the first sidewall dielectric layer 230 is formed, a second sidewall dielectric layer 240 may also be formed on the semiconductor upper surface. After forming the second sidewall dielectric layer 240, for example, an etching process such as a photolithography-etching process may be used to remove the polysilicon layer 220, the gate oxide layer 210, the isolation trench structure, and the second sidewall dielectric layer 240 on each well region, and the second sidewall dielectric layers 240 on both sides of the polysilicon layer 210 and on the gate oxide layer 210 are remained. Thereby forming the first gate electrode 141 and the second gate electrode 142.
Referring to fig. 13, fig. 13 is a schematic diagram of a dielectric layer according to an embodiment of the present application. In an embodiment of the present invention, a dielectric layer 310 may be formed on a semiconductor layer. An oxide layer is deposited prior to ion implantation. In the present embodiment, an oxide may be formed by CVD (Chemical Vapor Deposition) as a dielectric material of the dielectric layer 310, for example, silicon dioxide.
Referring to fig. 14, fig. 14 is a schematic diagram of a photoresist layer according to an embodiment of the present application. In one embodiment, a photoresist layer 320 may be formed on the dielectric layer 310. In this embodiment, the photoresist layer 320 may be formed by spin coating a photoresist on the upper surface of the semiconductor device. The photoresist layer 320 may be cleaned by developing and exposing, so as to etch in the subsequent process. A cleaning agent may be used in cleaning the photoresist in the photoresist layer 320, and in some embodiments of the present application, the cleaning agent may be, for example, a mixed solution including alcohol amine, boric acid, and derivatives thereof.
Referring to fig. 8 and 15-17, fig. 15 is a first schematic etching diagram according to an embodiment of the present application. FIG. 16 is a schematic view of a first doped region in an embodiment of the present application. In an embodiment of the present application, fig. 17 is a schematic etching diagram of a second embodiment of the present application. In an embodiment of the present invention, ions are implanted into the first well 130 by using the photoresist layer 320 over the second well 131 as a mask. The first doped region 410 is formed, a portion of the dielectric layer 310 is etched to expose the first gate 141, the first doped region 410 and a portion of the first well 130, and the photoresist layer 320 in the second well 131 is removed. In this embodiment, the previously deposited oxide layer is continuously etched by etching while the N-type ion implanted photoresist is not pulled out. And after etching, injecting N-type ions and removing the photoresist. In some embodiments of the present application, the ions doped in the first doping region 410 may also be ions of phosphorus element, boron element or other elements.
Referring to fig. 8 and 18-20, fig. 18 is a third etching schematic diagram in an embodiment of the present application. FIG. 19 is a schematic view of a second doped region in an embodiment of the present application. In an embodiment of the present application. FIG. 20 is a schematic view of a doped region of the present application in one embodiment. In an embodiment of the present invention, the photoresist layer 320 over the first well 130 is used as a mask to implant ions into the second well 131 to form the second doped region 420, and a portion of the dielectric layer 310 is etched to expose the second gate 142, the second doped region 420 and the second well 131, and the photoresist layer 320 in the first well 130 is removed. And (4) annealing treatment, repairing crystal damage on the silicon surface caused by N + ion injection, recovering a lattice structure and activating arsenic ions. Exposing and developing the photomask before P-type ion implantation to form photoresist, and implanting P-type boron dioxide ions. And etching the oxide layer deposited before under the P-type photomask layer under the condition of keeping the photoresist injected by the P-type ions not to be pulled out, and removing the P-type photoresist after the etching is finished.
Referring to fig. 21 and 22, fig. 21 is a schematic view of a first cladding layer according to an embodiment of the present application. Fig. 22 is a second illustration of a cover layer according to an embodiment of the present application. In an embodiment of the present application, the capping layer 500 may be formed on the exposed region of the semiconductor layer. The material of the capping layer 500 may be, for example, metallic cobalt, and the thickness of the capping layer 500 may be, for example, in the range of 10-20nm. After the first rapid thermal anneal in a nitrogen atmosphere, the metal in contact with the substrate silicon and the polysilicon reacts to form a metal silicide, which may be, for example, co 2 And (3) Si. In this embodiment, the annealing temperature range of the first rapid thermal annealing may be 400 to 550 ℃. And performing second rapid thermal annealing in a high-temperature nitrogen atmosphere, and reserving metal silicide on the active region and the polysilicon gate region. In the present embodiment, the annealing temperature range of the second rapid thermal annealing may be, for example, 650 to 750 ℃. At this time, co in a high resistance state 2 CoSi with Si converted to low-resistance state 2 。
Referring to fig. 8-22, a semiconductor structure is also provided, which may include a substrate, a semiconductor layer, a dielectric layer and a capping layer in an embodiment of the present application. In an embodiment of the present application, a semiconductor layer is located on the substrate 100, and the semiconductor layer may include the first well region 130 and the second well region 131, and the first gate 141 and the second gate 142. In an embodiment of the present application, the first gate 141 is located on the first well region 130, and the second gate 142 is located on the second well region 131. The dielectric layer 310 may be on the semiconductor layer, and the capping layer 500 may be on an exposed region of the semiconductor layer.
In summary, the present application provides a method for manufacturing a semiconductor device and a semiconductor structure, in which a metal reacts with a polysilicon and an active region but does not react with a dielectric oxide or a nitride. The semiconductor device self-aligned silicide barrier layer is designed and manufactured to meet the electrical performance requirements. The electrical performance of the semiconductor device at high impedance can be improved and the manufacturing cost can be reduced.
The above description of illustrated embodiments of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As indicated, these modifications may be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.
The systems and methods have been described herein in general terms as the details aid in understanding the invention. Furthermore, various specific details have been set forth in order to provide a thorough understanding of the embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the present invention.
Thus, although the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Thus, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the invention is to be determined solely by the appended claims.
The above description is only a preferred embodiment of the present application and a description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application. Besides the technical features described in the specification, other technical features are known to those skilled in the art, and are not described in detail herein in order to highlight the innovative features of the present invention.
Claims (7)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a semiconductor layer on the substrate, wherein the semiconductor layer comprises a first well region, a second well region, a first grid electrode formed on the first well region and a second grid electrode formed on the second well region;
forming a dielectric layer on the semiconductor layer;
forming a photoresist layer on the dielectric layer;
implanting ions into the first well region by taking the photoresist layer on the second well region as a mask to form a first doped region, and etching the dielectric layer to expose the first gate, the first doped region and the first well region;
removing the photoresist layer in the second well region;
implanting ions into the second well region by taking the photoresist layer on the first well region as a mask to form a second doped region, and etching the dielectric layer to expose the second gate, the second doped region and the second well region;
removing the photoresist layer on the first well region;
annealing the semiconductor device and forming a covering layer on the exposed region of the semiconductor layer, wherein the covering layer is a metal silicide layer; and
and carrying out multiple times of annealing treatment on the semiconductor device, and reserving metal silicide on the active region and the polysilicon gate region.
2. A method for manufacturing a semiconductor device according to claim 1, wherein: the semiconductor layer further comprises a first side wall dielectric layer, a second side wall dielectric layer and a grid oxide layer, and the first side wall dielectric layer and the second side wall dielectric layer are located on the grid oxide layer.
3. A method for manufacturing a semiconductor device according to claim 2, wherein: the thickness of the second side wall dielectric layer is larger than that of the first side wall dielectric layer.
4. A method for manufacturing a semiconductor device according to claim 1, wherein: the step of forming the semiconductor layer includes: and forming an isolation trench structure on the substrate, wherein the isolation trench structure is positioned between the first well region and the second well region.
5. A method for manufacturing a semiconductor device according to claim 4, wherein: the upper surface of the isolation trench structure is higher than the upper surfaces of the first well region and the second well region.
6. A method for manufacturing a semiconductor device according to claim 1, wherein: the dielectric layer is made of silicon dioxide.
7. A semiconductor structure, comprising:
a substrate;
the semiconductor layer is positioned on the substrate and comprises a first well region, a second well region, a first grid electrode and a second grid electrode;
wherein the first gate is located on the first well region, and the second gate is located on the second well region;
a dielectric layer on the semiconductor layer; and
the covering layer is located on the exposed area of the semiconductor layer, the covering layer is a metal silicide layer and comprises metal silicide, and the metal silicide is located on the active area and the polycrystalline silicon gate area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210418608.0A CN114899149B (en) | 2022-04-21 | 2022-04-21 | Manufacturing method of semiconductor device and semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210418608.0A CN114899149B (en) | 2022-04-21 | 2022-04-21 | Manufacturing method of semiconductor device and semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114899149A CN114899149A (en) | 2022-08-12 |
| CN114899149B true CN114899149B (en) | 2022-10-11 |
Family
ID=82717843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210418608.0A Active CN114899149B (en) | 2022-04-21 | 2022-04-21 | Manufacturing method of semiconductor device and semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114899149B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116206980A (en) * | 2023-04-28 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN116779615B (en) * | 2023-08-23 | 2023-11-07 | 合肥晶合集成电路股份有限公司 | Integrated semiconductor device and manufacturing method thereof |
| CN116936476B (en) * | 2023-09-15 | 2023-12-26 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211781A (en) * | 2006-12-28 | 2008-07-02 | 中芯国际集成电路制造(上海)有限公司 | Self-aligning metal silicide preparation method |
| CN101276830A (en) * | 2007-03-30 | 2008-10-01 | 索尼株式会社 | Solid-state imaging element and method for producing the same |
| CN102779790A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Method for manufacturing semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01214173A (en) * | 1988-02-23 | 1989-08-28 | Sony Corp | Manufacture of mos transistor |
-
2022
- 2022-04-21 CN CN202210418608.0A patent/CN114899149B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211781A (en) * | 2006-12-28 | 2008-07-02 | 中芯国际集成电路制造(上海)有限公司 | Self-aligning metal silicide preparation method |
| CN101276830A (en) * | 2007-03-30 | 2008-10-01 | 索尼株式会社 | Solid-state imaging element and method for producing the same |
| CN102779790A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114899149A (en) | 2022-08-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114899149B (en) | Manufacturing method of semiconductor device and semiconductor structure | |
| EP0515809A2 (en) | Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization | |
| US20070128776A1 (en) | Isolated fully depleted silicon-on-insulator regions by selective etch | |
| US20060121660A1 (en) | Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same | |
| US9953878B2 (en) | Method of forming a semiconductor device | |
| TWI260732B (en) | Method of self-aligning a damascene gate structure to isolation regions | |
| JP2006310717A (en) | Semiconductor element using solid phase epitaxy system and its manufacturing method | |
| CN115020343B (en) | Method for manufacturing semiconductor device | |
| US20020019102A1 (en) | Process to fabricate a novel source-drain extension | |
| US20030230779A1 (en) | Semiconductor device and method for manufacturing the same | |
| KR100529395B1 (en) | Semiconductor device having contact plug formed of dual epitaxial layer and method for fabricating the same | |
| US7407871B2 (en) | Method for passivation of plasma etch defects in DRAM devices | |
| JP3654285B2 (en) | Manufacturing method of semiconductor device | |
| US9159604B2 (en) | Semiconductor device and method for forming the same | |
| KR100821494B1 (en) | Process for the fabrication of dual gate structures for CMOS devices | |
| CN115101477B (en) | Semiconductor structure and manufacturing method thereof | |
| JP2004165470A (en) | Semiconductor device and its manufacturing method | |
| CN107464741A (en) | A kind of semiconductor devices and its manufacture method, electronic installation | |
| JP4070876B2 (en) | Manufacturing method of CMOS circuit | |
| US20150187756A1 (en) | Semiconductor device with metal silicide blocking region and method of manufacturing the same | |
| CN104851802B (en) | A kind of semiconductor devices and preparation method thereof | |
| KR100639464B1 (en) | Semiconductor device and method of fabricating thereof | |
| US7259053B2 (en) | Methods for forming a device isolation structure in a semiconductor device | |
| US11984362B1 (en) | Control of locos structure thickness without a mask | |
| TW468200B (en) | Manufacturing method of semiconductor device with high isolation technique |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |