KR100717320B1 - Electro-luminescence Display Device And Fabricating Method Of Thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro luminescence display device capable of preventing image degradation caused by line resistance of a common line and a method of manufacturing the same.

An electroluminescent display device according to the present invention comprises: a substrate on which an electroluminescent cell array is formed; A packaging plate bonded to the substrate by a bonding agent to face the electroluminescent cell array; It characterized in that it comprises a signal line for supplying a drive signal to the electroluminescent cell array and having a hole formed to extend to the region where the binder is formed, and to supply a drive signal.

Description

Electroluminescence Display Device and Manufacturing Method Thereof {Electro-luminescence Display Device And Fabricating Method Of Thereof}             

1 is a plan view showing a conventional electro luminescence display element.

2 is a plan view illustrating an electro luminescence display device according to another exemplary embodiment.

3A and 3B are plan views illustrating in detail the common line illustrated in FIGS. 1 and 2.

4 is a plan view illustrating an electro luminescence display device according to a first embodiment of the present invention.

5 is a plan view illustrating in detail the common line illustrated in FIG. 4.

FIG. 6 is a cross-sectional view illustrating an electroluminescence display element taken along the line "I-I '" in FIG. 4.

7 is a plan view illustrating an electro luminescence display device according to a second exemplary embodiment of the present invention.

8A and 8B are plan views illustrating various types of common lines according to first and second exemplary embodiments of the present invention.

<Explanation of symbols for main parts of drawing>

2,102: gate pad 4,104: supply pad

6,106: data pad 10: sub-pixel

101: substrate 111: packaging plate

120: sealant 130,132: common pattern

134: hall

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro luminescence display device, and more particularly, to an electro luminescence display device and a method of manufacturing the same which can prevent image quality degradation due to line resistance of a common line.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have been developed. Such flat panel display devices include Liquid Crystal Display (LCD), Field Emission Display (FED) Plasma Display Panel (PDP) and Electro-luminescence (hereinafter EL). And display devices. In order to improve the display quality of such a flat panel display device and to attempt to make a large screen, there are active researches.

Among them, PDP is attracting attention as a display device which is lightest and most advantageous for large screen because of its simple structure and manufacturing process. However, PDP has low luminous efficiency, low luminance and high power consumption. On the other hand, LCDs with thin film transistors (hereinafter referred to as "TFTs") as switching elements have difficulty in large screens because they use a semiconductor process, but demand is increasing as they are mainly used as display elements of notebook computers. However, LCDs are difficult to make large areas and consume large power consumption due to the backlight unit. In addition, the LCD has a large optical loss and a narrow viewing angle by optical elements such as a polarizing filter, a prism sheet, and a diffusion plate.

In contrast, EL display elements are classified into inorganic ELs and organic ELs depending on the material of the light emitting layer. The EL display elements are self-luminous elements that emit light by themselves and have advantages such as fast response speed and high luminous efficiency, luminance, and viewing angle.

As illustrated in FIG. 1, the organic EL display device includes subpixels 10 arranged in regions defined by intersections of the gate line GL and the data line DL. Each of the subpixels 10 is generated by the data integrated circuit (not shown) when the gate pulse generated by the gate integrated circuit (not shown) is supplied to the gate line GL through the gate pad 2. The data signal supplied to the data line DL is supplied through the pad 6 to generate light corresponding to the data signal.

To this end, each of the subpixels 10 is connected to an EL cell 0EL having a cathode connected to a base voltage source GND, a gate line GL, a data line DL, and a power supply line VDL. A switching thin film transistor T1, a driving thin film transistor T2 and a capacitor C for connecting to the anode of the cell OEL and driving the EL cell OEL are provided.

When the scan pulse is supplied to the gate line GL, the switching thin film transistor T1 is turned on to supply a data signal supplied to the data line DL to the node N. The data signal supplied to the node N is charged to the capacitor C and supplied to the gate terminal of the driving thin film transistor T2. The driving thin film transistor T2 is generated from a supply voltage source in response to a data signal supplied to a gate terminal, and is supplied to the EL cell OEL from the supply pad 4, the common line CL, and the power supply line VDL. By controlling the amount of current I, the amount of light emitted by the EL cell OEL is adjusted. Since the data signal is discharged from the capacitor C even when the switching thin film transistor T1 is turned off, the driving thin film transistor T2 has a current I from the supply voltage source until the data signal of the next frame is supplied. Is supplied to the EL cell OEL so that the EL cell OEL maintains light emission.

The organic EL element shown in FIG. 1 supplies a supply voltage to each of the power supply lines VDL1 to VDLm through a common line CL connected to the supply pad 4. At this time, the level of the supply voltage supplied to the start point of the power supply line VDL close to the common line CL and the end point of the power supply line VDL far from the common line CL is different, resulting in deterioration in image quality. This is because the line resistance included in the power supply line VDL increases from the start point to the end point.

2 illustrates an organic EL device having first and second common lines CL1 and CL2 positioned at both sides of a substrate.

The first common line CL1 is connected to the first supply pad 4a adjacent to the gate pad 2 connected to the first gate line GL1, and the second common line CL2 is connected to the nth gate line GLn. Is connected to the second supply pad 4b adjacent to the gate pad 2 connected thereto. The first to m th power supply lines VDL1 to VDLm are connected to each of the first and second common lines CL1 and CL2 between the first and second common lines CL1 and CL2. In this case, the supply voltage levels supplied to the start point and the end point of the power supply line VDL by the first and second common lines CL1 and CL2 are equal to each other to prevent deterioration in image quality.

However, as the common line CL of the organic EL device illustrated in FIGS. 1 and 2 increases away from the supply pad 4, the common line CL having a predetermined length V1 as shown in FIGS. 3A and 3B. ), The line resistance (a, b, c, ...) included in the circuit increases, which causes the supply voltage level to be distorted. To solve this problem, the total area of the common line CL is widened to prevent supply voltage drops. However, when the width H1 of the common line CL is made constant and the length V1 of the common line CL is made long, the panel becomes large in the longitudinal direction, and the length V1 of the common line CL is made constant. When the width H1 is widened, the panel becomes larger in the width direction. On the other hand, when the supply line drop is prevented by increasing the length or width of the common line CL as much as possible without changing the size of the panel, there is a problem in that the process margin area of the sealant applied to bond the substrate and the packaging plate is reduced. .

Accordingly, it is an object of the present invention to provide an electro luminescence display device and a method of manufacturing the same which can prevent image quality deterioration due to line resistance of a common line.

In order to achieve the above object, the electroluminescent display device according to the present invention comprises a substrate on which an electroluminescent cell array is formed; A packaging plate bonded to the substrate by a bonding agent to face the electroluminescent cell array; It characterized in that it comprises a signal line for supplying a drive signal to the electroluminescent cell array and having a hole formed to extend to the region where the binder is formed, and to supply a drive signal.

The hole of the signal line is formed in an area overlapping with the binder.

The holes may be formed of a plurality of groups, and the holes may be spaced apart from each other in a region overlapping the adhesive.

The signal line is formed on one side of the substrate.

The signal line is formed on both sides of the substrate.

The electroluminescent cell array includes a gate line; A data line crossing the gate line; A supply line to which a driving signal is supplied through the signal line; First and second thin film transistors connected to the gate line, the data line, and the power supply line; And an electroluminescent cell connected to the second thin film transistor.

In order to achieve the above object, the electroluminescent cell array formed substrate according to the present invention; A method of manufacturing an electroluminescence display device in which a packaging plate facing the electroluminescent cell array is formed by bonding with a bonding agent has a hole that supplies a driving signal to the electroluminescent cell array and extends to an area where the bonding agent is formed. And forming a signal line for supplying a driving signal.

The hole of the signal line is formed in an area overlapping with the binder.

The signal line is formed on one side of the substrate.

The signal line is formed on both sides of the substrate.

Other objects and features of the present invention in addition to the above objects will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 8B.

4 is a plan view of an organic EL device according to a first exemplary embodiment of the present invention.

Referring to FIG. 4, an organic EL device according to a first exemplary embodiment of the present invention includes a light emitting region, a gate pad 102 for supplying a gate signal to a gate line GL of a light emitting region, and a data line of a light emitting region. The data pad 106 for supplying a data signal to the DL, the common line CL commonly connected to each of the power supply lines VDL in the light emitting area, and supplying a supply voltage to the common line CL. It is provided with a supply pad 104 for.

As illustrated in FIG. 1, the light emitting area includes a plurality of sub-pixels 10 arranged in regions defined by intersections of the gate line GL and the data line DL. Each of the subpixels 10 is generated by the data integrated circuit (not shown) when the gate pulse generated by the gate integrated circuit (not shown) is supplied to the gate line GL through the gate pad 102. The pad 106 receives the data signal supplied to the data line DL and generates light corresponding to the data signal.

For this purpose, each of the subpixels 10 is connected to an EL cell 0EL having a cathode connected to a base voltage source GND, a gate line GL, a data line DL, and a supply voltage source VDD, and is connected to an EL cell. A switching thin film transistor T1, a driving thin film transistor T2 and a capacitor C for connecting to the anode of the (OEL) and driving the EL cell OEL are provided.

The gate pad 102 supplies the scan pulse generated by the gate integrated circuit to the gate line GL to turn on the switching thin film transistor T1.

The data pad 106 supplies a data signal generated by the data integrated circuit to the data line DL, and the data signal is charged to the capacitor C and supplied to the gate terminal of the driving thin film transistor T2.

The supply pad 104 supplies a supply voltage to the power supply line VDL through the common line CL. This supply voltage is supplied to the anode of the EL cell through the driving thin film transistor T2 turned on in response to the data signal.

Meanwhile, the common line CL supplies the supply voltage supplied through the supply pad 104 to each of the power supply lines VDL1 to VDLm. To this end, the common line CL includes a first common pattern 130 and a second common pattern 132 connected to the first common pattern 130 and overlapping the sealant 120.

As shown in FIG. 5, the first common pattern 130 is formed to have the same first width H1 and the same length V1 as compared to the common line illustrated in FIG. 3A.

The second common pattern 132 is formed to have a second width H2 in an area overlapping the sealant 120 and has a plurality of holes 134 penetrating through the second common pattern 132. As shown in FIG. 6, the holes 134 pass through ultraviolet rays (UV) irradiated from the rear surface of the substrate 101 to cure the sealant 120 used when the substrate 101 and the packaging plate 111 are bonded together. Let's do it. That is, ultraviolet light UV passing through the second common pattern 132 through the hole 134 is irradiated to the sealant 120 to cure the sealant 120.

Due to the second common pattern 132, the area of the common line CL is increased. As a result, the line resistance values a ≒ b ≒ c ≒ d of the common line CL positioned in a region close to the supply pad 104 or in a region far from the supply pad 104 become similar to each other to form the common line CL. Through this, the level of each supply voltage supplied to the first to m th power supply lines VDL1 to VDLm is also similar.

7 is a plan view illustrating an organic EL device according to a second exemplary embodiment of the present invention.

In the organic EL device according to the second embodiment of the present invention shown in FIG. 7, the common lines CL1 and CL2 are formed on both sides of the substrate as compared to the organic EL device according to the first embodiment of the present invention. And the same components.

Common lines CL1 and CL2 are formed on both sides of the substrate in parallel with the gate lines. That is, the first common line CL1 is connected to the first supply pad 104a adjacent to the gate pad connected to the first gate line, and the second common line CL2 is adjacent to the gate pad connected to the last gate line. It is connected with the 2nd supply pad 104b. The first to m th power supply lines VDL1 to VDLm are connected to each of the first and second common lines CL1 and CL2 between the first and second common lines CL1 and CL2. In this case, the level of the supply voltage supplied to the start point and the end point of the power supply line VDL by the first and second common lines CL1 and CL2 is similar (a ≒ b ≒ c ≒ d) to prevent image quality deterioration. can do.

Each of the first and second common lines CL includes a first common pattern 130 and a second common pattern 132 connected to the first common pattern 130 and overlapping the sealant 120.

The first common pattern 130 is formed to have the same first width H1 and the same length V1 as compared to the common line illustrated in FIG. 3B.

The second common pattern 132 is formed to have a second width H2 in an area overlapping the sealant 120 and has a plurality of holes 134 penetrating through the second common pattern 132. This hole 134 passes ultraviolet rays (UV) irradiated from the back of the substrate 101 to cure the sealant 120 for bonding the substrate 101 and the packaging plate 111 as shown in FIG. . That is, ultraviolet light UV passing through the second common pattern 132 through the hole 134 is irradiated to the sealant 120 to cure the sealant 120.

The area of the first and second common lines CL1 and CL2 as a whole is increased by the second common pattern 132. As a result, the line resistance values a ≒ b ≒ c of the first and second common lines CL1 and CL2 which are located in a region close to the supply pads 104a and 104b or in a region far from the supply pads 104a and 104b. Xd) becomes similar, so that the level of each supply voltage supplied to the first to m th power supply lines VDL1 to VDLm through the first and second common lines CL1 and CL2 is also similar.

8A and 8B are plan views illustrating another embodiment of a common line according to the first and second embodiments of the present invention.

The holes 134 included in the second common pattern 132 of the common line are uniformly formed at predetermined intervals as shown in FIGS. 5 and 6 or formed into a plurality of holes 134 as shown in FIG. 8A. The formed hole group HG is formed with a predetermined distance d therebetween, or as the distance from the supply pad increases, the number of holes 134 gradually increases [decreases], or as shown in FIG. 8B. As the distance increases, the number of holes 134 included in the hole group HG formed with a predetermined interval d therebetween gradually increases (decreases). Meanwhile, as the number of holes 134 gradually decreases away from the supply pad, the area of the common line gradually increases as the distance from the supply pad increases. The non-uniformity of the supply voltage level due to the line resistance can be prevented.

On the other hand, the number of holes (hole group), the width of the hole, the length of the hole, the shape of the hole, the spacing between the holes (hole group), etc. can be variously changed in the area where the sealant is applied. In addition, the number of holes included in the hole group is necessary so that the lowest ultraviolet rays for curing the sealant can pass.

As described above, the electroluminescent display device and the method of manufacturing the same according to the present invention include a common line having a second common pattern having holes in a region overlapping the first common pattern and the bonding agent. By this common line, the area of the entire common line is increased compared to the prior art. As a result, the voltage level supplied to the common line located in an area close to or far from the supply pad becomes the same, thereby preventing deterioration in image quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A substrate on which an electroluminescent cell array is formed; A packaging plate bonded to the substrate by a bonding agent to face the electroluminescent cell array; And a signal line for supplying a driving signal to the electroluminescent cell array and extending to a region where the binder is formed, and for supplying a driving signal to the electroluminescent display device. The method of claim 1, The hole of the signal line is formed in the region overlapping with the adhesive agent electroluminescent display device. The method of claim 1, And the holes are formed of a plurality of groups, and the groups of holes are spaced apart from each other in a region overlapping the adhesive. The method of claim 1, The signal line is Electroluminescent display device, characterized in that formed on one side of the substrate. The method of claim 1, The signal line is Electroluminescent display device, characterized in that formed on both sides of the substrate. The method of claim 1, The electroluminescent cell array A gate line; A data line crossing the gate line; A supply line to which a driving signal is supplied through the signal line; First and second thin film transistors connected to the gate line, the data line, and the power supply line; And an electroluminescent cell connected to the second thin film transistor. A substrate on which an electroluminescent cell array is formed; In the manufacturing method of the electro luminescence display element formed by bonding the packaging plate facing the electroluminescent cell array by a bonding agent, And supplying a driving signal to the electroluminescent cell array and forming a signal line having a hole extending to a region where the binder is formed, and supplying a driving signal to the electroluminescent cell array. . The method of claim 7, wherein The hole of the signal line is formed in the region overlapping with the adhesive agent manufacturing method of an electro luminescence display device. The method of claim 7, wherein The signal line is The method of manufacturing an electro luminescence display device, characterized in that formed on one side of the substrate. The method of claim 7, wherein The signal line is A method for manufacturing an electro luminescence display device, characterized in that formed on both sides of the substrate.

Images