KR100714571B1 - Thin film capacitor embedded printed circuit board, and methods of manufacturing the same - Google Patents

Abstract

Provided are a printed circuit board having a thin film capacitor and a method of manufacturing the same.

The present invention provides a copper clad laminate (CCL) having copper foil having a predetermined pattern on both surfaces thereof; An ordinary dielectric film formed on at least one surface of the patterned copper foil-attached CCL; And an upper electrode formed on the dielectric film, wherein the CCL has a plated through hole TH for interconnecting the patterned copper foil, and the patterned copper foil and the upper electrode are each a power pad. And a printed circuit board having a thin film capacitor configured to be connected to the ground pad, and a method of manufacturing the printed circuit board.

Thin film capacitors, printed circuit boards, dielectric films, CCL

Description

Thin film capacitor embedded printed circuit board, and method of manufacturing the same

1 is a cross-sectional view of a printed circuit board incorporating a conventional capacitor.

2 is a cross-sectional view of a conventional thin film capacitor.

3 is a cross-sectional view of a printed circuit board with a thin film capacitor according to an embodiment of the present invention.

4 is a cross-sectional view of a printed circuit board with a thin film capacitor according to another embodiment of the present invention.

5 (a-i) is a manufacturing process diagram of a printed circuit board with a thin film capacitor according to an embodiment of the present invention.

6 (a-1) is a manufacturing process diagram of a printed circuit board with a thin film capacitor according to another embodiment of the present invention.

7 is a diagram showing the relationship between the dielectric constant and the like for the frequency of the thin film capacitor manufactured according to the present invention.

8 is a view showing the relationship of the capacitance isometric to the DC bias of the thin film capacitor manufactured according to the present invention.

The present invention relates to a printed circuit board with a thin film capacitor and a method of manufacturing the same, and more particularly, to a printed circuit board with a thin film capacitor having a low-temperature dielectric dielectric film through a conventional build-up PCB manufacturing process. will be.

With the miniaturization, high functionality, and high frequency of electronic products, an embedded passive device technology has recently been introduced to insert passive components mounted on a PCB into the PCB. This technology embeds passive devices (more than 50% of which are capacitors) that occupy more than 50% of the surface area of the board, improving product reliability and reducing noise by miniaturizing the product, increasing design freedom, and reducing solder joints. In addition, as the connection path is shortened, the effect of reducing inductance can be obtained.

In particular, decoupling capacitors are used to remove noise due to power supply and switching by placing them near the IC, and increasingly demanding higher capacitance and lower equivalent series inductance (ESL) due to the higher speed of IC chips.

In the case of SMD (Surface Mount Devices), inductance is being reduced to ~ 300pH through the development of low inductance chip capacitors (LICCs) with reduced inductance.

Therefore, research on thin film embedded capacitor (EDC) continues, and due to the thin film thickness of EDC, high capacitance and low ESL characteristics are being sought.

As an example of the method of manufacturing such an embedded decoupling capacitor (hereinafter EDC), the invention described in US Pat. No. 5,261,153 is mentioned. In this method, as shown in FIG. 1, a dielectric sheet that is not cured is placed between conductive Cu foils to produce a Capacitive PCB. In this case, however, the capacitance density is as low as 0.077 nF / cm ² (0.5 nF / in ² ), which limits its use.

Another method is the invention described in US Pat. No. 6,541,137, which manufactures high temperature thin film embedded capacitors using ferroelectrics. In the above method, as shown in FIG. 2, barrier layers such as Ni-P and Ni-Cr are proposed to prevent oxidation of the conductive layer due to high temperature heat treatment (400 to 800 ° C.).

In another method, a part of the lower metal layer made of Al, Ta, Nb, etc. is oxidized through anodizing to be used as a dielectric layer, and an intermediate layer is formed on the dielectric layer using a conductive polymer or an organic semiconducting material, and the electrode is formed thereon. A built-in embedded capacitor manufactured by forming a metal is proposed.

However, as described above, in the case of the thin film embedded capacitor, a technology of manufacturing a material expressing a dielectric constant by forming a thin film on an electrode in the form of RCC and crystallizing it by heat treatment, and then putting it in a PCB process. However, such materials cannot be realized on PCBs containing Resin due to heat treatment at a high temperature of 400-800 ° C, as well as problems in the degree of alignment due to oxidation of electrode parts, shrinkage / expansion, and management and work by separate manufacturing. There are many problems such as sex. In addition, there is a technical problem to be solved also in fairness such as a problem of bonding with the lower electrode.

Accordingly, an object of the present invention is to provide a printed circuit board with a thin film capacitor having a dielectric constant film that can be manufactured through a conventional PCB in-line process.

Another object of the present invention is to provide a method of manufacturing a printed circuit board having the thin film capacitor embedded therein.

The present invention for achieving the above object,

Copper clad laminate (CCL) having copper foil having a predetermined pattern on both surfaces thereof;

An ordinary dielectric film formed on at least one surface of the patterned copper foil-attached CCL; And

An upper electrode formed on the dielectric film;

The CCL has a plated through hole TH for interconnecting the patterned copper foil, and

The patterned copper foil and the upper electrode relate to a printed circuit board having a thin film capacitor configured to be connected to a power pad and a ground pad, respectively.

In addition, the present invention,

Copper clad laminate (CCL) having copper foil having a predetermined pattern on both surfaces thereof;

Insulating layers formed on both sides of the patterned copper foil-attached CCL;

A lower electrode formed on at least one of the insulating layers;

A dielectric film formed on the lower electrode; And

An upper electrode formed on the dielectric film;

The CCL has a plated through hole TH for interconnecting the patterned copper foil,

In the insulating layer, a plated BVH connecting the copper foil of the CCL and the lower electrode is formed, and

The lower electrode and the upper electrode relate to a printed circuit board having a thin film capacitor configured to be connected to a power pad and a ground pad, respectively.

In addition, the present invention,

Forming a through hole at a predetermined position of a copper clad laminate (CCL) having copper foil laminated on both surfaces thereof, and then plating the through hole;

Forming a dielectric film on at least one surface of the CCL on which the through hole is formed through a low temperature film forming process;

After attaching a photo resist dry film to both sides of the laminate on which the dielectric film is formed, the lower electrode copper foil and the dielectric film having the same pattern are formed by etching the dielectric film and the copper foil by a general photolithography process. Forming step; And

And a step of forming an upper electrode on the dielectric film.

In addition, the present invention,

Forming a through hole at a predetermined position of a copper clad laminate (CCL) having copper foil laminated on both surfaces thereof, and then plating the through hole;

Attaching a photosensitive dry film to both surfaces of the CCL on which the through holes are formed, and then etching the copper foil using a conventional photolithography process to form a copper foil having a predetermined pattern;

Laminating an insulating layer on both surfaces of the CCL having the patterned copper foil, and then forming BVH at a predetermined position of the insulating layer;

Forming a metal conductive layer by electrolessly and electrolytic copper plating both surfaces of the laminate on which the BVH is formed;

Forming a dielectric film on at least one of the formed metal conductive layers through a low temperature film forming process;

A photoresist dry film is attached on the dielectric film, and then the dielectric film and the metal conductive layer are etched using a conventional photolithography process to form a metal conductive layer and an dielectric film having the same pattern. Process of doing; And

And a step of forming an upper electrode on the dielectric film.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view of a printed circuit board with a thin film capacitor according to an embodiment of the present invention.

As shown in FIG. 3, the printed circuit board 100 of the present invention includes: a copper clad laminate (CCL) 110 having copper foils 113a and 113b having predetermined patterns on both surfaces thereof; A dielectric film 130 formed on at least one surface of the copper foil-attached CCL 110; And an upper electrode 150 formed on the dielectric film 130.

The CCL 110 also has plated through holes 111a and 111b for interconnecting the patterned copper foils 113a and 113b.

The copper foil 111a and the upper electrode 150 are configured to be connected to the power pad 190b and the ground pad 190a of the IC chip, respectively. This connection is possible through the formation of BVH, TH, etc., the present invention is not limited to the specific method. For example, in the present invention, as shown in FIG. 3, the polymer insulating layer 160a, such as an ABF film, is stacked on the upper electrode 150, and then the BVHs 161a and 161b are formed at predetermined positions. Thereafter, the BVH may be plated and the metal conductive layer pattern 170a may be formed using a sequential process of electroless copper plating, dry film deposition, pattern formation, electrolytic copper plating, and flash etching. In addition, the polymer insulating layer 180a is laminated on both sides of the laminate on which the conductive layer pattern 170a is formed, BVH holes 181a and 181b are formed, electroless copper plating, pattern formation after dry film deposition, electrolytic copper plating and flash etching. Each layer can be connected through a well-known continuous process.

That is, in the present invention, the lower electrode copper foil 113a may be connected to the power pad 190b through the sequentially plated BVH 161b and BVH 181b, and the upper electrode 150 may be respectively It may be connected to the ground pad 190a through the sequentially plated BVH 161a and BVH 181a.

In addition, as shown in FIG. 3, the polymer insulating layer 160b is laminated, the BVH 163 is formed, and the conductive pattern is formed on the patterned copper foil 113b of the CCL 110 where the dielectric film 150 is not formed. 170b) forming, stacking polymer insulating layer 180b, forming BVH (183), electroless plating, electroplating, and so on, so that the lower electrode copper foil is connected to the input power pad 195 of the IC chip. can do.

4 is a cross-sectional view of a printed circuit board with a thin film capacitor according to another embodiment of the present invention. As shown in Figure 4, the printed circuit board 200 of the present invention, the copper clad laminate (210) attached to the copper foil (211a, 211b) having a predetermined pattern on both sides thereof; Insulating layers 230a and 230b formed on both surfaces of the copper foil-attached CCL 210; A lower electrode 250 formed on at least one of the insulating layers 230a and 230b; An dielectric film 260 formed on the lower electrode 250; And an upper electrode 270 formed on the dielectric film 260.

The CCL 210 also has plated through holes 211a and 211b for interconnecting the patterned copper foils 211a and 211b. In addition, the insulating layers 230a and 230b include plated BVHs 231a and 231b connecting the copper foils 213a and 213b of the CCL 210 to the lower electrode 250 or the metal conductive layer 250 ″, respectively. ) Is formed.

The lower electrode 250 and the upper electrode 270 are configured to be connected to the power pad 290b and the ground pad 290a of the IC chip, respectively. This connection is possible through the formation of BVH, TH, etc., the present invention is not limited to the specific method. For example, in the present invention, as shown in FIG. 4, the polymer insulating layer 280 such as an APF film is laminated on both surfaces of the laminate on which the upper electrode 270 is formed, and then BVHs 281a and 281b are formed at predetermined positions. . After that, the BVH may be plated and connected between layers through well-known continuous processes such as electroless copper plating, dry film deposition, pattern formation, electrolytic copper plating, and flash etching.

That is, in the present invention, the lower electrode 250 may be connected to the power pad 290b through the plated BVH 281b, and the upper electrode 270 may be connected to the ground pad through the plated BVH 281a. 290a).

In addition, as shown in FIG. 4, the polymer insulating layer 280b is laminated, the BVH 283 is formed, the electroless plating, the pattern formation after the D / F deposition, and the electroplating process, below the CCL on which the conductive pattern 250 ″ is formed. , And flash etching may be sequentially performed to connect the lower electrode copper foil to the input power pad 295 of the IC chip.

Meanwhile, in the above-described embodiment of the present invention, the dielectric films 130 and 260 may be formed by a physical vapor deposition (PVD) method, and have a BiZnNb-based dielectric constant at a low temperature of 300 ° C. or less (generally 200 ° C. or less). It is preferably composed of an amorphous metal oxide, and more preferably composed of Bi _x Zn _y Nb _z O ₇ metal oxide satisfying 1.3 <x <2.0, 0.8 <y <1.5, and z <1.6. In addition, a low-temperature dielectric thin film containing Bi ₂ O ₃ , ZnO, Nb ₂ O ₅ , PbO, CuO, TiO ₂ , or the like, or a thin film such as Al ₂ O ₃ which can be formed by ALD (Atomic Layer Deposition) method may be used.

More preferably, the thickness of the dielectric dielectric films 130 and 260 is limited to 1 μm or less, more preferably 500 nm or less.

In addition, the upper electrodes 150 and 270 are preferably made of at least one metal selected from the group consisting of Cu, Ni, Al, Pt, Ta, and Ag.

Next, the manufacturing process of the printed circuit board incorporating the thin film capacitor of the present invention will be described.

5 is a manufacturing process diagram of a printed circuit board with a thin film capacitor according to an embodiment of the present invention.

As shown in FIG. 5 (a), in the present invention, through holes 311a and 311b are first formed at predetermined positions of copper clad laminates 310 having copper foils laminated on both surfaces thereof, and then the through holes are formed. Plate. Such through holes are possible by conventional mechanical processing and are not limited to any particular method. Thereafter, the through holes 311a and 311b formed by the above processing can be conducted by electroless copper plating and electrolytic copper plating.

Subsequently, in the present invention, as shown in FIG. 5B, at least one surface of the CCL 310 having the through holes 311a and 311b is formed on the at least one surface thereof through a low temperature film forming process.

The dielectric dielectric film 330 may be formed by a physical vapor deposition (PVD) method such as sputtering, and is preferably composed of a BiZnNb-based amorphous metal oxide having a dielectric constant at a low temperature of 300 ° C or lower (generally, 200 ° C or lower). . More preferably, Bi _x Zn _y Nb _z O ₇ metal oxides satisfying 1.3 <x <2.0, 0.8 <y <1.5, and z <1.6. In the present invention, a low-temperature dielectric thin film including Bi ₂ O ₃ , ZnO, Nb ₂ O ₅ , PbO, CuO, TiO ₂ , or the like, and Al ₂ O ₃ , which can be formed by ALD (Atomic Layer Deposition), may be used as the dielectric film. It may be.

More preferably, the thickness of the dielectric dielectric film 330 is limited to 1 μm or less, more preferably 500 nm or less.

Subsequently, in the present invention, as shown in Figure 5 (c), after attaching a photoresist dry film (335) on both sides of the laminate on which the dielectric film 330 is formed, using a conventional photolithography process By etching the dielectric film 330 and the copper foil, the lower electrode copper foil 313a and the dielectric dielectric film 330 having the same pattern are formed.

At this time, the dry film 335 is also attached below the CCL 310, and then exposed, developed, and etched to form a copper foil 313b having a predetermined pattern.

Then, after forming the dielectric film and / or copper foil having a predetermined pattern, the dry film 335 of the etched portion is removed.

Next, in the present invention, the upper electrode 350 is formed on the dielectric film 330.

Preferably, as shown in FIG. 5 (d), after the dry film is re-attached to the surface of the laminate on which the dielectric film 330 is formed, the portion A where the dielectric film 330 is etched. And exposing and developing the relaminated dry film so that a dry film pattern 340 is formed on a portion of the dielectric film adjacent thereto. As such, the reason why the dry film pattern 340 is formed not only in the portion A where the dielectric film 330 is etched but also in the portion of the dielectric film 330 adjacent thereto is because of the copper foil as the lower electrode. This is to make the size of the upper electrode 350 formed later than 313a smaller. By reducing the size of the upper electrode 350 in this way, not only a space for forming BVH in a subsequent process can be given, but also leakage current characteristics can be improved.

Subsequently, as shown in FIG. 5E, after forming the upper electrode 350 on the dielectric film 330 on which the dry film pattern 337 is not formed, the dry film is removed to have a predetermined pattern. The upper electrode 50 may be formed.

In this case, the present invention is not limited to the specific method of forming the upper electrode 350. For example, the upper electrode may be formed on the dielectric film 330 on which the dry film pattern is formed by using a conventional PVD method or printing method such as sputtering method or evaporation method. In addition, a method of electroplating after electroless plating may be used, and an upper electrode may be formed by applying a PVD method after electroless plating.

In the present invention, the upper electrode 350 is preferably made of at least one metal selected from the group consisting of Cu, Ni, Al, Pt, Ta, and Ag.

Next, in the present invention, as shown in FIG. 5 (f), the polymer insulating layers 360a and 360b, such as ABF films, are laminated on both surfaces of the laminate prepared as described above, and then BVH 361a, 361b and 363). Such BVH can be processed using conventional CO ₂ lasers.

Then, as shown in Figure 5 (g), the insulating layer (360a, 360b) through the electroless copper plating, dry film deposition pattern formation, electrolytic copper plating and Flash etching process on both sides of the laminate laminated the insulating layer having the BVH The metal conductive layer patterns 370a and 370b may be formed. On the other hand, the BVH is conducted with such electroless and electroplating.

Then, as shown in FIG. 5 (h), the polymer insulating layers 380a and 380b are laminated on both sides of the laminate on which the metal conductive layer patterns 370a and 370b are formed, and the BVHs 381a and 381b and 383 are formed and electroless. The printed circuit board 300 as shown in FIG. 5 (i) may be manufactured through processes such as copper plating, D / F deposition, pattern formation, electrolytic copper plating, and flash etching. 5 (i), reference numeral 390a denotes a ground pad, 390b denotes a power pad, and 395 denotes an input power pad.

On the other hand, Figure 6 is a manufacturing process diagram of a printed circuit board with a thin film capacitor according to another embodiment of the present invention.

As shown in FIG. 6 (a), in the present invention, through holes 411a and 411b are first formed at predetermined positions of a copper clad laminate (CCL) 410 in which copper foils are laminated on both surfaces thereof. Plate. Such through holes are possible by conventional mechanical processing and are not limited to any particular method. Thereafter, the through-holes 411a and 411b formed by the above processing may be normally conducted through electroless copper plating and electrolytic copper plating.

Subsequently, as shown in FIG. 6 (b), the photosensitive dry film 420 is attached to both surfaces of the CCL 410 having the through hole, and then the copper foil is etched by using a conventional photolithography process. ), Copper foils 413a and 413b having a predetermined pattern are formed.

6 (d), after laminating polymer insulating layers 430a and 430b such as a polymer insulating film such as an ABF film on both sides of the CCL 410 having the patterned copper foils 413a and 413b, BVHs 431a and 431b are formed at predetermined positions of the insulating layer. Such BVH can be processed using conventional CO ₂ lasers.

Next, as shown in FIG. 6E, both surfaces of the CCL 410 having the insulating layers 430a and 430b stacked thereon, for example, by electroless copper plating, and then electrolytic copper plating to form metal conductive layers 450 and 450 on the insulating layer. On the other hand, the above formed BVHs 431a and 431b become conductive.

In the present invention, at least one of the formed metal conductive layers is used as the lower electrode 450 of the thin film capacitor.

Subsequently, in the present invention, as shown in FIG. 6 (f), the dielectric film 460 is formed on the lower electrode 450 through a low temperature film formation process.

The dielectric dielectric film 460 may be formed by a physical vapor deposition (PVD) method such as sputtering and the like, and is preferably composed of a BiZnNb-based amorphous metal oxide having a dielectric constant at a low temperature of 300 ° C or lower (generally 200 ° C or lower). . More preferably, Bi _x Zn _y Nb _z O ₇ metal oxides satisfying 1.3 <x <2.0, 0.8 <y <1.5, and z <1.6. In the present invention, a low-temperature dielectric thin film including Bi ₂ O ₃ , ZnO, Nb ₂ O ₅ , PbO, CuO, TiO ₂ , or the like, and Al ₂ O ₃ , which can be formed by ALD (Atomic Layer Deposition), may be used as the dielectric film. It may be.

More preferably, the thickness of the dielectric dielectric film 460 is limited to 1 μm or less, more preferably 500 nm or less.

Next, as shown in Figure 6 (g), after attaching a photo resist dry film (462) on both sides of the laminate on which the dielectric film 460 is formed, using the conventional photolithography process After the dielectric film 460 and the lower electrode 450 are etched, the dry film 462 of the unvisible portion is removed. Accordingly, as shown in FIG. 6H, the lower electrode 450 and the dielectric dielectric film 460 having the same pattern may be formed.

Thereafter, in the present invention, the upper electrode 470 is formed on the upper dielectric film 460 by electroless plating.

Preferably, first, the dry film is reattached to the surface of the laminate on which the dielectric film 460 is formed, and then, as shown in FIG. 6 (i), the portion A where the dielectric film 460 is etched. And exposing and developing the relaminated dry film so that a dry film pattern 465 is formed on a portion of the dielectric film adjacent thereto. As such, the reason why the dry film pattern 465 is formed not only in the portion A where the dielectric film 460 is etched but also in the portion of the dielectric film 460 adjacent thereto is as described above.

Subsequently, as shown in FIG. 6 (j), the upper electrode 470 is formed on the dielectric film 460 on which the dry film pattern 465 is not formed.

In this case, the present invention is not limited to the specific method of forming the upper electrode 470. For example, the upper electrode may be formed on the dielectric film 460 on which the dry film pattern is formed by using a conventional PVD method or printing method such as sputtering method or evaporation method. In addition, a method of electroplating after electroless plating may be used, and an upper electrode may be formed by applying a PVD method after electroless plating.

In the present invention, the upper electrode 470 is preferably composed of at least one metal selected from the group consisting of Cu, Ni, Al, Pt, Ta, and Ag.

Subsequently, in the present invention, as shown in FIG. 6 (k), the polymer insulating layers 480a and 480b, such as ABF films, are laminated on both surfaces of the laminate prepared as described above, and then BVHs 481a, 481b, and 483 are positioned at predetermined positions. ) Can be formed. Such BVH can be processed using conventional CO ₂ lasers.

Thereafter, as shown in FIG. 6 (l), the final printed circuit board 400 may be manufactured by processes such as electroless copper plating, pattern formation after D / F adhesion, electrolytic copper plating, and flash etching on both surfaces of the laminate. . Through this sequential process, the BVH is conductive, and a metal conductive layer pattern is formed on the insulating layers 480a and 480b. 6 (k), reference numeral 490a denotes a ground pad, 490b denotes a power pad, and 495 denotes an input power pad.

Through the above-described manufacturing process, each of the lower electrode and the upper electrode constituting the thin film capacitor of the present invention can be effectively connected to the power pad and ground pad attached to various IC chips through the formation of the BVH presented through one embodiment. Therefore, it is possible to implement a thin film capacitor having excellent decoupling characteristics.

Hereinafter, the present invention will be described in detail with reference to examples, which are merely exemplary and the present invention is not limited thereto.

Example

Through vias were formed on the CCL substrate through mechanical drills, and then electroless and electrolytic copper plating were used to form Cu 2 μm metal electrode layers. Was then formed in such as 5 (a) even in the CCL the metal electrode layer, Bi Zn _{1 .5 1 .5 1 .0} Nb O ₇ composition sputtering method Full paraelectric film having a thickness of 300nm. At this time, the deposition temperature was 25 ° C., and the atmosphere gas composition had an Ar: O ₂ ratio of 4: 1.

Subsequently, as shown in FIG. 5 (b), after deposition of the dielectric film, D / F (dry film) was attached according to a general PCB process and patterned through a photolithography process. After patterning as shown in FIG. 5 (c), D / F was removed and D / F was formed again to form an upper electrode having a thickness of 1 μm. Subsequently, an insulating film (ABF) was stacked according to a general flip chip BGA process as shown in FIG. 5 (e) and a blind via hole (BVH) was formed using a laser. At this time, since the electrode and the dielectric film is thin, preferably a CO ₂ Laser. CO ₂ Laser is easy to process because of its long wavelength and small effect on metal.

In addition, as shown in FIG. 5 (g), after electroless plating according to a general flip chip BGA process, D / F was laminated and patterned through a photolithography process, followed by electroplating. After the electroplating, D / F was removed and the finished electrode pattern was formed by removing the electroless plating layer through flash etching. Subsequent processes follow the normal flip chip BGA process.

7 and 8 show the results of evaluating the electrical properties using the Impedance Analyzer after the dielectric film was manufactured in the above manner. FIG. 7 is a graph showing electrical characteristics measured by forming a Bi _1.5 Zn ₁ Nb _1.5 dielectric thin film on a CCL substrate and then forming an upper electrode through sputtering. The deposition of BZN was performed at room temperature, so it was analyzed as an uncrystallized amorphous state. In this amorphous state, the dielectric constant of 50 or more and loss of 0.01 or less can be confirmed. Therefore, the use of this BZN material enables dielectric film formation process at room temperature and PCB in-line process application. Can be.

Meanwhile, FIG. 8 shows the change in permittivity of BZN according to the change of DC-bias, which is different from the commonly used ferroelectric, and it can be seen that the change in permittivity according to the change of current is shown as a dielectric material.

As described above, the present invention has been described in detail through the preferred embodiments, but the present invention is not limited to the contents of these embodiments. Those skilled in the art to which the present application pertains, although not shown in the Examples, can be imitated or improved for various inventions within the scope of the appended claims, all of which are within the technical scope of the present invention. Would be too self-explanatory.

As described above, the present invention has a useful effect in the manufacture of a thin film capacitor embedded printed circuit board having excellent decoupling characteristics by forming a thin film capacitor having a low-temperature dielectric film through a conventional PCB in-line process. In addition, it is possible to ensure excellent productivity compared to the process that requires a conventional high temperature heat treatment.

Claims (37)

Copper clad laminate (CCL) having copper foil having a predetermined pattern on both surfaces thereof; A low temperature dielectric dielectric film formed on at least one surface of the patterned copper foil-attached CCL; And An upper electrode formed on the low temperature dielectric film; The CCL has a plated through hole TH for interconnecting the patterned copper foil, and The patterned copper foil and the upper electrode is a printed circuit board with a thin film capacitor configured to be connected to the power pad and the ground pad, respectively. The printed circuit board with a thin film capacitor according to claim 1, wherein the low-temperature dielectric film is made of BiZnNb-based amorphous metal oxide. The low-temperature dielectric dielectric film of claim 1 or 2, wherein the low-temperature dielectric film is composed of Bi _x Zn _y Nb _z O ₇ metal oxides satisfying 1.3 <x <2.0, 0.8 <y <1.5, and z <1.6. Printed circuit board with a thin film capacitor. The printed circuit board with a thin film capacitor according to claim 1, wherein the low-temperature dielectric film is an Al ₂ O ₃ thin film formed by ALD (Atomic Layer Deposition). The printed circuit board with a thin film capacitor according to claim 1, wherein the low-temperature dielectric film has a thickness of 1 µm or less. The printed circuit board of claim 1, wherein the through-holes are Cu electroless and electroplated. The printed circuit board of claim 1, wherein the upper electrode is made of at least one metal selected from the group consisting of Cu, Ni, Al, Pt, Ta, and Ag. The method of claim 1, wherein the printed circuit board, A polymer insulating layer formed on both surfaces of the laminate in which the upper electrode is formed; A metal conductive layer pattern formed on the polymer insulating layer; And Further comprising a polymer insulating layer formed on the conductive layer pattern, And a non-electrolytic and electrolytic copper plated BVH formed at a predetermined position of the polymer insulating layer to connect the patterned copper foil and the upper electrode to the power pad and the ground pad, respectively. Copper clad laminate (CCL) having copper foil having a predetermined pattern on both surfaces thereof; Insulating layers formed on both surfaces of the copper foil-attached CCL; A lower electrode formed on at least one of the insulating layers; A low temperature dielectric film formed on the lower electrode; And An upper electrode formed on the low temperature dielectric film; The CCL has a plated through hole TH for interconnecting the patterned copper foil, In the insulating layer, a plated BVH connecting the copper foil of the CCL and the lower electrode is formed, and The lower electrode and the upper electrode is a printed circuit board with a thin film capacitor configured to be connected to the power pad and the ground pad, respectively. 10. The printed circuit board of claim 9, wherein the low-temperature dielectric film is made of BiZnNb-based amorphous metal oxide. The method of claim 9 or 10, wherein the low-temperature dielectric dielectric film is composed of Bi _x Zn _y Nb _z O ₇ metal oxide satisfying 1.3 <x <2.0, 0.8 <y <1.5, and z <1.6. Printed circuit board with a thin film capacitor. 10. The printed circuit board of claim 9, wherein the low-temperature dielectric film is an Al ₂ O ₃ thin film formed by ALD (Atomic Layer Deposition). 10. The printed circuit board with a thin film capacitor according to claim 9, wherein the low-temperature dielectric film has a thickness of 1 µm or less. 20. The printed circuit board of claim 19, wherein the through-holes and the BVH are electroless and electroplated with Cu. The printed circuit board of claim 9, wherein the upper electrode is made of at least one metal selected from the group consisting of Cu, Ni, Al, Pt, Ta, and Ag. The printed circuit board of claim 9, wherein the lower electrode is formed of Cu electroless plating and electroplating. The method of claim 9, wherein the printed circuit board, Further comprising a polymer insulating layer formed on both sides of the laminate on which the upper electrode is formed, And an electroless and electrolytic copper plated BVH formed at a predetermined position of the polymer insulating layer so as to connect the lower electrode and the upper electrode to the power pad and the ground pad, respectively. Forming a through hole at a predetermined position of a copper clad laminate (CCL) having copper foil laminated on both surfaces thereof, and then plating the through hole; Forming a low-temperature dielectric dielectric film on at least one surface of the CCL on which the through hole is formed through a low temperature film formation process; After attaching a photoresist dry film to both surfaces of the laminate on which the dielectric film is formed, the dielectric film and the copper foil are etched by a general photolithography process to form the lower electrode copper foil and the dielectric film having the same pattern. Process of doing; And Forming a top electrode on the dielectric film; and a method of manufacturing a printed circuit board including a thin film capacitor. 20. The method of claim 18, wherein the low-temperature dielectric film is a BiZnNb-based amorphous metal oxide formed by PVD. 20. The method according to claim 18 or 19, wherein the low-temperature dielectric film is composed of Bi _x Zn _y Nb _z O ₇ metal oxide satisfying 1.3 <x <2.0, 0.8 <y <1.5, and z <1.6. Printed circuit board manufacturing method with a thin film capacitor. 19. The method of claim 18, wherein the low temperature dielectric film is an Al ₂ O ₃ thin film formed by ALD (Atomic Layer Deposition). 19. The method of claim 18, wherein the through-holes are subjected to Cu electroless plating and electroplating. 19. The method of claim 18, wherein the upper electrode is made of at least one metal selected from the group consisting of Cu, Ni, Al, Pt, Ta, and Ag. 19. The method of claim 18, further comprising Stacking a polymer insulating layer on both surfaces of the laminate in which the upper electrode is formed, and then forming BVH at a predetermined position; Forming a metal conductive layer pattern by electroless copper plating, pattern formation after dry film attachment, and electrolytic copper plating on both sides of the laminate on which the BVH is formed; Stacking a polymer insulating layer on both surfaces of the laminate on which the conductive layer pattern is formed, and then forming BVH at a predetermined position; And Forming a metal conductive layer pattern by electroless copper plating, dry film deposition, pattern formation, and electrolytic copper plating on both sides of the laminate on which the BVH is formed; and further comprising a thin film capacitor embedded printed circuit board. The method of claim 18, wherein the forming of the upper electrode comprises: Reattaching a dry film to a surface of the laminate on which the low-temperature dielectric film is formed; Exposing and developing the reattached dry film such that a dry film pattern is formed on a portion where the low temperature dielectric film is etched and a portion of the low temperature dielectric film adjacent thereto; And And forming an upper electrode on the low-temperature dielectric film in which the dry film pattern is not formed. 27. The method of claim 25, wherein an upper electrode is formed on the low temperature dielectric film by PVD. 27. The method of claim 25, wherein after the electroless plating on the low temperature dielectric film, the upper electrode is formed by using one of PVD and electroplating methods. Forming a through hole at a predetermined position of a copper clad laminate (CCL) having copper foil laminated on both surfaces thereof, and then plating the through hole; Attaching a photosensitive dry film to both surfaces of the CCL on which the through holes are formed, and then etching the copper foil using a conventional photolithography process to form a copper foil having a predetermined pattern; Laminating an insulating layer on both surfaces of the CCL having the patterned copper foil, and then forming BVH at a predetermined position of the insulating layer; Forming a metal conductive layer by electrolessly and electroplating both surfaces of the laminate on which the BVH is formed; Forming a low temperature dielectric film on at least one of the formed metal conductive layers through a low temperature film forming process; A photoresist dry film is attached to the dielectric film, and then the low-temperature dielectric film and the metal conductive layer are etched by using a conventional photolithography process to form a metal conductive layer and a dielectric film having the same pattern. Forming step; And Forming an upper electrode on the low temperature dielectric film; and a method of manufacturing a printed circuit board having a thin film capacitor embedded therein. 29. The method of claim 28, wherein the low-temperature dielectric film is made of BiZnNb-based amorphous metal oxide. 30. The method according to claim 28 or 29, wherein the low-temperature dielectric film is composed of Bi _x Zn _y Nb _z O ₇ metal oxide satisfying 1.3 <x <2.0, 0.8 <y <1.5, and z <1.6. Printed circuit board manufacturing method with a thin film capacitor. 29. The method of claim 28, wherein the low temperature dielectric film is an Al ₂ O ₃ thin film formed by ALD (Atomic Layer Deposition). 29. The method of claim 28, wherein the through hole and the BVH are electroless and electroplated with Cu. 29. The method of claim 28, wherein the upper electrode is made of at least one metal selected from the group consisting of Cu, Ni, Al, Pt, Ta, and Ag. The method of claim 28, further comprising: Stacking a polymer insulating layer on both surfaces of the laminate in which the upper electrode is formed, and then forming BVH at a predetermined position; And And forming a metal conductive layer pattern by electroless copper plating, dry film deposition, pattern formation, and electrolytic copper plating on both sides of the laminate on which the BVH is formed. The method of claim 28, wherein the forming of the upper electrode, Reattaching a dry film to a surface of the laminate on which the low-temperature dielectric film is formed; Exposing and developing the reattached dry film such that a dry film pattern is formed on a portion where the low temperature dielectric film is etched and a portion of the dielectric film adjacent thereto; And And forming an upper electrode on the low-temperature dielectric film in which the dry film pattern is not formed. 36. The method of claim 35, wherein an upper electrode is formed on the low temperature dielectric film by PVD. 36. The method of manufacturing a printed circuit board with a thin film capacitor according to claim 35, wherein after the electroless plating on the low temperature dielectric film, an upper electrode is formed by using one of PVD and electroplating methods.

Images