KR100710211B1 - Field Emission Display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a field emission display device, and more particularly, to a structure of a field emission display device in which a concentration of an electric field is widely distributed along an interface of a cruciform hole so that a large amount of electrons are emitted.

The field emission display device according to the present invention includes a plurality of cathode electrode lines, a cathode insulation layer formed on the cathode electrode line, a metal bus electrode formed on the cathode insulation layer to emit electrons, and the plurality of cathode electrodes. And a plurality of gate electrode lines intersecting the line and being formed to expose the metal bus electrode at an intersection thereof, wherein the electrons are emitted along an interface between the gate electrode line and the exposed metal bus electrode.

According to the present invention, the concentration of the electric field is widely distributed along the interface of the cruciform hole, so that a lot of electrons are emitted in the plane between the gate electrode and the cathode electrode to realize high luminance. In addition, as the overlapping area of the gate electrode and the cathode electrode is narrowed, the capacitance component is reduced, thereby reducing power consumption and enabling high-speed response / driving. In addition, the manufacturing method is easy, and the driving voltage is reduced and power consumption is reduced by the low voltage tunnel (Tunel) effect by controlling the thickness of the insulating layer.

Description

Field emission display device {Field Emission Display}             

1 is a perspective view showing a conventional field emission display device.

FIG. 2 is a cross-sectional view of the field emission display device shown in FIG. 1. FIG.

3 is a plan view illustrating an electrode structure of the field emission display device illustrated in FIG. 1.

4A and 4D are cross-sectional views showing a conventional method for manufacturing a field emission display device.

5 is a cross-sectional view of a field emission display device according to the present invention;

6 is a plan view showing an electrode structure of the field emission display device according to the present invention.

FIG. 7 is an enlarged perspective view of part X shown in FIG. 6;

8a and 8e are cross-sectional views showing a manufacturing method according to the present invention.

9 is a waveform diagram showing a general waveform of the field emission display device according to the present invention;

<Description of Symbols for Main Parts of Drawings>

2,42 upper glass substrate 4,44 anode electrode

6,46 phosphor 7: separation layer

7a: opening hole 8,38: lower glass substrate                 

9: tip region 10,30: cathode electrode

12: resistive layer 14, 34: gate insulating layer

14a, 34a: insulating material 15: decagonal hole

16, 36: gate electrode 16a, 26, 35a, 36a: electrode material

22 emitter 30,31 electron beam

32,52: field emission array 35: metal bus electrode

40,50: spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission display device, and more particularly, to a field emission display device in which a large number of electrons are emitted along an interface by forming a hole of a predetermined shape to expose a metal bus electrode to a gate electrode.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes (hereinafter, referred to as "CRTs"). Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (hereinafter referred to as "FEDs"), and plasma displays (hereinafter referred to as "PDPs"). &Quot; EL ", &quot; EL &quot;, and the like. In order to improve the display quality, research and development are being actively conducted to increase the brightness, contrast and color purity of flat panel displays.

The FED concentrates a high field on a sharp cathode (emitter), emits electrons by a quantum mechanical tunnel effect, and displays an image by exciting the phosphor using the emitted electrons.

1 and 2, an upper glass substrate 2 on which an anode electrode 4 and a phosphor 6 are stacked, and a field emission array 32 formed on the lower glass substrate 8 are provided. FED is shown. The field emission array 32 includes the cathode electrode 10 and the resistive layer 12 formed on the lower glass substrate 8, and the gate insulating layer 14 and the emitter 22 formed on the resistive layer 12. ) And a gate electrode 16 formed on the gate insulating layer 14. The cathode electrode 10 supplies current to the emitter 22, and the resistive layer 12 restricts the overcurrent applied from the cathode electrode 10 toward the emitter 22 to uniform the emitter 22. It serves to supply current. The gate insulating layer 14 insulates between the cathode electrode 10 and the gate electrode 16. The gate electrode 16 is used as an extraction electrode for drawing electrons. A spacer 40 is installed between the upper glass substrate 2 and the lower glass substrate 8 to withstand the external atmospheric pressure.

In order to display an image, a negative (-) cathode voltage is applied to the cathode electrode 10 and a positive (+) anode voltage is applied to the anode electrode 4. A gate voltage of positive polarity (+) is applied to the gate electrode 16. The electron beam 30 emitted from the emitter 22 is then accelerated toward the anode electrode 4. The electron beam 30 collides with the red, green, and blue phosphors 6 to excite the phosphors 6. At this time, visible light of any one of red, green, and blue colors is generated according to the phosphor 6. In the phosphor 6, red, green, and blue are sequentially arranged in sub-pixel units as shown in FIG. For this reason, when the electron beam 30 generated in any one subpixel or pixel is accelerated toward the phosphor 6, it is possible to emit light of the phosphor 6 of another color adjacent by diffusion of the electron beam 30.

FEDs having an emitter structure of such a conical tip are mainly manufactured by the "spint method".

4A to 4D are diagrams illustrating a method of manufacturing the FED step by step using the spin method.

First, as shown in FIG. 4A, an electrode material is deposited on the lower glass substrate 8 and then patterned to form a cathode electrode 10. Then, the insulating material 14a is deposited on the cathode electrode 10 by a predetermined thickness, and the electrode material 16a is deposited on the entire surface. The electrode material 16a is patterned by a photolithograpy as shown in FIG. 4B to form a gate electrode 16, and the insulating material 14a is etched using the gate electrode 16 as a mask. Then, the etched insulating material 14a is formed of the gate insulating layer 14. The gate insulating layer 14 is provided with a tip region 9 in which the emitter 22 is formed. Subsequently, an isolation layer 7 is formed on the gate insulating layer 14 as shown in FIG. 4C. In the separation layer 7, opening holes 7a opposed to the tip regions 9 are formed. Subsequently, while the lower glass substrate 8 is rotated at approximately 15 ° inclination, an electrode material is deposited on the surface of the cathode electrode 10 in the tip region 9 as shown in FIG. 4D. At this time, the electrode material is also formed on the separation layer 7 as shown in FIG. 4D as time passes, and is deposited conical on the cathode electrode 10 to become the emitter 22. Finally, the separation layer 7 on which the electrode material 26 is stacked is removed.

The manufacturing method of the FED using the spin method is complicated, and precise control of the process is required in the vacuum deposition process of the electrode material obliquely, and the resolution is impaired due to the limited space in order to have many electron sources. Problems arise in increasing the resolution.

The FED as shown in FIG. 1 excites the phosphor 6 by the electron beam 30 to generate visible light, but in order to obtain high luminance, the amount of electrons generated from the cathode electrode 10 must be increased. However, in order to increase the amount of electrons, the driving voltage is increased so much that excessive power consumption is wasted. In addition, the overlapping area of the gate electrode 16 and the cathode electrode 10 has a large capacitance component, which causes problems in high-speed response and driving. This problem is present in other flat panel displays in addition to the FED. For this purpose, recently, the emitter 22 has been developed in a flat type with good mass productivity. In addition, research is being conducted to apply the high voltage phosphor used in the general CRT to the FED.

Accordingly, an object of the present invention is to provide a field emission display device which obtains high brightness by distributing an electric field in a large area along an interface of a predetermined shape hole formed so that the metal bus electrode is exposed at the intersection of the cathode electrode and the gate electrode. It is.

In order to achieve the above object, the field emission display device according to the present invention includes a plurality of cathode electrode lines, a cathode insulation layer formed on the cathode electrode line, and a metal bus electrode formed on the cathode insulation layer to emit electrons. And a plurality of gate electrode lines intersecting the plurality of cathode electrode lines and exposing the metal bus electrodes at intersections thereof, wherein the electrons are along an interface between the gate electrode lines and the exposed metal bus electrodes. It is preferred to be released.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 9.

5 and 6, the field emission display device according to the present invention is formed on the upper glass substrate 42 and the lower glass substrate 38 on which the anode electrode 44 and the phosphor 46 are stacked. The field emission array 52 is provided. The field emission array 52 covers only the cathode electrode 30 formed on the lower glass substrate 38 and the gate insulating layer 34 formed on the cathode electrode 30, and only an upper portion of the gate insulating layer 34. The gate electrode 36 formed in parallel with the metal bus electrode 35 and the gate insulating layer 34, and the metal bus electrode 35 at the intersection of the cathode electrode 30 on the gate electrode 36. ) Is provided with a cross-shaped hole 15 formed to be exposed.

Unlike the prior art, the field emission display device according to the present invention emits electrons along the interface of the cruciform holes in a similar shape to a flat type.

The cathode electrode 30 supplies a current to an emitter (not shown), and the gate insulating layer 34 insulates between the cathode electrode 30 and the gate electrode 36. In addition, the metal bus electrode 35 serves as a bridge between the gate electrodes 36 divided up and down. The gate electrode 36 is used as an extraction electrode for withdrawing electrons. The spacer 50 is installed between the upper glass substrate 42 and the lower glass substrate 38 to withstand the external atmospheric pressure. In order to display an image, a negative (-) cathode voltage is applied to the cathode electrode 30 and a positive (+) anode voltage is applied to the anode electrode 44. The gate voltage of positive polarity (+) is applied to the gate electrode 36. The electron beam 31 emitted from the emitter, not shown, is then accelerated toward the anode electrode 44. The electron beam collides with the red, green, and blue phosphors 46 to excite the phosphors 46. At this time, visible light of any one of red, green, and blue colors is generated according to the phosphor 46. In the phosphor 46, red, green, and blue are sequentially arranged in sub-pixel units as shown in FIG. 6. For this reason, the electron beam 31 generated in any one subpixel or pixel is accelerated toward the phosphor 46.

Referring to FIG. 7, since electrons are generated and emitted along the interface of the cross-shaped hole 15 formed to expose the metal bus electrode 35 at the intersection, more electrons are emitted than the conventional tip type. In addition, the voltage becomes equal between the gate electrode 36 and the cathode electrode 30. In addition, when the voltage is applied to the cathode electrode 30 at a position slightly lower than the gate electrode 36, the electrons do not substantially move horizontally, but tunnel through the gate insulating layer 34 vertically. To use the effect. The gate electrode 36 is positioned slightly above the electrons to move upwards and at the same time the high pressure is applied to the anode electrode 44 to excite the phosphor to drive.

8A and 8E are diagrams showing step by step manufacturing method of the FED according to the present invention.

First, as shown in FIG. 8A, an electrode material is deposited on the lower glass substrate 38 and then patterned to form a cathode electrode 30. Then, an insulating material 34a is deposited on the cathode electrode 30 and the lower glass substrate 38. The entire surface is deposited by a predetermined thickness, and the electrode material 35a is deposited on the insulating material 34a as shown in FIG. 8B. The electrode material 35a is patterned as shown in FIG. 8C so that the metal bus electrode 35 is formed, and the insulating material 34a is etched using the metal bus electrode 35 as a mask. The etched insulating material 34a then forms the gate insulating layer 34. After the electrode material 36a is entirely deposited on the metal bus electrode 35 and the lower glass substrate 38 by a predetermined thickness as shown in FIG. 8D, the electrode material 36a is formed by photolithography. The gate electrode 36 is formed by patterning as shown in FIG. 8E. At this time, the cross-shaped hole 15 formed to expose the metal bus electrode is also patterned on the gate electrode at the same time. Such a FED manufacturing method is simple in structure and easy to manufacture. The driving voltage between the gate electrode and the cathode electrode can be reduced by controlling the thickness of the gate insulating layer. In other words, as the thickness of the insulating layer decreases, the voltage for tunneling electrons, that is, the driving voltage decreases. Therefore, the thinner the thickness of the gate insulating layer is, the lower voltage driving is possible, and the power consumption can be lowered.

A general driving method will be briefly described with reference to FIG. 9. FIG. 9 controls gradation and brightness by a supply pulse between the cathode electrode and the gate electrode. First, the cathode pulse width is fixed and the gate pulse width, which is the data, is controlled, so that a gray scale of 0-255 is possible according to the pulse width. The cathode electrode receives a scan pulse from a cathode driver not shown. At this time, image data is supplied to the gate electrode in synchronization with the scan pulse supplied to the cathode electrode. After the scanning of the entire line is completed, the pulses opposite to the scanning pulses are simultaneously applied to the entire cells to remove the charged particles of the cells charged through the gate insulating layer during the scan, thereby eliminating the charges accumulated in each cell, thereby increasing the high speed and low voltage. Drive it.

As a result, the field emission display device according to the present invention forms a cross-shaped hole to expose the metal bus electrode at the intersection of the cathode electrode and the gate electrode, so that the area intersecting between the two electrodes is reduced, and the electric field is distributed. Is widened so that many electrons can be emitted along the interface of the cruciform holes.

As described above, in the field emission display device according to the present invention, the concentration of the electric field is widely distributed along the interface of the cruciform holes on the gate electrode, so that a large number of electrons are emitted in the plane between the gate surface and the cathode electrode to realize high brightness. . In addition, as the area where the gate electrode and the cathode cross each other is narrowed, the capacitance component is reduced, thereby reducing power consumption and enabling high-speed response / driving. In addition, since a tunnel effect in which electrons move substantially vertically when a voltage is applied, problems caused by diffusion of an electron beam can be reduced. In addition, the manufacturing method is easy, and the thickness of the insulating layer is controlled to reduce driving voltage and power consumption due to the low voltage tunnel effect.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (3)

A plurality of cathode electrode lines, A cathode insulating layer formed on the cathode electrode line; A metal bus electrode formed on the cathode insulating layer to emit electrons; And a plurality of gate electrode lines intersecting the plurality of cathode electrode lines and exposing the metal bus electrodes at intersections thereof, wherein the electrons are emitted along an interface between the gate electrode lines and the exposed metal bus electrodes. A field emission display device, characterized in that. The method of claim 1, And the gate electrode line is formed such that the metal bus electrode is crosswise exposed at the intersection point, and the electrons are emitted along the cross-shaped interface of the exposed metal bus electrode. The method of claim 1, And the gate electrode line is formed to expose the metal bus electrode in an octagonal shape at the intersection point, and the electrons are emitted along the octagonal interface of the exposed metal bus electrode.

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