KR100709461B1 - Method of Forming Tungsten Gate - Google Patents
Method of Forming Tungsten Gate Download PDFInfo
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- KR100709461B1 KR100709461B1 KR1020010038022A KR20010038022A KR100709461B1 KR 100709461 B1 KR100709461 B1 KR 100709461B1 KR 1020010038022 A KR1020010038022 A KR 1020010038022A KR 20010038022 A KR20010038022 A KR 20010038022A KR 100709461 B1 KR100709461 B1 KR 100709461B1
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- South Korea
- Prior art keywords
- forming
- layer
- gate
- tungsten
- temperature
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 16
- 239000010937 tungsten Substances 0.000 title claims abstract description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 238000000137 annealing Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000004544 sputter deposition Methods 0.000 claims abstract description 6
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 229910007991 Si-N Inorganic materials 0.000 abstract description 9
- 229910006294 Si—N Inorganic materials 0.000 abstract description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 abstract description 4
- 238000007788 roughening Methods 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- -1 Tungsten nitride Chemical class 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
Abstract
본 발명은 반도체 소자의 텅스텐 게이트의 배리어 층을 형성하는 방법에 관한 것으로 후속 열공정에서 W-Si-N층을 형성하지 않고 W6층을 스퍼터링으로 증착하고 N2 분위기에서 어닐링을 수행함으로써 W6층을 W-Si-N층으로 전환시켜 인의 재분포를 방지하고 W-Si-N과 폴리실리콘막의 경계면이 거칠게 되는 것을 방지한다.The invention W 6 by depositing by sputtering a W 6 layer without forming a W-Si-N layer in a subsequent thermal process to a method of forming a barrier layer of tungsten of the semiconductor device gate and performing the annealing in the N 2 atmosphere, The layer is converted to a W-Si-N layer to prevent redistribution of phosphorus and to prevent roughening of the interface between W-Si-N and the polysilicon film.
Description
도 1a 내지 도 1e는 본 발명에 따른 텅스텐 게이트 전극 형성 방법에 의해 제조된 반도체 소자를 설명하기 위한 단면도.1A to 1E are cross-sectional views illustrating a semiconductor device manufactured by a tungsten gate electrode forming method according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10 : 반도체 기판 20 : 게이트산화막10 semiconductor substrate 20 gate oxide film
30 : 폴리실리콘막 40 : W6층30: polysilicon film 40: W 6 layer
50 : 텅스텐막50: tungsten film
본 발명은 반도체 소자의 게이트 형성 방법에 관한 것으로, 특히 텅스텐 게이트의 배리어 층을 형성하는 방법에 관한 것이다.The present invention relates to a method for forming a gate of a semiconductor device, and more particularly to a method for forming a barrier layer of a tungsten gate.
종래의 폴리실리콘 게이트의 RC 지연의 문제점을 해결하기 위해 W6/폴리실리콘의 폴리사이드 게이트를 이용하는데, W6를 이용한 게이트는 소자의 동작 속도는 증가하지만 하부의 폴리실리콘층과의 반응을 방지하기 위한 배리어층을 반드시 필요로 한다. 이러한 베리어층은 통상적으로 텅스텐 질화막이 사용되는데, 후속 열공 정에서 하부층인 폴리실리콘층과 반응하여 W-Si-N막이 형성되게 되고, 이 경우 폴리실리콘막 내부의 실리콘이 이동하면서 인(phosphorus)의 재분포가 발생하며, 폴리실리콘막의 표면이 거칠게 되어 게이트 식각 프로파일이 나빠진다는 문제점이 있었다.In order to solve the problem of the RC delay of the conventional polysilicon gate, a polyside gate of W 6 / polysilicon is used. The gate using W 6 increases the operation speed of the device but prevents reaction with the lower polysilicon layer. A barrier layer for this is necessary. Tungsten nitride film is generally used as the barrier layer. In a subsequent thermal process, a W-Si-N film is formed by reacting with a polysilicon layer, which is a lower layer, and in this case, silicon inside the polysilicon film moves to form phosphorus (phosphorus). Redistribution occurs, and the surface of the polysilicon film is rough, so there is a problem that the gate etching profile is bad.
본 발명은 이러한 문제를 해결하기 위해, 후속 열공정에서 W-Si-N층을 형성하지 않고 W6층을 스퍼터링으로 증착하고 N2 분위기에서 어닐링을 수행함으로써 W6 층을 W-Si-N층으로 전환시켜 인의 재분포를 방지하고 W-Si-N과 폴리실리콘막의 경계면이 거칠게 되는 것을 방지하는 텅스텐 게이트 형성 방법을 제공하는 것을 그 목적으로 한다.The present invention to solve this problem, a subsequent thermal process W-Si-N without forming a layer by depositing a W 6 layer by sputtering and to perform annealing in N 2 atmosphere W 6 layers a W-Si-N layer in the It is an object of the present invention to provide a method for forming a tungsten gate which prevents redistribution of phosphorus to prevent the redistribution of phosphorus and roughening the interface between W-Si-N and polysilicon film.
상기 목적을 달성하기 위해 본 발명에 따른 텅스텐 게이트 형성 방법은 반도체 기판 상에 게이트산화막 및 폴리실리콘막의 적층 구조를 형성하는 단계와, W6층을 형성하는 단계와, 어닐링을 수행하는 단계와, 텅스텐층을 형성하는 단계 및 식각 공정에 의해 게이트 전극을 형성하는 단계를 포함하는 것을 특징한다.In order to achieve the above object, a tungsten gate forming method according to the present invention comprises the steps of forming a laminated structure of a gate oxide film and a polysilicon film on a semiconductor substrate, forming a W 6 layer, performing annealing, tungsten Forming a layer and forming a gate electrode by an etching process.
이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
도 1a 내지 도 1e는 본 발명에 따른 텅스텐 게이트 전극 형성 방법에 의해 제조된 반도체 소자를 설명하기 위한 단면도들이다. 도 1a 내지 도 1d를 참조하면, 반도체 기판(10) 상에 게이트산화막(20) 및 폴리실리콘막(30)의 적층 구조를 형성한다(도 1a 참조). 폴리실리콘막(30)은 SiH4 및 SiH2Cl2 가스를 이용하여 500 내지 700℃의 온도 및 760Torr 이하의 압력에서 증착하는 것이 바람직하다. 그 다음에는 W6층(40)을 형성하는데 Ar 스퍼터링을 이용하여 300℃의 온도 및 10Torr 이하의 압력에서 증착하는 것이 바람직하다(도 1b 참조). 다음에는 어닐링 공정을 수행하여 W6층(40)을 W-Si-N층(45)으로 전환시킨다(도 1c 참조). 여기서 어닐링은 500 내지 900℃의 온도 및 N2 분위기에서 수행되는 RTP 공정이거나 동일한 온도 및 압력에서 퍼니스에서 수행되는 것이 바람직하다. 그 다음에 텅스텐막(50)을 형성하는데 Ar 스퍼터링을 이용하여 300℃의 온도 및 10Torr 이하의 압력에서 증착하는 것이 바람직하다(도 1d 참조). 게이트 마스크를 이용하여 식각 공정을 수행하여 게이트 전극을 형성한다(도 1e 참조).1A to 1E are cross-sectional views illustrating a semiconductor device manufactured by a tungsten gate electrode forming method according to the present invention. 1A to 1D, a stacked structure of a gate oxide film 20 and a polysilicon film 30 is formed on a semiconductor substrate 10 (see FIG. 1A). The polysilicon film 30 is preferably deposited at a temperature of 500 to 700 ° C. and a pressure of 760 Torr or less using SiH 4 and SiH 2 Cl 2 gas. It is then preferred to deposit at a temperature of 300 ° C. and a pressure of 10 Torr or less using Ar sputtering to form the W 6 layer 40 (see FIG. 1B). Next, an annealing process is performed to convert the W 6 layer 40 to the W-Si-N layer 45 (see FIG. 1C). The annealing here is preferably an RTP process carried out at a temperature of 500 to 900 ° C. and N 2 atmosphere, or preferably carried out in a furnace at the same temperature and pressure. Then, it is preferable to deposit at a temperature of 300 ° C. and a pressure of 10 Torr or less using Ar sputtering to form the tungsten film 50 (see FIG. 1D). An etching process is performed using the gate mask to form a gate electrode (see FIG. 1E).
이상에서 설명한 바와 같이, 본 발명에 따른 텅스텐 게이트 형성 방법은 하부의 폴리실리콘막으로부터 실리콘 및 인이 이동하는 것을 방지하며 W-Si-N과 폴리실리콘막의 경계면이 거칠게 되는 것을 방지하는 효과가 있다.As described above, the tungsten gate forming method according to the present invention has an effect of preventing silicon and phosphorus from moving from the lower polysilicon film and roughening the interface between W-Si-N and the polysilicon film.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010038022A KR100709461B1 (en) | 2001-06-29 | 2001-06-29 | Method of Forming Tungsten Gate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010038022A KR100709461B1 (en) | 2001-06-29 | 2001-06-29 | Method of Forming Tungsten Gate |
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| Publication Number | Publication Date |
|---|---|
| KR20030002423A KR20030002423A (en) | 2003-01-09 |
| KR100709461B1 true KR100709461B1 (en) | 2007-04-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1020010038022A KR100709461B1 (en) | 2001-06-29 | 2001-06-29 | Method of Forming Tungsten Gate |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10135460A (en) * | 1996-10-29 | 1998-05-22 | Internatl Business Mach Corp <Ibm> | Mosfet device and its manufacture |
| KR100197660B1 (en) * | 1996-05-22 | 1999-06-15 | 김영환 | Fabricating method of semiconductor device with tungsten silicide |
| KR20010004047A (en) * | 1999-06-28 | 2001-01-15 | 김영환 | Method of forming gate for semiconductor device |
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2001
- 2001-06-29 KR KR1020010038022A patent/KR100709461B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100197660B1 (en) * | 1996-05-22 | 1999-06-15 | 김영환 | Fabricating method of semiconductor device with tungsten silicide |
| JPH10135460A (en) * | 1996-10-29 | 1998-05-22 | Internatl Business Mach Corp <Ibm> | Mosfet device and its manufacture |
| KR20010004047A (en) * | 1999-06-28 | 2001-01-15 | 김영환 | Method of forming gate for semiconductor device |
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| KR20030002423A (en) | 2003-01-09 |
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