KR100197660B1 - Fabricating method of semiconductor device with tungsten silicide - Google Patents

Fabricating method of semiconductor device with tungsten silicide Download PDF

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Publication number
KR100197660B1
KR100197660B1 KR1019960017354A KR19960017354A KR100197660B1 KR 100197660 B1 KR100197660 B1 KR 100197660B1 KR 1019960017354 A KR1019960017354 A KR 1019960017354A KR 19960017354 A KR19960017354 A KR 19960017354A KR 100197660 B1 KR100197660 B1 KR 100197660B1
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layer
tungsten silicide
tungsten
semiconductor device
wny
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KR1019960017354A
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Korean (ko)
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KR970077210A (en
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엄금용
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer

Abstract

본 발면은 반도체소자의 텅스텐 실리사이드 제조방법에 관한 것으로, 텅스텐 실리사이드를 형성할 때 하부의 게이트 산화막으로 F가 침투되는 것을 해소하기 위하여 게이트를 형성할 때 폴리실리콘층 상부에 비정질상태의 WNy층을 성장한 다음, 그 상부에 텅스텐층을 성장시킨후, 열처리 공정으로 텅스텐 실리사이드를 형성하는 기술이다.The present invention relates to a method for manufacturing tungsten silicide of a semiconductor device, wherein an amorphous WNy layer is grown on top of a polysilicon layer when a gate is formed to eliminate the penetration of F into the gate oxide film at the bottom when the tungsten silicide is formed. Next, a tungsten silicide is formed by growing a tungsten layer thereon and then performing a heat treatment process.

Description

텅스텐 실리사이드를 갖는 반도체소자 제조방법Method of manufacturing semiconductor device having tungsten silicide

제1도는 종래의 기술로 폴리실리콘층 상부에 텅스텐 실리사이드막을 형성할 때 폴리실리콘층 그레인 바운다리를 통해 하부의 게이트 산화막 까지 F가 침투되는 것을 도시한 단면도.1 is a cross-sectional view showing that F is penetrated through a polysilicon layer grain boundary to a lower gate oxide layer when a tungsten silicide film is formed on the polysilicon layer according to a conventional technique.

제2도는 게이트 산화막으로 F가 침투 되는 경우 실리콘과 결합된 산소기가 떨어짐을 도시한 구조식.2 is a structural formula showing that the oxygen group combined with silicon falls when F is penetrated into the gate oxide film.

제3도는 제2도에서 산소기가 떨어진 곳으로 F또는 다른 불순물이 비정상적으로 결합된 것을 도시한 구조식.FIG. 3 is a structural formula showing abnormal combination of F or other impurities to the place where oxygen group is separated from FIG.

제4도 및 제5도는 본 발명에 의해 폴리실리콘층과 텅스텐 실리사이드막 사이에 비정질의 WNy층을 형성한 단면도.4 and 5 are cross-sectional views of the present invention in which an amorphous WNy layer is formed between a polysilicon layer and a tungsten silicide film.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1, 11 : 반도체 기판 2, 12 : 게이트 산화막1, 11: semiconductor substrate 2, 12: gate oxide film

3, 13 : 폴리실리콘층 14 : 비정질의 WNy층3, 13: polysilicon layer 14: amorphous WNy layer

4, 16 : 텅스텐 실리사이드막 15 : 텅스텐층4, 16: tungsten silicide film 15: tungsten layer

본 발명은 텅스텐 실리사이드를 갖는 반도체소자 제조방법에 관한 것으로, 특히 텅스텐 실리사이드막을 형성시 불소(F)가 게이트 산화막으로 침투되어 게이트 산화막의 특성이 저하되는 것을 방지하도록 텅스텐 실리사이드를 형성하는 반도체소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having tungsten silicide, and more particularly, to a method of manufacturing a semiconductor device in which tungsten silicide is formed to prevent fluorine (F) from penetrating into the gate oxide film and deteriorating the characteristics of the gate oxide film. It is about.

일반적으로 반도체소자에는 폴리실리콘층을 도전 배선으로 많이 이용하는데 반도체소자가 고집적화 됨에 따라 폴리실리콘층 도전배선의 선폭이 감소하여 저항이 증대된다. 이와같이 저항이 증대되는 것을 해소하기 위하여 금속 실리사이드를 폴리실리콘층 상부면에 형성하는 방법이 대두되었다.Generally, a polysilicon layer is used as a conductive wiring in a semiconductor device, and as the semiconductor device is highly integrated, the line width of the polysilicon layer conductive wiring is reduced, thereby increasing resistance. In order to eliminate such an increase in resistance, a method of forming a metal silicide on the upper surface of the polysilicon layer has emerged.

특별히 반도체소자의 게이트를 폴리실리콘층와 텅스텐 실리사이드가 적층되는 구조인 폴리사이드 구조를 널리 이용하고 있다.In particular, the gate of the semiconductor device is widely used a polyside structure, which is a structure in which a polysilicon layer and tungsten silicide are laminated.

상기와 같이 폴리사이드의 구성방법은 반도체기판 상부에 게이트 산화막을 형성하고, 그상부에 폴리실리콘층과 텅스텐층을 각각 증착한 다음, 열처리 공정으로 텅스텐 실리사이드(WSi2)를 형성한다.As described above, in the polyside construction method, a gate oxide film is formed on the semiconductor substrate, a polysilicon layer and a tungsten layer are deposited on the semiconductor substrate, and tungsten silicide (WSi 2 ) is formed by a heat treatment process.

텅스텐 실리사이드 형성방법은 다음(1)식과 같다.The tungsten silicide forming method is represented by the following equation (1).

한편, 텅스텐 실리사이드의 저저항 획득에 비하여 텅스텐 실리사이드를 형성하는 과정에서 F가 하부의 게이트 산화막으로 침투 되는 문제가 발생되고, 그로 인하여 게이트 산화막의 두께 증가(약 10-20A)의 원인이 되고 있으며, F와 실리콘의 본딩으로 절연 파괴 원인이 되어 생산성을 저하시키는 원인이 되고 있다.On the other hand, in the process of forming tungsten silicide, the problem that F penetrates into the gate oxide film at the lower side occurs in comparison with obtaining low resistance of tungsten silicide, thereby causing a thickness increase of the gate oxide film (about 10-20A). Bonding of F and silicon causes breakage of insulation, which causes a decrease in productivity.

따라서, 본 발명은 상기한 문제점을 해소하기 위하여 게이트를 형성할 때 폴리실리콘층 상부에 비정질상태의 WNy층을 성장한 다음, 그 상부에 텅스텐층을 성장시킨후 열처리 공정으로 텅스텐 실리사이드를 형성하는 반도체소자 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a semiconductor device for forming a tungsten silicide by heat treatment after growing an amorphous WNy layer on the polysilicon layer and then growing a tungsten layer on the polysilicon layer when forming a gate to solve the above problems. The purpose is to provide a manufacturing method.

상기한 목적을 달성하기 위한 본 발명은 반도체소자 제조방법에 있어서, 반도체기판상부에 게이트 산화막과 폴리실리콘층, 비정질의 WNy층 및 텅스텐층을 순차적으로 형성하는 단계와, 열처리 공정으로 상기 텅스텐층을 텅스텐 실리사이드층으로 형성하는 단계로 이루어진다.In accordance with another aspect of the present invention, a method of manufacturing a semiconductor device includes: sequentially forming a gate oxide film, a polysilicon layer, an amorphous WNy layer, and a tungsten layer on a semiconductor substrate; Forming a tungsten silicide layer.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제1도는 종래의 기술로 반도체 기판 상부에 폴리사이드를 형성한 단면도를 도시한 것으로, 반도체기판(1) 상부에 게이트 산화막(2)과 폴리실리콘층(3), 텅스텐층을 예를 들어 100-1500A의 두께로 증착하고, 열처리 공정을 실시하여 텅스텐 실리사이드막(4)을 형성할 때 텅스텐층에서 생성된 F가 저부에 있는 폴리실리콘층(3)의 그레인 바운다리를 통하여 하부에 게이트 산화막(2)으로 침투된다. 그로인하여 게이트 산화막(2)의 절연특성이 저하된다.FIG. 1 is a cross-sectional view of a polyside formed on a semiconductor substrate according to a conventional technique. The gate oxide film 2, the polysilicon layer 3, and the tungsten layer are formed on the semiconductor substrate 1, for example. When deposited to a thickness of 1500 A and subjected to a heat treatment process to form the tungsten silicide film 4, the F oxide generated in the tungsten layer is formed at the bottom through the grain boundary of the polysilicon layer 3 at the bottom thereof. Penetrate into) As a result, the insulating properties of the gate oxide film 2 are lowered.

제2도는 게이트 산화막(2)으로 F가 침투 되는 경우 실리콘과 결합된 산소기가 떨어짐을 도시한 구조식이다.FIG. 2 is a structural formula showing that the oxygen group combined with silicon falls when F penetrates into the gate oxide film 2.

제3도는 산소기가 떨어진 곳으로 F또는 다른 불순물이 비정상적으로 결합한 것을 도시한 구조식이다.FIG. 3 is a structural formula showing abnormal combination of F or other impurities to a place where an oxygen group is separated.

제4도는 및 제5도는 본 발명에 의해 텅스텐 실리사이드막을 형성하는 과정을 도시한 단면도이다.4 and 5 are cross-sectional views showing a process of forming a tungsten silicide film according to the present invention.

제4도는 반도체기판(11) 상부에 게이트 산화막(12)과 폴리실리콘층(13), 비정질의 WNy층(14)을 300-400℃의 온도에서 20-40A의 두께로 증착한다음, 그 상부에 텅스텐층(15)을 1000-1500A의 두께로 증착시킨 단면도이다.FIG. 4 deposits a gate oxide film 12, a polysilicon layer 13, and an amorphous WNy layer 14 on the semiconductor substrate 11 at a thickness of 20-40A at a temperature of 300-400 ° C. Is a cross-sectional view in which a tungsten layer 15 is deposited to a thickness of 1000-1500A.

상기의 비정질의 WNy층(14)을 형성하는 (2)식은 다음과 같다.Equation (2) for forming the amorphous WNy layer 14 is as follows.

제5도는 제4도 공정후 N2분위기, 800-900℃의 온도에서 약 30분 정도 열처리하여 텅스텐층(15)을 텅스텐 실리사이드층(16)으로 형성한 단면도로서, 상기 열처리 공정시 상기 비정질의 WNy층(14)은 폴리실리콘층(13) 계면에서 WSixNy층(14`)으로 변환되면서 일부의 WNy층(13)은 남아 있게된다. 상기 WSixNy층(14`)은 20-40A의 두께로 형성된다.FIG. 5 is a cross-sectional view of the tungsten layer 15 formed of the tungsten silicide layer 16 by heat treatment for about 30 minutes in an N 2 atmosphere and a temperature of 800-900 ° C. after the process of FIG. 4. The WNy layer 14 is converted to the WSi x Ny layer 14 ′ at the polysilicon layer 13 interface, leaving some WNy layer 13 remaining. The WSi x Ny layer 14 'is formed to a thickness of 20-40A.

상기와 같이 WSixNy층(14`)은 상부의 텅스텐층(15)에서 발생되는 F가 저부의 폴리실리콘층(3)으로 확산되는 것을 방지하는 역할을 하게 된다. 그로 인하여 F의 확산이 없고 낮은 저항성을 갖는 폴리사이드 구조의 게이트를 형성할 수가 있다.As described above, the WSixNy layer 14 ′ prevents F generated from the upper tungsten layer 15 from diffusing into the polysilicon layer 3 at the bottom. This makes it possible to form a gate having a polyside structure with no diffusion of F and low resistance.

참고로, 텅스텐층을 1000-1500A의 두께로 형성하는 비정질WNy층(14)은 20-40A의 두께로 형성하여야 F의 확산이 되지 못하게 된다. 또한, 상기 WSxNy층(14`)에 Ny는 F를 블로킹한 다음, 이후에 증발되며, W분자는 Si와 결합하여 최종적으로는 WsixNy또는 WNy는 거의 소모하게 되어 게이트 전극 구조는 폴리실리콘층, 텅스텐 실리사이드층의 적층구조가 된다.For reference, the amorphous WNy layer 14 forming the tungsten layer to a thickness of 1000-1500A should be formed to a thickness of 20-40A to prevent the diffusion of F. In addition, Ny blocks F in the WS x Ny layer 14 'and then evaporates thereafter. W molecules are combined with Si, and finally Wsi x Ny or WNy is almost consumed. It becomes a laminated structure of a silicon layer and a tungsten silicide layer.

상기한 본 발명에 의하면 텅스텐 실리사이드를 형성하는 과정에서 하부의 게이트 산화막으로 F가 침투되는 것을 방지할 수가 있으며, 그로 인하여 게이트 산화막의 특성을 향상시켜서 반도체 소자의 신뢰성을 향상시킬 수가 있다.According to the present invention described above, F can be prevented from penetrating into the lower gate oxide film during the formation of tungsten silicide, thereby improving the reliability of the semiconductor device by improving the characteristics of the gate oxide film.

Claims (4)

반도체소자 제조방법에 있어서, 반도체기판상부에 게이트 산화막과 폴리실리콘층, 비정질의 WNy층 및 텅스텐층을 순차적으로 형성하는 단계와, 열처리 공정으로 상기 텅스텐층을 텅스텐 실리사이드층으로 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체소자 제조방법.A method of manufacturing a semiconductor device comprising the steps of sequentially forming a gate oxide film, a polysilicon layer, an amorphous WNy layer, and a tungsten layer on a semiconductor substrate, and forming the tungsten layer as a tungsten silicide layer by a heat treatment process. A semiconductor device manufacturing method characterized in that. 제1항에 있어서, 상기 비정질의 WNy층은 7SiH2Cl2+ 2WF6+ NH3의 가스를 공급하여 증착하는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the amorphous WNy layer is deposited by supplying a gas of 7SiH 2 Cl 2 + 2WF 6 + NH 3 . 제1항에 있어서, 상기 WNy층은 20-40A의 두께로 형성하고, 상기 텅스텐층은 1000-1500A의 두께로 형성하는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the WNy layer is formed to a thickness of 20-40A, and the tungsten layer is formed to a thickness of 1000-1500A. 제1항에 있어서, 상기 열처리 공정은 N2분위기와 800-900℃의 온도에서 실시하는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the heat treatment is performed at a temperature of N 2 and 800-900 ° C. 6.
KR1019960017354A 1996-05-22 1996-05-22 Fabricating method of semiconductor device with tungsten silicide KR100197660B1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100548538B1 (en) * 1999-06-28 2006-02-02 주식회사 하이닉스반도체 Method of forming gate for semiconductor device
KR100709461B1 (en) * 2001-06-29 2007-04-18 주식회사 하이닉스반도체 Method of Forming Tungsten Gate
KR101001151B1 (en) 2008-07-23 2010-12-15 주식회사 하이닉스반도체 Method for fabricating semiconductor device and non-volatile random access memory

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