KR100707627B1 - Light emitting display and driving method thereof - Google Patents

Abstract

The present invention relates to a light emitting display device, comprising: a pixel portion including a pixel receiving a data signal by a scan signal and emitting light by a current corresponding to the data signal, and outputting a plurality of first light emission control signals to the pixel portion A first light emission control driver, a second light emission control driver for outputting a plurality of second light emission control signals to the pixel portion, and the first light emission control driver and the second light emission control driver alternately for one horizontal period; And a controller configured to generate a light emission control signal and a control signal to output the second light emission control signal, wherein the pixel receives the first light emission control signal and the second light emission control signal and emits light. An emission control signal is inverted and transmitted to the pixel, and a method of driving the same is provided.

Bidirectional, emission control signal, delay

Description

LIGHT EMITTING DISPLAY AND DRIVING METHOD THEREOF

1 is a structural diagram showing a structure of a light emitting display device according to the prior art.

2 is a structural diagram showing a structure of a light emitting display device according to the present invention.

3 is a structural diagram illustrating a structure of a control unit employed in the light emitting display device of FIG. 2.

4A and 4B are structural diagrams showing a first embodiment of the light emission control driver employed in the light emitting display device of FIG.

5 is a signal diagram illustrating a signal input to the light emission control driver illustrated in FIGS. 4A and 4B.

6 is a circuit diagram illustrating a first embodiment of a pixel employed in a light emitting display device according to the present invention.

7 is a signal diagram illustrating a signal input to the pixel of FIG. 6.

8 is a view showing a second embodiment of a pixel employed in the light emitting device according to the present invention.

9 is a signal diagram illustrating a signal input to the pixel of FIG. 8.

*** Explanation of symbols on main parts of drawings ***

100: pixel portion 110: light emitting element

200: data driver 300: scan driver

310: first light emission control driver 320: second light emission control driver

400: control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting display device, and more particularly, to a light emitting display device and a driving method thereof, by providing a light emission control signal in both directions of the light emitting display device to prevent the light emission control signal from being delayed to the pixel by the load of the light emission control line. .

Recently, various flat panel display devices having a smaller weight and volume than the cathode ray tube have been developed. In particular, a light emitting display device having excellent luminous efficiency, brightness, viewing angle, and fast response speed has been attracting attention.

The light emitting device has a structure in which a light emitting layer, which is a thin film that emits light, is positioned between a cathode electrode and an anode electrode, and excitons are generated by injecting electrons and holes into the light emitting layer to recombine them, and the excitons fall to low energy to emit light. have.

In the light emitting device, the light emitting layer is formed of an inorganic material or an organic material, and is classified into an inorganic light emitting device and an organic light emitting device according to the type of light emitting layer.

1 is a structural diagram showing a structure of a light emitting display device according to the prior art. Referring to FIG. 1, a light emitting display device according to the related art includes a pixel portion 10 in which an image is displayed by a plurality of pixels, a data driver 20 applying a data signal to the pixel portion 10, and a pixel portion. And a scan driver 30 for selecting the pixel of 10 to apply the data signal to the selected pixel.

In the pixel unit 10, a plurality of pixels 11 are arranged and a light emitting device OLED is connected to each pixel 11. And n scan lines S1, S2, ... Sn-1, Sn formed in the row direction and transmitting the scan signal, and m data lines D1, D2, forming the column direction and transmitting the data signal. ... Dm-1, Dm) and M power supply lines (not shown) for transferring pixel power are arranged. The pixel unit 10 emits light by the scan signal, the data signal, and the pixel power source to display an image.

The data driver 20 is a means for applying a data signal to the pixel unit 10. The data driver 20 is connected to the data lines D1, D2,... Dm-1, Dm of the pixel unit 10. Connected to apply a data signal to the pixel portion 10.

The scan driver 30 is a means for sequentially outputting scan signals, and the scan driver 30 scan lines S1, S2, ... Sn-1, Sn and the emission control lines E1, E2, ... En -1, En) to transmit a scan signal and a light emission control signal to a specific row of the pixel portion 10. The data signal input from the data driver 20 is applied to a specific row of the pixel unit 10 to which the scan signal is transmitted, and a current is generated in the pixel, and the generated current is transmitted to the light emitting element by an emission control signal to display an image. Will be displayed. At this time, all the rows emit light sequentially to complete one frame. The scan signal and the light emission control signal are input in the form of pulses.

In the conventional light emitting display device having the above configuration, a plurality of pixels are connected to the emission control line, and the emission control signal is input to the pixel in one direction of the emission control line. The pixel includes a resistance component and a capacitor component, and the emission control signal transmitted through the emission control line by the resistance component and the capacitor component is gradually increased, so that the response speed of the pixel is slowed down by the emission control signal.

In particular, as the light emitting display device gradually increases in size and the number of pixels gradually increases, the resistance component and the capacitor component of the pixel unit 100 become larger, so that the response speed due to the light emission control signal becomes more important.

Accordingly, the present invention has been made to solve the problems of the prior art, and an object of the present invention is to input a light emission control signal in both directions of a pixel portion to delay the light emission control signal generated by a load formed on the light emission control line. The present invention provides a light emitting display device and a driving method thereof to prevent a delay in response speed of a pixel and to improve a switching characteristic of a transistor by implementing a transistor controlled by a light emission control signal as a symmetry transistor.

In order to achieve the above object, a first aspect of the present invention provides a pixel unit including a pixel that receives a data signal by a scan signal and emits light by a current corresponding to the data signal; A first emission control driver for outputting an emission control signal, a second emission control driver for outputting a plurality of second emission control signals to the pixel portion, and the first emission control driver and the second emission control driver for one horizontal period; And a control unit for generating a control signal for alternately outputting the first emission control signal and the second emission control signal, wherein the pixel receives the first emission control signal and the second emission control signal and emits light. The second emission control signal is inverted to provide a light emitting display device which is transferred to the pixel.

According to a second aspect of the present invention, a pixel portion including a pixel which receives a data signal by a scan signal and emits light by a current corresponding to the data signal, generates an emission control signal consisting of a pulse wave and divides the pulse into A first light emission control driver including a first switching unit for generating a first light emission control signal composed of a front end of a pulse, and a light emission control signal consisting of a pulse wave and dividing the pulse into a second light emission consisting of a rear end of the pulse A second light emission control driver including a second switching unit to generate a control signal, and a control unit configured to transmit a control signal to control the first switching unit and the second switching unit, wherein the pixel is connected to the first light emission control signal. The second emission control signal is received and emits light, and the second emission control signal is inverted and transmitted to the pixel. To provide an optical display device.

According to a third aspect of the present invention, a method of transmitting a scan signal to select a pixel to form a current corresponding to a data signal, and splitting one emission control signal to form a first emission control signal and a second emission control signal Transmitting the first emission control signal to one end of the emission control line, the second emission control signal to the opposite end of the emission control line, and inverting and receiving the second emission control signal from the pixel; The current is transmitted to the light emitting device by the first light emission control signal and the second light emission control signal to provide the light emitting device to emit light.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a structural diagram showing a structure of a light emitting display device according to the present invention. Referring to FIG. 2, the light emitting display device according to the present invention includes a pixel unit 100, a data driver 200, a scan driver 300, a first light emission control driver 310, and a second light emission control driver 320. ) And the control unit 400.

The pixel unit 100 includes a plurality of scan lines S0, S1, S2, ... Sn-1, Sn, a plurality of data lines D1, D2, ... Dm-1, Dm, and emission control lines E1. And a plurality of pixels 110 defined by E2, ... En-1, En). Each of the pixels 110 receives the first and second scan signals from the scan driver 300 through the scan lines S0, S1, S2, ... Sn-1, Sn and the first and second scan signals. The pixels 110 are selected by the pixel 110, and the selected pixel 110 receives a data signal supplied from the data driver 200 through the data lines D1, D2,... Generate a corresponding current. The first and second light emission control drivers 310 and 320 generate a light emission control signal and apply the current generated according to the light emission control signal transmitted through the light emission control lines E1, E2, ... En-1, En. The light is emitted to display an image.

The data driver 200 is positioned on one side of the pixel unit, receives digital video data, converts the digital video data into a data signal, and supplies the digital video data to the data lines D1, D2,..., Dm-1, Dm. In this case, the data driver 200 may be mounted on a substrate including the pixel unit 100 or installed outside the substrate.

The scan driver 300 is positioned on one side of the pixel unit 100 and generates a scan signal and transfers the scan signal to the scan lines S0, S1, S2, ... Sn-1, Sn, and transmits the data to the pixel to which the scan signal is transmitted. Allow signal to be delivered. In addition, the scan driver 300 may include a light emission control circuit driver.

The first and second emission control drivers 310 and 320 are disposed on both sides of the pixel unit 100 and sequentially emit the emission control lines E1, E2, ... En-1, En in response to a start pulse and a clock signal. A light emission control signal for driving is generated and sequentially supplied to the light emission control lines E1, E2, ... En-1, En. In this case, the emission control signal is divided into a first emission control signal and a second emission control signal, and the first emission control driver 310 outputs the first emission control signal and the second emission control driver 320 outputs the second emission control signal. Output the signal. The first emission control signal is output before the second emission control signal, so that one emission control signal is completed by the first emission control signal and the second emission control signal, and the pixel 110 is selected by the completed emission control signal. do.

The controller 400 outputs a first control signal for controlling the first light emission control driver 310 and a second control signal for controlling the second light emission control driver 320. By the first control signal and the second control signal, the first and second light emission control drivers 310 and 320 are turned on at different times to output the first and second light emission control signals at different times, respectively.

3 is a structural diagram illustrating a structure of a control unit employed in the light emitting display device of FIG. 2. Referring to FIG. 3, the controller 400 receives the clock signal CLK and outputs a first control signal Φ and a second control signal Φ.

The control unit 400 includes a first NAND gate and a second NAND gate having two input terminals and one output terminal, and includes three inverters at an output terminal of the first NAND gate. The buffers are connected in series, and three buffers configured as inverters are connected in series at the output terminal of the second NAND gate. The clock signal is input to one input terminal of the first NAND gate, and the output signal of the second inverter among the inverters connected to the output terminal of the second NAND gate is input to the other input terminal. In addition, a clock signal CLK is input to one input terminal of the second NAND gate, and a clock bar signal is inputted through the inverter 413, and the other input terminal is connected to an output terminal of the first NAND gate. The output signal of the second buffer of the buffers is input.

The controller 400 configured as described above outputs the first control signal Φ 1 and the second control signal Φ 2 shown in FIG. 5 to the first emission control driver 310 and the second emission control driver 320. Enter it. The second control signal .phi.2 becomes a subsignal of the first control signal .phi.1.

4A and 4B are structural diagrams showing a first embodiment of a light emission control circuit employed in the light emitting display device of FIG. 4A illustrates the first emission control driver 310 and FIG. 4B illustrates the second emission control driver 320. Referring to FIGS. 4A and 4B, the first light emission control driver 310 includes a first shift register 311, a first buffer 312, and a first switching unit 313 and a second light emission control. The driver 320 includes a second shift register unit 321, a second buffer unit 322, and a second switching unit 323.

When the start pulse SP is input to the first shift register 311, the first light emission control driver 310 receives the first shift signal sr1 by shifting the start pulse SP. The second shift signal sr2, the third shift signal sr3, and the fourth shift signal sr4 are sequentially output.

In the first buffer unit 312, even-numbered inverters are connected in series and receive a first shift signal sr1, a second shift signal sr2, a third shift signal sr3, and a fourth shift signal sr4. It transfers to the first switching unit 313.

In this case, the first switching unit 313 is switched by the first control signal Φ 1, and the first switching unit 313 is configured such that the N MOS transistor is connected to each emission control line. The first control signal Φ 1 is transmitted to the gate of the N MOS transistor, and when the first control signal Φ 1 is a high signal, a signal is output to the emission control line and is output by the first switching unit 313. Splits the pulse of each shift signal to generate a plurality of first light emission control signals e11, e12, e13, e14 from which the preceding portion of the pulse is output.

When the start pulse SP is input to the second shift register unit 321, the second light emission control driver 320 receives the first shift signal sr1 shifted by the start pulse SP. The second shift signal sr2, the third shift signal sr3, and the fourth shift signal sr4 are sequentially output.

In addition, the second buffer unit 322 is connected to an even number of inverters in series and receives the first shift signal sr1, the second shift signal sr2, the third shift signal sr3, and the fourth shift signal sr4. The transfer to the second switching unit 323.

In this case, the second switching unit 323 switches by the second control signal .phi.2, and the second switching unit 323 is configured to form N MOS transistors in each emission control line. The second control signal Φ 2 is transmitted to the gate of the N MOS transistor, and when the second control signal Φ 2 is a high signal, a signal is output to the emission control line and is output by the second switching unit 323. Splits the pulse of each shift signal to generate a plurality of second light emission control signals e21, e22, e23, e24 to which the rear part of the pulse is output.

5 is a signal diagram illustrating a signal input and output to the light emission control circuit shown in FIGS. 4A and 4B. Referring to FIG. 5, a start pulse SP, a clock CLK, a first control signal Φ 1, and a second control signal Φ 2 are input to the first and second light emission control drivers 310 and 320. A first shift signal sr1, a second shift signal sr2, a third shift signal sr3, a fourth shift signal sr4, a plurality of first emission control signals e11, e12, e13, e14, and a plurality of Second emission control signals e21, e22, e23, and e24. The dotted line indicates that the first light emission control driver 310 or the second light emission control driver 320 is turned off so that no signal is output.

Since the first emission control driver 310 and the second emission control driver 320 operate using the same start pulse SP and the clock CLK, the first emission control driver 310 and the second emission control driver 320 generate the same first to fourth shift signals sr1 to sr4. . The first light emission control driver 310 outputs a plurality of first light emission control signals e11, e12, e13, and e14 by the first control signal. The control driver 320 outputs a plurality of second light emission control drivers e21, e22, e23, and e24. The first emission control signal and the second emission control signal are combined to form one emission control signal.

In addition, the first emission control driver 310 and the second emission control driver 320 are located at both sides of the pixel unit 100 to transmit the first emission control signal and the second emission control signal through one emission control line. Therefore, the light emission control signal is transmitted from both sides of the light emission control line, and the problem of delaying the light emission control signal transmitted to the pixel far from the light emission control circuit by the resistance component of the pixel unit 100 and the capacitor formation is solved.

7 is a circuit diagram illustrating a first embodiment of a pixel employed in a light emitting display device according to the present invention. Referring to FIG. 7, the pixel 110 includes a light emitting element OLED and a pixel circuit 115, and the pixel circuit 115 includes first to fifth transistors M1 to M5 and first and second electrodes. Capacitors Cst and Cvth. The first to fourth transistors M1 to M4 are implemented as P MOS transistors, and the fifth transistor M5 is implemented as a CMOS transistor in which an N MOS transistor and an N MOS transistor are connected.

The first transistor M1 has a source connected to a first power source ELVdd, a drain connected to a first node A, a gate connected to a second node B, and a voltage applied to the second node B. This causes the current to flow from the source to the drain.

The second transistor M2 has a source connected to the data line Dm, a drain connected to the third node C, a gate connected to the first scan line Sn, and transferred through the first scan line Sn. The data signal is selectively transmitted to the third node C by one scanning signal.

The third transistor M3 has a source connected to the first node A, a drain connected to the second node B, a gate connected to the second scan line Sn-1, and a second scan line Sn-1. The first transistor M1 is selectively diode-connected by the second scan signal transmitted through the second scan signal.

The fourth transistor M4 has a source connected to the first power supply ELVdd, a drain connected to the third node C, and a gate connected to the second scan line Sn-1, so that the second scan line Sn-1 The voltage of the first power source ELVdd is selectively transferred to the third node C by the second scan signal transmitted through the second scan signal.

In the fifth transistor M5, a source is transferred to the first node A, a drain is connected to an anode electrode of the light emitting device OLED, and a gate is connected to an emission control line En to selectively emit an emission control line En. The current flowing in the direction from the source to the drain of the first transistor M1 is selectively transmitted to the light emitting device OLED by the light emission control signal transmitted through the light emitting control signal. The gate formed in the P MOS transistor of the fifth transistor M5 is directly connected to the light emission control line, and the gate formed in the N MOS transistor is connected to the light emission control line through an inverter (in).

When the first capacitor Cst has a first electrode connected to a first power source ELVdd and a second electrode connected to a third node C to transmit a data signal to the third node C, the data signal and the first The predetermined voltage is stored by the voltage of the power supply ELVdd.

In the second capacitor Cvth, the first electrode is connected to the third node C and the second electrode is connected to the second node B so that the first transistor M1 is diode-connected by the third transistor M3. In this case, the threshold voltage of the first transistor M1 is stored.

In the light emitting device OLED, the anode electrode is connected to the first node A, and the cathode electrode is connected to the second power source ELVss to emit light by the current flowing from the first node A. FIG.

8 is a signal diagram illustrating a signal input to the pixel of FIG. 7. Referring to FIG. 8, the pixel operates by the first and second scan signals sn and sn-1, the data signal, and the light emission control signal en. The first and second scan signals sn and sn-1 and the emission control signal en are periodic signals.

First, when the first scan signal sn and the emission control signal en become the high signal, and the second scan signal sn-1 becomes the low signal, the third transistor (sn-1) causes the third transistor ( M3 and the fourth transistor M4 are turned on so that the first transistor M1 is diode connected and the first power source ELVdd is transferred to the first electrode of the second capacitor Cvth. At this time, a voltage corresponding to the difference between the threshold voltages of the first power supply ELVdd and the first transistor M1 is applied to the second node B, and the threshold voltage of the first transistor M1 is applied to the second capacitor Cvth. Corresponding voltage is stored.

Thereafter, when the first scan signal sn becomes a low signal in the first section T1 and the first light emission control signal en that is high with the second scan signal sn-1 is transmitted, the first scan signal The second transistor M2 is turned on by the sn, and the data signal is transmitted to the third node C. The first power source ELVdd is transmitted to the first electrode of the first capacitor Cst, and the second transistor M2 is turned on. The data signal is transmitted to the electrode. Therefore, the voltage corresponding to the difference between the pixel power supply and the data signals ELVdd-Vdata is stored in the first capacitor Cst.

At this time, a voltage corresponding to Equation 1 below is applied between the gate source of the first transistor M1 by the first capacitor Cst and the second capacitor Cvth connected in series.

Here, Vgs corresponds to the voltage between the gate sources of the first transistor M1, ELVdd corresponds to the voltage of the first power supply, Vdata corresponds to the voltage of the data signal, and Vth corresponds to the threshold voltage of the first transistor M1.

At this time, in the fifth transistor M5 implemented with the N MOS transistor and the P MOS transistor, the first emission control signal becomes a high signal, the P MOS transistor is turned off, and the N MOS transistor is a high signal by the inverter in. Is switched to the low signal and inputted, so that the fifth transistor M5 is maintained in the off state. Therefore, inflow of current into the light emitting device OLED is blocked by the fifth transistor M5.

In addition, in the second period T2, the first scan signal sn becomes a low signal and the second scan signal sn-1 is transmitted so that the voltage corresponding to Equation 1 is the gate of the first transistor M1. Passed between sources. At this time, when the second light emission control signal that is high is transmitted, the fifth light emission control signal of the fifth transistor M5, which is implemented by the N MOS transistor and the P MOS transistor, becomes the high signal and the P MOS transistor is turned off. The MOS transistor is inputted by the high signal being converted into the low signal by the inverter in so that the fifth transistor M5 is maintained in the off state. Therefore, the inflow of current into the light emitting device OLED is blocked by the fifth transistor M5.

When the first emission control signal and the second emission control signal are both low signals, current flows into the PMOS transistor region of the fifth transistor into the light emitting device OLED. The current flowing into the light emitting device OLED corresponds to Equation 2 below.

Where Vgs is the voltage between the gate sources of the first transistor M1, Vdd is the voltage of the pixel power source, Vdata is the voltage of the data signal, Vth is the threshold voltage of the first transistor M1, and β is the first transistor M1. Corresponds to the gain factor of.

Therefore, the current flowing into the light emitting device OLED flows regardless of the threshold voltage of the first transistor M1. Therefore, a current compensated for the threshold voltage flows to the first node A. FIG.

In the fifth transistor M5, an N-MOS transistor and a P-MOS transistor are coupled to each other, and electrons, which are carriers of the N-MOS transistor, and holes that are carriers of the P-MOS transistor, interact with each other, resulting in device characteristics of the fifth transistor M5. Is improved.

9 is a diagram illustrating a second embodiment of a pixel employed in the light emitting device according to the present invention, and FIG. 10 is a signal diagram illustrating a signal input to the pixel of FIG. 9. Referring to FIGS. 9 and 10, unlike the pixel illustrated in FIG. 7, the first through fourth transistors M1 through M4 are implemented as N MOS transistors, and as shown in FIG. 10, the first and second transistors are illustrated in FIG. 10. The scan signals sn and sn-1 and the emission control signal en are input and operated.

While preferred embodiments of the present invention have been described using specific terms, such descriptions are for illustrative purposes only and it is understood that various changes and modifications may be made without departing from the spirit and scope of the following claims. You must lose.

According to the light emitting display device and the driving method thereof according to the present invention, it is possible to prevent the light emitting control call from being delayed by the load of the pixel portion by applying the light emission control signal in both directions and increasing the size and providing high definition image quality. .

In addition, the transistor controlled by the emission control signal is implemented as a symmetry transistor to improve the switching characteristics of the transistor.

Claims (15)

A pixel unit including a pixel which receives a data signal by a scan signal and emits light by a current corresponding to the data signal; A first emission control driver for outputting a plurality of first emission control signals to the pixel portion; A second emission control driver for outputting a plurality of second emission control signals to the pixel portion; And A control unit for generating a control signal for controlling the first light emission control driver and the second light emission control driver to output the first light emission control signal and the second light emission control signal alternately for one horizontal period; The pixel emits light by receiving the first emission control signal and the second emission control signal, and the second emission control signal is inverted and transferred to the pixel. The method of claim 1, The control unit A first NAND gate, a second NAND gate, a first inverter connected to an output terminal of the first NAND gate, and a second inverter connected to an output terminal of the second NAND gate, And the first NAND gate receives a clock signal and an output signal of the second NAND gate, and the second NAND gate receives a clock signal and an output signal of the first NAND gate. The method of claim 1, The control signal is divided into a first control signal and a second control signal, and the second control signal is a sub-signal of the first control signal. The method of claim 1, The first light emission control driver A first shift register unit for shifting a start pulse and sequentially outputting a plurality of shift signals; and dividing the shift signal through the first control signal to generate a first emission control signal composed of a front end of the shift signal; A first switching unit, The second light emission control driver A second shift register unit for shifting the start pulse to sequentially output a plurality of shift signals, and dividing the shift signal through the second control signal to generate a second emission control signal consisting of a rear end of the shift signal; A light emitting display device comprising a second switching unit. The method of claim 4, wherein The first and second switching units include a transistor. A pixel unit including a pixel which receives a data signal transmitted by a scan signal and emits light by a current corresponding to the data signal; A first light emission control driver including a first switching unit generating a light emission control signal consisting of a pulse wave and dividing the pulse into two to generate a first light emission control signal consisting of the front end of the pulse; A second light emission control driver including a second switching unit generating a light emission control signal consisting of pulse waves and dividing the pulse into two to generate a second light emission control signal consisting of a rear end of the pulse; And It includes a control unit for transmitting a control signal for controlling the first switching unit and the second switching unit, The pixel emits light by receiving the first emission control signal and the second emission control signal, and the second emission control signal is inverted and transferred to the pixel. The method of claim 6, The control unit A first NAND gate, a second NAND gate, a first inverter connected to an output terminal of the first NAND gate, and a second inverter connected to an output terminal of the second NAND gate, And the first NAND gate receives a clock signal and an output signal of the second NAND gate, and the second NAND gate receives a clock signal and an output signal of the first NAND gate. The method of claim 6, The control signal is divided into a first control signal and a second control signal, and the second control signal is a sub-signal of the first control signal. The method of claim 6, The first light emission control driver A first shift register unit for shifting a start pulse and sequentially outputting a plurality of shift signals; and dividing the shift signal through the first control signal to generate a first emission control signal composed of a front end of the shift signal; A first switching unit, The second light emission control driver A second shift register unit for shifting the start pulse to sequentially output a plurality of shift signals, and dividing the shift signal through the second control signal to generate a second emission control signal consisting of a rear end of the shift signal; A light emitting display device comprising a second switching unit. The method of claim 6, The first and second switching units include a transistor. The method according to claim 1 or 6, And a data driver for transmitting a scan signal and a data driver for transmitting a data signal to the pixel unit. The method according to claim 1 or 6, And a first light emission control driver and a second light emission control driver formed on both sides of the pixel portion. The method according to claim 1 or 6, The pixel is Light emitting device for emitting light according to the flow of current; A first transistor for generating said current by a voltage applied to a gate; A second transistor which transfers a data signal by a first scan signal to a gate of the first transistor; A first capacitor for storing a voltage corresponding to a difference between a first power supply and the data signal; A second capacitor storing the threshold voltage of the first transistor; A third transistor configured to diode-connect the first transistor by a second scan signal such that the threshold voltage of the first transistor is stored in the second capacitor; A fourth transistor configured to store a voltage corresponding to a difference between the first power supply and the data signal in the first capacitor by the second scan signal; And A fifth transistor configured to transmit the current to the light emitting device by the first light emission control signal and the second light emission control signal; The fifth transistor is implemented as a CMOS transistor in which a P-MOS transistor and an N-MOS transistor are combined. An inverter is connected to a gate of the N-MOS transistor so that the second emission control signal is inverted and transferred to the gate of the N-MOS transistor. Light emitting display. Transferring a scan signal to select a pixel to form a current corresponding to the data signal; Dividing one emission control signal to form a first emission control signal and a second emission control signal; Transmitting the first emission control signal to one end of an emission control line, the second emission control signal to an opposite end of the emission control line, and inverting and receiving the second emission control signal from the pixel; And And transmitting the current to the light emitting device by the first light emitting control signal and the second light emitting control signal to cause the light emitting device to emit light. delete

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