KR100581808B1 - Light emitting display by using demultiplexer - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting display device using a demultiplexer, comprising: a pixel unit displaying an image, a scan driver transferring a scan signal, a data driver transferring a data signal to a plurality of first data lines, and applied to the first data line And a demultiplexer unit having a plurality of demultiplexers for demultiplexing the data signals to be transmitted to a plurality of second data lines, wherein the pixel unit is connected to at least two adjacent pixels with different scan lines and different second data lines. The second data lines may be connected to the first data lines through the demultiplexer.

Therefore, current flows through the OLED regardless of the threshold voltage of the pixel power supply and the driving transistor, and the data signal is transmitted through the demultiplexer to transmit the data signal to more data lines than the number of output lines of the data driver, thereby reducing manufacturing costs. can do.

Demultiplexer, Luminescent, Organic, Pixel

Description

Light emitting display device using demultiplexer {LIGHT EMITTING DISPLAY BY USING DEMULTIPLEXER}

1 is a circuit diagram illustrating a pixel of a light emitting display device according to the related art.

2 is a structural diagram showing a structure of an embodiment of a light emitting display device using a demultiplexer according to the present invention.

3 is a circuit diagram illustrating a pixel used in the light emitting display device of FIG. 2.

4 is a timing diagram illustrating an operation of a pixel of FIG. 3.

FIG. 5 is a diagram illustrating an embodiment of a demultiplexer employed in the light emitting display device of FIG. 2.

6 is a circuit diagram illustrating an example embodiment of a pixel unit coupled to a demultiplexer employed in a light emitting display according to the present invention.

FIG. 7 is a timing diagram illustrating an operation of the circuit of FIG. 6.

FIG. 8 is a block diagram illustrating a portion of the scan driver employed in the light emitting display device of FIG. 2.

9 is a timing diagram illustrating an operation of the scan driver of FIG. 8.

10 is a comparative example with a light emitting display device using a demultiplexer according to the present invention.

FIG. 11 is a circuit diagram illustrating a pixel unit coupled to a demultiplexer employed in the comparative example of FIG. 10.

12 is a timing diagram illustrating an operation of the pixel unit illustrated in FIG. 11.

*** Description of the main parts of the drawings

100: pixel portion 110: pixel

200: data driver 210: demultiplexer

300: scan driver 400: controller

The present invention relates to a light emitting display device, and more particularly, to a light emitting display device using a demultiplexer for selectively transmitting a data signal transmitted from a data driver to a pixel through a demultiplexer.

Recently, various flat panel display devices having a smaller weight and volume than the cathode ray tube have been developed. In particular, a light emitting display device having excellent luminous efficiency, brightness, viewing angle, and fast response speed has been attracting attention.

The light emitting device has a structure in which a light emitting layer, which is a thin film that emits light, is positioned between a cathode electrode and an anode electrode, and excitons are generated by injecting electrons and holes into the light emitting layer to recombine them, and the excitons fall to low energy to emit light. It is.

In the light emitting device, the light emitting layer is formed of an inorganic material or an organic material, and is classified into an inorganic light emitting device and an organic light emitting device according to the type of light emitting layer.

1 is a circuit diagram illustrating a pixel of a light emitting display device according to the related art. Referring to FIG. 1, three pixels adjacent from right to left are referred to as a first pixel, a second pixel, and a third pixel, and each pixel has the same configuration and performs the same operation. Each pixel includes an organic light emitting device (hereinafter referred to as OLED), a driving transistor (Thin Film Transistor M2), a capacitor Cst, and a switching transistor M1. The scanning line Sn, the data line Dm, and the power supply line Vdd are connected to the pixel. The scanning line Sn is formed in the row direction, and the data line Dm and the power supply line Vdd are formed in the column direction. Where n is any integer between 1 and N, and m is any integer between 1 and M.

The first pixel has a first switching transistor connected to a red data line RDm, the second pixel has a first switching transistor connected to a green data line Dm + 1_G, and the third pixel has a third switching transistor connected to a blue data line. Three adjacent pixels connected to (Dm + 1_B) display red (R), green (G), and blue (B), respectively.

Therefore, the data driver for transmitting the data signal to the pixel should have the same number of output lines as the data lines, and the data driver includes a plurality of integrated circuits such that a plurality of output lines are provided. As a result, a problem arises in that the manufacturing cost is increased.

In particular, as the resolution and inch of the pixel portion increase, the data driver includes more output lines, thereby increasing manufacturing costs.

In addition, referring to the operation of the first pixel, when the first switching transistor is turned on by the scan signal through the scan line, the red data signal is transmitted to the pixel through the data line RDm. In this case, the voltage difference between the pixel power supply and the data signal is stored in the storage capacitor Cst.

In addition, a voltage stored in the storage capacitor Cst is applied to the gate electrode of the driving transistor M2 so that a constant current flows from the source electrode of the driving transistor M2 toward the drain electrode, thereby being connected to the driving transistor M2. An electric current flows in and emits light.

Equation 1 below represents the amount of current flowing from the source electrode to the drain electrode of the driving transistor M2.

Where I _OLED is the current flowing through the OLED, Vgs is the gate-source voltage of the driving transistor, Vth is the threshold voltage of the driving transistor M2, Vdata is the voltage of the data signal, and β is the gain factor of the driving transistor M2. ).

According to Equation 1, the current flowing through the OLED is affected by the pixel voltage and the threshold voltage of the driving transistor M2.

As the size of the pixel portion increases, a large number of pixels are connected to the pixel power lines, and a voltage drop occurs in the pixel voltage. The threshold voltage of the driving transistor M2 is non-uniform in the manufacturing process of the light emitting display device.

Accordingly, the light emitting display device according to the related art has a problem that the data driver includes more output lines as the resolution and the inch of the pixel portion increase, thereby increasing the manufacturing cost and causing the current flowing through the OLED to each pixel unevenly. Has the problem.

Accordingly, the present invention has been made to solve the problems of the prior art, an object of the present invention is to reduce the number of output lines of the data driver to reduce the manufacturing cost of the light emitting display device and to allow the current to flow uniformly in the OLED. It is to provide a light emitting display device.

As a technical means for achieving the above object, a first aspect of the present invention is a pixel unit for displaying an image, a scan driver for transmitting a scan signal, a data driver for transmitting a data signal to a plurality of first data lines, and the first And a plurality of demultiplexers configured to demultiplex the data signals applied to the data lines and transmit the demultiplexers to a plurality of second data lines, wherein the pixel parts include second and different scan lines and at least two adjacent pixels. A data line is connected, and the different second data lines are connected to the first data line through the demultiplexer unit.

In addition, the pixel may include a light emitting device, a driving transistor for driving a driving current through the light emitting device, a first switching transistor for selectively transmitting a data signal to a source electrode of the driving transistor, and a second for selectively transmitting an initialization signal. A switching transistor, a third switching transistor for selectively diode coupling the driving transistor, and receiving the initialization signal to store a first voltage corresponding to the initialization signal, and then storing the data signal from the gate electrode of the driving transistor. And a storage capacitor for receiving the second voltage corresponding to the data signal, a fourth switching transistor for selectively blocking the pixel power supply, and a fifth switching transistor for selectively blocking the driving current.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a structural diagram showing a structure of an embodiment of a light emitting display device using a demultiplexer according to the present invention. Referring to FIG. 2, the light emitting display device includes a pixel unit 100, a data driver 200, a demultiplexer 210, a scan driver 200, and a controller 400.

The pixel unit 100 includes a pixel 110 including N × M OLEDs, and N first red scan lines S1.1_R, S1.2_R, ... S1.N-1_R, S1. N_R), N first green scan lines S1.1_G, S1.2_G, ... S1.N-1_G, S1.N_G, first blue scan lines S1.1_B, S1.2_B, ... S1. N-1_B, S1.N_B), second red scan line (S2.1_R, S2.2_R, ... S2.N-1_R, S2.N_R), N second green scan lines (S2.1_G, S2.2_G , ... S2.N-1_G, S2.N_G, second blue scanning lines S2.1_B, S2.2_B, ... S2.N-1_B, S2.N_B, N light emission control lines E1. 1, E1.2, ... E1.N-1, E1.N and M first data lines D1,1 D1,2, D1.3, ... DM.1 arranged in the column direction , DM.2, DM.3). Then, the first power source Vdd and the second power source Vss are supplied from the outside, and the OLED emits light by the data signal and the pixel power source in response to the scan signal to represent an image.

The data driver 200 generates data signals and supplies the generated data signals to the second data lines D1 D2, D3,... DM. Here, each of the second data lines D1 D2, D3, ... DM is provided for each output line of the data driver 120, and the data driver 120 is provided for each period (1 horizontal period) in which the scan signal is supplied. M data signals are supplied to the second data lines D1, D2, D3, ... DM.

The data signal input through one data line includes a red data signal, a green data signal, and a blue data signal, and each data signal is sequentially input.

The demultiplexer unit 210 includes a plurality of demultiplexers, and includes first and second data lines D1, 1 D1, 2, D1.3, ... DM.1, DM.2, and DM.3. D1, D2, ... DM-1, DM). In addition, the demultiplexer unit 210 transmits the data signal transmitted by the second data lines D1, D2,... DM-1, DM connected to the data driver 200 by one control signal. Optionally transfer to lines D1,1 D1,2, D1.3, ... DM.1, DM.2, DM.3.

The scan driver 200 generates a red scan signal, a green scan signal, and a blue scan signal in response to the control signal, and sequentially transmits the red scan signal, the green scan signal, and the blue scan signal to the pixel unit 100. Each of the red, green, and blue first scanning lines S1.1, S1.2, ... S1.N-1, S1.N, and the red, green, and blue second scanning lines S2.1 of the pixel unit 100. , S2.2, ... S2.N-1, S2.N) and emission control lines (E1.1, E1.2, ... E1.N-1, E1.N) are sequentially scanned Signal and the emission control signal to the red, green and blue first scanning lines S1.1, S1.2, ... S1.N-1, S1.N, and the red, green and blue second scanning lines S2.1, S2.2, ... S2.N-1, S2.N) and emission control lines E1.1, E1.2, ... E1.N-1, S1.N.

The controller 400 generates a control signal and transmits the control signal to the demultiplexer 210 and the scan driver 300. The control signal includes a first control signal CLR, a second control signal CLG, and a third control signal CRB, and includes a first control signal CLR, a second control signal CLG, and a third control signal. CRB sequentially performs the on-off operation.

3 is a circuit diagram illustrating a pixel used in the light emitting display device of FIG. 2. Referring to FIG. 3, the pixel 110 includes an OLED and a peripheral circuit thereof, and includes a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, and a fourth switching transistor ( M4), a fifth switching transistor M5, a driving transistor M6, and a storage capacitor Cst. The first to fifth switching transistors M1, M2, M3, M4, and M5 and the driving transistor M6 include a gate electrode, a source electrode, and a drain electrode, and the storage capacitor Cst serves as the first electrode and the second electrode. Is done.

In the first switching transistor M1, a gate electrode is connected to the first scan line, a source electrode is connected to the data line, and a drain electrode is connected to the first node A. Therefore, the data signal is transmitted to the first node A by the first scan signal input through the first scan line.

In the second switching transistor M2, the gate electrode and the source electrode are connected to the second scan line, and the drain electrode is connected to the second node B. Therefore, the second scan signal input through the second scan line is transmitted to the second node B. FIG.

In the third switching transistor M3, the gate electrode is connected to the first scan line, the source electrode is connected to the third node C, and the drain electrode is connected to the second node B. Therefore, the potentials of the second node B and the third node C are made equal by the first scan signal input through the first scan line.

The fourth switching transistor M4 has a source electrode connected to the pixel power line Vdd, a drain electrode connected to the first node A, and a gate electrode connected to the emission control line. Therefore, the pixel power is selectively transferred to the driving transistor M6 according to the emission control signal transmitted through the emission control line.

The fifth switching transistor M5 has a source electrode connected to the third node C, a drain electrode connected to the OLED, and a gate electrode connected to the emission control line E1.n. Therefore, the current is selectively transferred to the OLED according to the emission control signal transmitted through the emission control line E1.n.

In the driving transistor M6, the source electrode is connected to the first node A, the drain electrode is connected to the third node C, and the gate electrode is connected to the second node B. Therefore, when the potentials of the second node B and the third node C become the same by the operation of the third switching transistor, the driving transistor M6 is diode-coupled and the data signal transmitted to the first node A is transmitted. Reaches the second node B through the driving transistor M6. When the pixel power is delivered to the first node, a current flows from the source electrode through the drain electrode in response to the voltage applied to the gate electrode. That is, the amount of current flowing by the potential of the second node B is determined.

The storage capacitor Cst is connected to the storage capacitor Cst of which the first electrode is connected to the pixel power line Vdd and the second electrode of the storage capacitor Cst is connected to the second node B. Therefore, when the initialization signal is connected to the second node B by the second switching transistor M2, the initialization signal is transferred to the storage capacitor Cst so that the storage capacitor Cst stores the initialization voltage and the first switching transistor M1. When the data signal is transferred to the driving transistor M6 by the third switching transistor M3, the voltage corresponding to the data signal is charged. The storage capacitor Cst transfers the stored voltage to the second node B so that the voltage stored in the storage capacitor Cst is applied to the gate electrode of the driving transistor M6.

4 is a timing diagram illustrating an operation of a pixel of FIG. 3. Referring to FIG. 4, the pixel is operated by inputting a first scan signal s1.n, a second scan signal s2.n, and a light emission control signal e1.n to the pixel. The first scan signal s1.n, the second scan signal s2.n, and the emission control signal e1.n are periodic signals, and the first section T1 and the second section T2. And a third section T3, and the third section T3 is maintained until one frame ends.

The first scan signal s1.n maintains a low state in the first section T1, maintains a high state in the second section T2 and the third section T3, and the second scan signal s2.n ) Maintains a high state in the first section T1 and a third section T3 and maintains a low state in the second section T2. In addition, the emission control signal e1.n maintains a high state in the first section T1 and the second section T2 and is switched to a low state in the third section T3 to maintain a low state.

In the first period T1, the second switching transistor M2 is turned on by the first scan signal s1.n. Therefore, the initialization signal is transmitted to the second node B so that the storage capacitor Cst is initialized by the initialization signal.

In the second period T2, the first switching transistor M1 and the third switching transistor M3 are turned on by the second scanning signal s2.n. Therefore, the data signal is transmitted to the first node A through the first switching transistor M1 and the potentials of the second node B and the third node C are equal by the third switching transistor M3. The driving transistor M6 is diode-coupled so that the data signal transmitted to the first node A is transferred to the second node B.

Therefore, the voltage corresponding to Equation 1 below is stored in the storage capacitor Cst, and the voltage corresponding to Equation 1 is applied to the gate electrode of the driving transistor M6.

Where Vsg is the voltage between the source and gate electrode of the driving transistor M6, Vdd is the pixel power supply voltage, Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor M6.

In the third period T3, the fourth switching transistor M4 and the fifth switching transistor M5 are turned on by the light emission control signal, and the pixel power is applied to the driving transistor M6. In this case, a voltage corresponding to Equation 1 is applied to the gate electrode of the driving transistor M6 so that a current corresponding to Equation 2 below flows from the source of the driving transistor M6 to the drain electrode.

Where I _OLED is the current flowing through the OLED, Vgs is the voltage applied to the gate electrode of the driving transistor M6, Vdd is the voltage of the pixel power supply, Vth is the threshold voltage of the driving transistor M6, and Vdata is the voltage of the data signal. .

Therefore, the current flowing in the OLED flows regardless of the threshold voltage of the driving transistor M6.

FIG. 5 is a diagram illustrating an embodiment of a demultiplexer employed in the light emitting display device of FIG. 2. Referring to FIG. 5, the demultiplexer 211 has three switching elements connected in parallel, receives a signal from one first data line, and outputs a signal to three second data lines, each of the second multiplexers. The data line is connected to the first switching element T1, the second switching element T2, and the third switching element T3.

The first switching device T1 is provided on the first first data line Dm and the first second data line Dm_R of the data driver 200 to supply the first data signal supplied to the first first data line Dm. 2 It is supplied to the data line Dm_R. The first switching device T1 is driven by the first control signal CLR supplied from the controller 210.

The second switching element T2 is provided between the first first data line Dm and the second second data line Dm + 1_G to supply the data signal supplied to the first first data line Dm to the second second data. Supply to line (Dm + 1_G). The second switching device T2 is driven by the second control signal CLG supplied from the controller 210.

The third switching element T3 is provided between the first first data line Dm and the third second data line Dm + 1_B to supply the data signal supplied to the first first data line Dm to the third second data. Supply to line (Dm + 1_B). The third switching device T3 is driven by the third control signal CLG supplied from the controller 210.

6 is a circuit diagram illustrating an example embodiment of a pixel unit coupled to a demultiplexer employed in a light emitting display according to the present invention. Referring to FIG. 6, for the sake of explanation, six pixels shown in FIG. 3 are arranged side by side, and each pixel is referred to as a first pixel 111 to a sixth pixel 116 in a left to right direction. The first pixel 111 and the fourth pixel 114 are red (R), the second pixel 112 and the fifth pixel 115 are green (G), the third pixel 113 and the sixth pixel 116. ) Represents blue (B).

The first pixel 111 and the fourth pixel 114 representing red, the second pixel 112 and the fifth pixel 115 representing green, the third pixel 113 and the sixth pixel representing blue ( 116 shares a scanning line, a light emission control line and a pixel power supply line, respectively. The scan lines are the first and second red scan lines S1.N_R and S2.N_R connected to the pixels representing red and the first and second green scan lines S1.N_G and S2.N_G input to the pixels representing green. ) And the first and second blue scan lines S1.N_B and S2.N_B which represent blue, and each first scan line is a signal one cycle earlier than each second scan line.

In addition, the first to third pixels 111, 112, and 113 are connected to the first demultiplexer 211 through the first first data lines Dm_R, Dm_G, and Dm_B, and the fourth to sixth pixels 114, 115, and 116 are also second-first. The second demultiplexer 212 is connected to the data lines Dm + 1_R, Dm + 1_G, and Dm + 1_B. In addition, the first demultiplexer 211 and the second demultiplexer 212 are connected to the data driver 200 through the first second data lines Dm and Dm + 1, respectively, to receive a data signal.

The first demultiplexer 211 and the second demultiplexer 212 may output data signals output from the first second data line and the second second data line according to a control signal from the first to third pixels 111, 112, and 113 and the fourth to fourth pixels. 6 pixels 114, 115, and 116 are sequentially transmitted.

FIG. 7 is a timing diagram illustrating an operation of the circuit of FIG. 6. Referring to FIG. 7, the pixel is a first red scan signal s1.n_R and a second red scan signal s2.n_R through a red scan line, and a first green scan signal s1.n_G through a green scan line. And a second green scan signal s2.n_G, a first blue scan signal s1.n_B and a second blue scan signal s2.n_B are input through a blue scan line, and a light emission control signal is input through a light emission control line. It is operated by input.

The first red scan signal s1.n_R, the first green scan signal s1.n_B, the first blue scan signal s1.n_G, the second red scan signal s2.n_R, and the second green scan The signal s2.n_G, the second blue scan signal s2.n_B, and the emission control signal e1.n are periodic signals, and the first section T1, the second section T2, and the third section ( T3) and the third section T3 is maintained until one frame ends.

In the first section T1, the first red scan signal s1.n_R, the first green scan signal s1.n_G, and the first blue scan signal are in an on state s1.n_B. Accordingly, the first pixel 111 and the fourth pixel 114 are initialized first, and the second pixel 112, the fifth pixel 115, the third pixel 113, and the sixth pixel 116 are sequentially initialized. This is followed by initialization. In this case, the data signals are sequentially input to the first to third pixels 111, 112, and 113 through the first demultiplexer 211 and to the fourth to sixth pixels 114, 115, and 116 through the second demultiplexer 212. Each demultiplexer 211 and 212 sequentially transmits a data signal by a control signal, and the control signal is a first red scan signal s1.n_R, a first green scan signal s1.n_G, and a first blue scan signal s1. .n_B).

In the second period T2, the second red scan signal s2.n_R, the second green scan signal s2.n_G, and the third blue scan signal s2.n_B are sequentially turned on. Therefore, first the first switching transistor M1 of the first pixel 111 and the fourth pixel 114 is turned on, followed by the first switching transistor of the second pixel 112 and the fifth pixel 115 ( The data signal is transmitted to each pixel in the order in which the first switching transistor M1 of the M1, the third pixel 113 and the sixth pixel 116 is turned on, and the first switching transistor M1 is turned on. do.

In the third section T3, the emission control signal is turned on so that the first to sixth pixels 111 to 116 connected to one emission control line emit light by the emission control signal.

In this case, the first pixel 111 and the fourth pixel 114 that emit red light are connected to the first and second red scan lines, and the second pixel 112 and the fifth pixel 115 that emit green light are formed in the first pixel 111. The third pixel 113 and the sixth pixel 116, which are connected to the first and second green scan lines and emit blue light, are connected to the first and second green scan lines, so that the storage capacitor Cst of each pixel is initialized. Since a data signal input to each pixel is input immediately after the data is input, the previous data signal is not stored again in the storage capacitor Cst.

Therefore, since the storage capacitor Cst is initialized, the data signal is stored in the storage capacitor Cst regardless of the magnitude of the voltage of the previous data signal, so that the data signal can be transferred using the demultiplexer.

FIG. 8 is a block diagram illustrating a portion of the scan driver employed in the light emitting display device of FIG. 2. Referring to FIG. 8, the scan driver 300 includes a shift register 310, a first calculator 320, and a second calculator 330.

The shift register 310 is composed of a plurality of flip-flops, and the lower flip-flops in the upper flip-flops are referred to as the first flip-flops to the fourth flip-flops 311 to 314, and each flip-flop is a clock signal CLK, CLK_B Motivated by The first flip-flop 311 receives the start pulse SP, outputs the first shift signal 1sr1 shifted from the start pulse SP, and again the first shift signal 1sr1 receives the second flip-flop 312. Is entered. The second flip-flop 312 that receives the first shift signal 1sr1 outputs the second shift signal 2sr1 shifted from the first shift signal 1sr1, and the second shift signal 2sr1 is again generated. It is input to three flip-flops 313. In addition, the third flip-flop 313 receiving the second shift signal 2sr1 outputs the third shift signal 3sr1 shifted from the second shift signal 2sr1. The third shift signal 3sr1 is input to the fourth flip-flop 314 to output the fourth shift signal 4sr1 obtained by shifting the third shift signal 3sr1 from the fourth flip-flop 314. The fourth shift signal 4sr1 is input to a lower flip-flop (not shown), and the lower flip-flop performs the same operation.

The first calculator 320 includes a plurality of NAND gates and a plurality of NOR gates, and the NAND gate and the NOR gate are alternately arranged. The upper and lower NAND gates are referred to as the first NAND gate 321, the second NAND gate 322, and the third NAND gate 323, and the upper and lower NOR gates are referred to as the first NOR gate 324 and the second. The NOR gate 325 and the third NOR gate 326 are called.

The first NAND gate 321 receives and operates the first shift signal 1sr1 and the second shift signal 2sr1 to generate the first operation signal 1sr2, and the second NAND gate 322 is the second shift. The signal 2sr1 and the third shift signal 3sr1 are received and computed to generate a second operation signal 2sr2. The third NAND gate 323 has a third shift signal 3sr1 and a fourth shift signal 4sr1. Is received to generate a third operation signal (3sr2).

The first NOR gate 324 receives the second shift signal 2sr1 and the third shift signal 3sr1 to generate a first emission control signal e1, and the second NOR gate 325 The third shift signal 3sr1 and the fourth shift signal 4sr1 are received and calculated to generate a second emission control signal e2. The third NOR gate 326 is lower than the fourth shift signal 4sr1. The signal of the flip-flop is input and calculated to generate a third emission control signal e3.

The second calculator 330 is connected only to the NAND gate of the first calculator 320. For simplicity, the second calculator 330 connected only to the first NAND gate 321 will be described. In the second calculator 330, three NOR gates 331 are connected in parallel, and each of the NOR gates is one. The input terminal receives a first operation signal, which is an output signal of the first NAND gate 321, and the other input terminal receives a control signal output from the controller 400. The control signal includes three signals CLR, CLG and CLB, each signal is input to each NOR gate 331.

The NOR gate 331 outputs a high signal when a low signal is input to two input terminals, and a low signal is output when a high signal or two different signals are input to the two input terminals. Therefore, when the second control signal is sequentially input while the first operation signal, which is the output signal of the first NAND gate, is low, the scan signals, which are high signals, are sequentially output to the three NOR gates.

The buffer 332 is connected to an output terminal of the NOR gate 324 of the first calculator and an output terminal of the NOR gate 331 of the second calculator to improve signal characteristics of the scan signal and the light emission control signal. When the driving transistor M6 of the pixel unit is of P-MOS type, the buffer inverts and outputs signals output from the NOR gates 324 and 331 of the first and second operation units.

In addition, an output terminal for outputting a scan signal among the output terminals of each scan driver is connected to two scan lines to apply a scan signal to two columns of upper and lower columns so that the pixel operates by two scan signals.

9 is a timing diagram illustrating an operation of the scan driver of FIG. 8. Referring to FIG. 9, when the start pulse SP and the clock signals CLK and CLK_B are input to the first shift register 311, the first shift register 311 shifts the start pulse SP to generate the first shift register 311. One shift signal 1sr1 is output.

The first shift signal 1sr1 output from the first shift register 311 is input to the first calculator 320 and the second shift register 312.

The second shift register 312 receives the first shift signal 1sr1, outputs the second shift signal 1sr2, and inputs the first shift signal 1sr2 to the first calculator 320 and the third shift register 313.

The third shift register 313 and the fourth shift register 314 perform the same operations as the first shift register 311 and the second shift register 312 so as to shift signals in order to sequentially shift the third shift signal 1sr3 and the third shift register 313. The fourth shift signal 1sr4 is output.

The first NAND gate 321 of the first calculator 320 receives the first shift signal 1sr1 and the second shift signal 2sr1 to perform a NAND operation, and the second NAND gate 322 receives the second shift signal. The NAND operation is performed by receiving the 2sr1 and the third shift signal 3SR1, and the third NAND gate 323 receives the third shift signal 3sr1 and the fourth shift signal 4sr1 to perform a NAND operation. .

Accordingly, each NAND gate of the first calculator 320 sequentially outputs the first operation signal 1sr2, the second operation signal 2sr2, and the third operation signal 3sr2.

The first NOR gate 324 of the first calculator 320 receives the second shift signal 2SR1 and the third shift signal 3SR1 to perform an NOR operation, and the second NOR gate 325 receives the third shift signal. The third NOR gate 326 receives the fourth shift signal 4SR1 and the lower shift signal to perform NOR operation by receiving the 3SR1 and the fourth shift signal 4SR1, respectively, to control light emission. The signals e1, e2, and e3 are output.

The second calculator 330 includes a plurality of three NOR gate pairs 332, and each NOR gate of the first NOR gate pair has a first operation signal 1sr2, a first control signal CLR, and a first operation signal. The three scan signals s1.1_R, s1.1_G, s1.1_B are performed by performing an NOR operation on (1sr2), the second control signal (CLG), and the first operation signal (1sr2) and the third control signal (CLB), respectively. ). The second NOR gate pair and the lower gate pair perform the same operation as the first NOR gate pair, and the second calculator 330 sequentially outputs the scan signal.

10 is a comparative example with a light emitting display device using a demultiplexer according to the present invention. Referring to FIG. 10, the light emitting display device includes a pixel unit 100, a data driver 200, a demultiplexer 210, a scan driver 200, and a controller 400.

The pixel unit 100 includes a pixel 110 including N × M OLEDs, and N first scanning lines S1.1, S1.2, ... S1.N-1, S1.N arranged in a row direction. ), N second scanning lines (S2.1, S2.2, ... S2.N-1, S2.N), N light emitting control lines (E1.1, E1.2, ... E1.N) -1, E1.N) and 3M first data lines D1,1 D1,2, D1.3, ... DM.1, DM.2, DM.3 arranged in the column direction . In addition, when the first power source Vdd and the second power source Vss are externally supplied, the OLED emits light by the data signal and the pixel power source in response to the scan signal to represent an image.

The data driver 200 supplies the data signals generated by generating the data signals to the second data lines D1, D2,... DM-1 and DM. Here, each of the second data lines D1, D2, ..., DM-1, DM is provided for each output line of the data driver 120, and the data driver 120 is provided with a period (1 horizontal) during which a scan signal is supplied. M data signals are supplied to each of the second data lines D1, D2, ..., DM-1, DM for each period.

The demultiplexer 210 includes first data lines D1,1 D1,2, D1.3, ... DM.1, DM.2, DM.3 and second data lines D1, D2, ... The number of demultiplexers equal to the number of second data lines D1, D2, ..., DM-1, DM, which are located between .DM-1 and DM and connected to the data driver, is included. In addition, the demultiplexer unit 210 controls the data signal transmitted by the second data lines D1, D2,... DM-1 and DM connected to the data driver 200 by one control line. And optionally (D1,1 D1,2, D1.3, ... DM.1, DM.2, DM.3).

The scan driver 200 generates a scan signal and a light emission control signal and sequentially transmits the scan signal and the emission control signal to the pixel unit 100. First scanning lines S1.1, S1.2, ... S1.N-1, S1.N of the pixel portion 100, N second scanning lines S2.1, S2.2, ... S2 N-1, S2.N) and N light emission control lines (E1.1, E1.2, ... E1.N-1, E1.N) sequentially remove scan signals and light emission control signals. One scanning line (S1.1, S1.2, ... S1.N-1, S1.N), the second scanning line (S2.1, S2.2, ... S2.N-1, S2.N) And light emission control lines E1.1, E1.2, ... E1.N-1, E1.N.

The controller 400 generates a control signal and transfers the control signal to the demultiplexer 210. The control signal includes a first control signal CLR, a second control signal CLG, and a third control signal CRB, and the data signal is transmitted to the pixel according to the operation of the control signal.

FIG. 11 is a circuit diagram illustrating a pixel unit coupled to a demultiplexer employed in the comparative example of FIG. 10. Referring to FIG. 11, for the sake of explanation, three pixels shown in FIG. 3 are arranged side by side, and each pixel includes a first pixel 111, a second pixel 112, and a third pixel from left to right. The pixel 113 is referred to as a first pixel 111, which is red (R), the second pixel 112 is green (G), and the third pixel 113 is blue (B).

The first to third pixels 111, 112, and 113 share the first scan line S1.n, the second scan line S2.n, the emission control line E1.n, and the pixel power supply line Vdd. do. Each pixel is connected to a red data line Dm_R to which red data is input, a green data line Dm + 1_G to which green data is input, and a blue data line Dm + 1_B to which blue data is input. The red data line Dm_R, the green data line Dm + 1_G, and the blue data line Dm + 1_B are the first data lines D1, 1 D1, 2, D1.3, ... DM.1, DM. 2, DM.3), and three data lines are connected to one demultiplexer 211.

The demultiplexer 211 is a demultiplexer included in the demultiplexer unit 210 including a plurality of demultiplexers, and includes a first switching device T1, a second switching device T2, and a third switching device T3. One end of each of the first to third switching elements is connected to the red data line Dm_R, the green data line Dm + 1_G, and the blue data line Dm + 1_B, and the opposite end thereof has one second data line. The data line Dm is connected to one of (D1, D2, D3, ... DM). Where m is an integer between 1 and M.

In addition, the first control signal CLR, the second control signal CLG, and the third control signal CLG are input to each switching element of the demultiplexer 211 so that the first to third control signals CLR, CLG, and CLB are input. Each switching element operates to sequentially input data signals inputted through the second data line Dm to the red data line Dm_R, the green data line Dm + 1_G, and the blue data line Dm + 1_B. To pass.

12 is a timing diagram illustrating an operation of the pixel unit illustrated in FIG. 11. Referring to FIG. 12, the pixel operates by inputting a first scan signal s1.n, a second scan signal s2.n, and an emission control signal e1.n. The first scan signal s1.n, the second scan signal s2.n, and the emission control signal e1.n are periodic signals, and the first section T1, the second section T2, and A third section T3 is included and the third section T3 is maintained until one frame ends. The first scan signal s1.n is a signal one cycle ahead of the second scan signal s2.n. Accordingly, the first scan signal s1.n input through the first scan line becomes the n-1 th scan signal, and the second scan signal s2.n input through the second scan line corresponds to the n th scan signal. Becomes

In the first period T1, the first scan signal s1.n is input as a low signal, and the second scan signal s2.n and the emission control signal e1.n are input as a high signal. The n−1 th red, green, and blue data signals are sequentially applied to the data lines connected to the first to third pixels 111, 112, and 113 by the demultiplexer 211. At this time, the second switching transistors M2 of the first to third pixels 111, 112, and 113 are turned on by the first scan signal s1.n, and the initialization voltage is stored in each storage capacitor Cst. At this time, since the first switching transistor M1 is turned off, the n-th data signal is not applied to the first to third pixels 111, 112, and 113.

In the second period T2, the first scan signal s1.n and the emission control signal e1.n are input as a high signal, and the second scan signal s2.n is input as a low signal. In this case, the first control signal CLR is input to the demultiplexer 211 as a low signal so that the n-th red data signal is applied to the first pixel 111 and the data is applied to the second pixel 112 and the third pixel 113. No signal is applied. Subsequently, the second control signal CLG is inputted as a low signal so that the nth green data signal is applied to only the second pixel 112, and the third control signal CLG is inputted as a low signal. The signal is applied only to the third pixel 113.

However, the first to third pixels 111, 112, and 113 share a scan signal, and the first switching transistor M1 of each pixel is simultaneously turned on by the second scan signal s2.n. At this time, the n-th red data signal applied to the first pixel 111 is input by the operation of the demultiplexer 211, but the n-th green and blue data signals of the second pixel 112 and the third pixel 113 are input. The n-1 th green and blue data signals, which are parasitic to the green and blue data lines GDLm and BDLm, are not inputted, thereby inputting the n-1 th green and blue data signals to the storage capacitor Cst. There is a problem that the process of initializing stored in the file has no meaning.

In addition, when the driving transistor M6 diode-couples and stores a voltage corresponding to the data signal in the storage capacitor Cst, when the voltage of the n−1 th data signal is higher than the voltage of the n th data signal, the driving transistor ( Since the voltage of the gate electrode of M6) is formed higher than the voltage of the source electrode, there is a problem that no current flows.

Therefore, when the circuit of the pixel portion is formed as shown in FIG. 11, the light emitting display device using the demultiplexer cannot use the pixel illustrated in FIG. 3 in the pixel portion. Therefore, there is a problem in that the demultiplexer cannot be used so that the size of the data driver of the pixel unit is large, the configuration is complicated, and the price is high.

2 to 12 show that the pixel portion is composed of P MOS transistors, but it is apparent to those skilled in the art that the pixel portion is composed of N MOS transistors.

While preferred embodiments of the present invention have been described using specific terms, such descriptions are for illustrative purposes only and it is understood that various changes and modifications may be made without departing from the spirit and scope of the following claims. You must lose.

The light emitting display device using the demultiplexer according to the present invention causes a current to flow through the OLED regardless of the threshold voltages of the pixel power supply and the driving transistor, and transmits a data signal through the demultiplexer so that the data driver has more data lines than the number of output lines of the data driver. The data signal can be transferred to reduce manufacturing costs.

Claims (7)

A pixel portion for displaying an image; A scan driver transferring a scan signal to the plurality of scan lines; A data driver transferring a data signal to the plurality of first data lines; And And a demultiplexer unit including a plurality of demultiplexers for demultiplexing the data signal applied to the first data line and transferring the demultiplexer to a plurality of second data lines. And at least two adjacent pixels in the pixel portion are connected to different scan lines and to different second data lines connected to one demultiplexer. The method of claim 1, And a control unit for transmitting a control signal to the demultiplexer unit and the scan driver. The method of claim 1, And different scan lines connected to the at least two adjacent pixels sequentially transmit the scan signals to the pixels. The method of claim 1, The demultiplexer includes at least two switching elements, one end of the at least two switching elements is connected to one first data line, and a second data line is respectively connected to the other end of the at least two switching elements. A light emitting display device for operating a device to select the output terminal to transmit a data signal. The method of claim 1, wherein the scan driving unit, A shift register unit for sequentially shifting input signals and outputting the output signals to a plurality of output terminals; A plurality of arithmetic means for receiving two output signals from among a plurality of output signals of the shift register to perform a NAND operation, and a plurality of arithmetic means for outputting arithmetic signals and two output signals of the plurality of output signals to perform NOR operation A first calculating part including a plurality of second calculating means for outputting a control signal; And a second calculation unit including a plurality of third calculation means for calculating the control signal and the operation signal and outputting the control signal as at least two scan signals sequentially output. The method of claim 5, wherein And the third calculating means selects the different scan lines to transfer the scan signals based on the control signal. The method of claim 1, wherein the pixel Light emitting element; A driving transistor for driving a driving current through the light emitting device; A first switching transistor for selectively transferring a data signal to a source electrode of the driving transistor; A second switching transistor for selectively transferring an initialization signal; A third switching transistor for selectively diode coupling the driving transistor; A storage capacitor receiving the initialization signal and storing a first voltage corresponding to the initialization signal, and receiving the data signal from a gate electrode of the driving transistor and storing a second voltage corresponding to the data signal; And And a fourth switching transistor for selectively blocking the pixel power supply and a fifth switching transistor for selectively blocking the driving current.

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