KR100578846B1 - Light emitting display - Google Patents

Abstract

The present invention relates to a light emitting display device.

A light emitting display device according to the present invention includes a first switching element for diode-connecting a transistor supplying a current to a light emitting element in response to a voltage charged in a capacitor in response to a first control signal, and data in response to a selection signal from a scanning line. A light emitting display having a pixel comprising a second switching element for transmitting a voltage to the capacitor, and a third switching element for blocking a current supplied from the transistor to the light emitting element in response to a second control signal from the light emitting scan line. Device. Here, the operation time point of the second control signal is slower than the operation time point of the first control signal.

According to the present invention, it is possible to prevent the black gradation display from being normally performed by the off current of the third switching element.

Light emitting display, OLED, threshold voltage, black gradation

Description

Light emitting display device {LIGHT EMITTING DISPLAY}

1 is a diagram showing a pixel circuit of a voltage write type organic EL display device according to the prior art.

2 is a diagram schematically illustrating a light emitting display device according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a pixel circuit according to an exemplary embodiment of the present invention.

4 is a driving timing diagram of the pixel circuit of FIG. 3.

5 is a diagram illustrating a structure of a scan driver according to an exemplary embodiment of the present invention.

FIG. 6 is a detailed circuit diagram of a signal output unit generating a light emission signal shown in FIG. 5.

FIG. 7 is a diagram illustrating waveforms of signals output according to the clock inverter illustrated in FIG. 6.

The present invention relates to a display device, and more particularly, to an organic electroluminescent (EL) display device.

In general, an organic EL display device is a display device for electrically exciting a fluorescent organic compound to emit light, and is capable of representing an image by voltage or current writing NxM organic light emitting cells. The organic light emitting cell has a structure of an anode, an organic thin film, and a cathode layer. The organic thin film has a multilayer structure including an emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) to improve the emission efficiency by improving the balance between electrons and holes. It also includes a separate electron injecting layer (EIL) and a hole injecting layer (HIL).

The organic light emitting cell may be driven using a simple matrix method and an active matrix method using a thin film transistor (TFT) or a MOSFET. In the simple matrix method, the anode and the cathode are orthogonal and the line is selected and driven, whereas the active driving method connects the thin film transistor and the capacitor to each indium tin oxide (ITO) pixel electrode to maintain the voltage by the capacitor capacitance. It is a driving method. In this case, the active driving method is divided into a voltage programming method and a current programming method according to the type of signal applied to maintain the voltage on the capacitor.

FIG. 1 is a pixel circuit of a voltage write type organic EL display device, and typically shows a pixel circuit connected to an m th data line Dm and an n th scan line Sn of a plurality of pixel circuits.

As shown in Fig. 1, the transistor M1 is connected to the organic EL element OLED to supply a current for emitting light. The amount of current in the transistor M1 is controlled by the data voltage applied through the switching transistor M2. At this time, a capacitor Cst for maintaining the applied voltage for a predetermined period is connected between the source and the gate of the transistor M2. The gate of the transistor M2 is connected to the scan line Sn and the source is connected to the data line Dm.

Referring to the operation of the conventional pixel circuit, when the transistor M2 is turned on by the selection signal applied to the gate of the transistor M2, the data voltage is transferred to the gate of the driving transistor M1 through the data line Dm. Is approved. In response to the data voltage applied to the gate, a current flows through the transistor M1 to the organic EL element OLED to emit light. At this time, the current flowing through the organic EL element OLED is represented by Equation 1 below.

Where I _OLED is the current flowing through the organic EL element OLED, Vgs is the voltage between the gate and the source of the transistor M1, Vth is the threshold voltage of the transistor M1, Vdata is the data voltage, and β is the transistor M1. It represents a constant value determined by the size and characteristics of.

As shown in Equation 1, according to the pixel circuit shown in FIG. 1, a current corresponding to the applied data voltage Vdata is supplied to the organic EL element OLED, and the organic EL element OLED corresponds to the supplied current. ) Will emit light.

However, such a pixel circuit of the conventional voltage writing method has a problem in that it is difficult to obtain a high gradation due to the variation in the threshold voltage Vth of the thin film transistor generated for each pixel due to the nonuniformity of the manufacturing process. For example, when driving a transistor of a pixel at 3V, a voltage must be applied to the gate of the thin film transistor at intervals of about 12 mV (= 3 V / 256) in order to express an 8 bit 256 gray level. When the variation in the threshold voltage of the thin film transistor is 100 kΩ, it is difficult to express a high gray scale.

An object of the present invention is to provide a light emitting display device capable of expressing uniform brightness by compensating for variation in threshold voltages of a driving transistor included in a pixel circuit.

Another object of the present invention is to provide a light emitting display device in which black gray scale display is normally performed.

In order to achieve the above object, a light emitting display device according to an aspect of the present invention is formed in a pixel region where a data line, a selection scan line, and a light emitting scan line cross each other, and correspond to a capacitor, a light emitting element, and a voltage charged in the capacitor. A transistor for supplying current to the light emitting element, a first switching element for diode-connecting the transistor in response to a first control signal, and a second switching element for transferring the data voltage to the capacitor in response to a selection signal from the scan line A pixel circuit including a third switching element for blocking a current supplied from the transistor to the light emitting element in response to a second control signal from the light emitting scan line; A data driver supplying a data signal to the data line according to an applied data control signal; And a first signal output unit configured to supply a selection signal to the scan line according to an input signal applied thereto, and a second signal output unit configured to generate the second control signal based on the selection signal output from the first signal output unit. And a driver, wherein an operation time point of the second control signal is slower than an operation time point of the first control signal. The first control signal may be a selection signal applied to a scan line immediately before the current scan line to which the selection signal is applied.

The first signal output unit of the scan driver may include: a shift register configured to sequentially delay an input signal by a predetermined period to generate a plurality of first signals; And a logic operation unit configured to generate a plurality of selection signals by performing a logic operation on the first signals. In addition, the second signal output unit of the scan driver operates according to the clock control signal applied, delays the selection signal output from the first signal output unit for a predetermined period, and outputs the second control signal applied to the light emitting scan line. It may include a clock inverter. In this case, the second signal output unit may further include at least one inverter for inverting and outputting a signal output from the clock inverter.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a directly connected part but also an electrically connected part with another element in between.

A light emitting display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings. In the embodiment of the present invention, an organic EL display device using electroluminescence of an organic material is described as an example of a light emitting display device.

2 schematically illustrates a light emitting display device according to an exemplary embodiment of the present invention.

As illustrated in FIG. 2, a light emitting display device according to an exemplary embodiment includes a display panel 100, a scan driver 200, and a data driver 300.

The display panel 100 includes a plurality of data lines D1 to Dm extending in the column direction, a plurality of scanning lines extending in the row direction, and a plurality of pixel circuits 10. The data lines D1 to Dm transfer the data voltage representing the image to the pixel circuit 10.

According to an exemplary embodiment of the present invention, the scan lines include a plurality of selection scan lines S1 -Sn for transmitting selection signals for selecting pixels and a plurality of emission scan lines E1 for transmitting light emission signals for controlling light emission periods of the organic EL elements. -En). The pixel circuit 10 is formed in the pixel region defined by the data lines and the selection and emission scanning lines.

The scan driver 200 sequentially applies the selection signals to the selection scan lines S1 to Sn, and sequentially applies the emission signals to the emission scan lines E1-En, respectively. The data driver 300 simultaneously applies a data voltage to the data lines D1 to Dm.

The scan driver 200 and / or the data driver 300 may be directly mounted on the glass substrate in the form of an integrated circuit. Alternatively, these drivers 200 and / or 300 may be formed on the glass substrate with the same layers as the layers forming the channels of the selective and light emission scan lines, the data lines, and the transistors. Alternatively, the driving units 200 and / or 300 may be formed on a substrate separate from the glass substrate, and the substrates may be electrically connected to the glass substrate. Also, a tape carrier package (TCP) and an FPC (attached to the glass substrate may be electrically connected. It may be mounted in the form of a chip in a flexible printed circuit (TAB) or tape automatic bonding (TAB).

Hereinafter, a pixel circuit according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a diagram illustrating a pixel circuit according to an exemplary embodiment of the present invention, and FIG. 4 is a driving timing diagram of the pixel circuit of FIG. 3.

In FIG. 3, only the furnace circuit connected to the m-th data line Dm and the n-th scan line Sn is illustrated for convenience of description. In Fig. 4, the selection signals applied to the nth scan line Sn and the (n-1) th scan line Sn-1 are represented by scan [n] and scan [n-1], respectively. Then, the signal applied to the emission scan line En is represented by the emission signal emit [n].

On the other hand, when the term for the scan line is defined, a scan line that transmits a selection signal for operating a transistor connected to the data line and the selection scan line so as to transfer the data voltage is referred to as a "current scan line" and transmits the selection signal immediately before the current selection signal. The scan line is referred to as the "last scan line".

As shown in FIG. 3, a pixel circuit according to an exemplary embodiment of the present invention includes five transistors M1 to M5, a storage capacitor Cst, a threshold voltage compensation capacitor Cvth, and an organic EL element OLED. Include. In FIG. 3, the transistors M1 to M5 are shown as p-channel field effect transistors, but the present invention is not limited thereto. For example, the transistors M1 to M4 may be p-channel field effect transistors and the transistor M5 may be an n-channel electric field. It is possible to change the configuration of the effect transistor. The transistor has two main electrodes (drain electrode and source electrode) and one control electrode (gate electrode).

The transistor M1 is a driving transistor for driving the organic EL element OLED, and is connected between the power supply VDD for supplying a high level power supply voltage and the transistor M5, and according to the voltage applied to the gate, The current flowing through the organic EL element OLED is controlled through M5). The transistor M2 is connected between the gate and the drain of the transistor M1, and diodes transistor M1 are responsive to the low level select signal scan [n-1] from the immediately preceding scan line Sn-1. Connect in the form.

The first electrode A of the capacitor Cvth is connected to the gate of the driving transistor M1, and the capacitor Cst and the transistor (Vst) are connected between the second electrode B of the capacitor Cvth and the power source VDD. M4) is connected in parallel. The transistor M4 connects the second electrode B of the capacitor Cvth to the power supply VDD in response to the low level select signal scan [n-1] from the previous scan line Sn-1. The transistor M3 is a switching transistor connected between the data line D _m and the second electrode B of the capacitor Cvth. The transistor M3 is connected to the low level select signal scan [n] from the current scan line Sn. In response, the data voltage from the data line Dm is transferred to the second electrode B of the capacitor Cvth.

The transistor M5 is connected between the drain of the transistor M1 and the anode of the organic EL element OLED, in response to the high level light emission signal emit [n] from the light emission scan line En. The drain and the organic EL element OLED are electrically blocked, and the current from the transistor M1 is supplied to the organic EL element OLED in response to the low level emission signal emit [n] from the emission scan line En. To pass.

The organic EL element OLED emits light corresponding to the input current. The voltage VSS connected to the cathode of the organic EL element OLED is a voltage having a lower level than the voltage VDD, and a ground voltage, a negative voltage, and the like may be used.

Hereinafter, an operation of a pixel circuit according to an exemplary embodiment of the present invention will be described with reference to FIG. 4.

First, when the selection signal scan [n-1] of the previous scan line Sn-1 becomes low in the T1 period, the transistor M2 is turned on so that the driving transistor M1 is connected in the form of a diode. Therefore, the voltage between the gate and the source of the driving transistor M1 is changed until the threshold voltage Vth of the driving transistor M1 is reached. At this time, since the source of the transistor M1 is connected to the power supply VDD, the gate of the transistor M1, that is, the voltage of the first electrode A of the capacitor Cvth becomes (VDD + Vth). Since the transistor M4 is turned on by the low level select signal scan [n-1], the second electrode B of the capacitor Cvth is connected to the power source VDD. The voltage of the two electrodes B becomes the power supply voltage VDD. Therefore, the threshold voltage Vth is stored in the capacitor Cvth. In addition, since the n-channel transistor M5 is turned off by the high level light emission signal emit [n], the current of the transistor M1 is prevented from flowing to the organic EL element OLED.

Next, when the selection signal scan [n-1) of the immediately preceding scan line Sn-1 becomes high level and the selection signal scan [n] of the current scan line Sn becomes low level in the period T2, the transistor M3. , M4 is turned on and transistors M2 and M4 are turned off. The data voltage Vdata is transferred from the data line Dm to the transistor M3. Then, the data voltage Vdata is transferred to the second electrode B of the capacitor Cvth, so that the voltage of the first electrode A of the capacitor Cvth is boosted by the difference between the data voltage Vdata and the power supply voltage VDD. do. Accordingly, the gate of the transistor M1, that is, the voltage Vg of the first electrode A of the capacitor Cvth is represented by Equation 2, and the current I _OLED flowing through the drain of the transistor M1 is represented by Equation 3 Become together. Since the transistor M5 is turned on by the low level light emission signal emit [n], the current I _OLED is transferred to the organic EL element OLED to emit light. In addition, since the voltage Vgs between the gate and the source of the transistor M1 is stored in the capacitors Cvth and Cst, the selection signal scan [n-1] of the previous scan line Sn-1 even after the T2 period. Is at a high level, the transistor M1 supplies a current as shown in Equation 3 to the organic EL element OLED. That is, the capacitor Cst serves to store the data voltage together with the threshold voltage Vth compensation capacitor Cvth.

Here, Vgs represents a voltage between the gate and the source of the transistor M1, Vth represents a threshold voltage of the transistor M1, Vdata represents a data voltage, and β represents a constant value.

In Equation 3, the current I _OLED transmitted to the organic EL element OLED is determined by the power supply voltage VDD and the data voltage Vdata regardless of the threshold voltage Vth of the driving transistor M1. do. Therefore, even though the threshold voltages Vth of the driving transistors M1 of the pixel circuits 10 of the display panel 100 are different from each other, in the present exemplary embodiment, the deviation of the threshold voltages Vth is compensated by the capacitor Cvth to induce The current supplied to the EL element OLED becomes constant. That is, according to the pixel circuit exemplified in the embodiment of the present invention, the luminance unbalance problem caused by the variation of the threshold voltage of the thin film transistor according to the position between each subpixel can be solved.

Meanwhile, in the pixel circuit of FIG. 3, when the threshold voltage Vth is stored in the capacitor Cvth by applying the low level selection signal scan [n-1] to the previous scan line Sn-1, the light emission scan line is simultaneously applied. When the emission signal (emit [n]) applied to (En) becomes a high level, an off current of the transistor M5 may momentarily flow to the organic EL element OLED. In this case, since the organic EL element OLED can emit a predetermined amount of light due to the off current, black gradation display is not normally performed. Therefore, as shown in FIG. 4, it is preferable that the operation timing of the emission signal emit [n] of the emission scanning line En is slower than the operation timing of the selection signal scan [n-1] of the scanning line Sn-1. Here, the operation time point indicates when the level state of the signal starts to change, for example, when the signal is changed from the low level to the high level or when the signal is changed from the high level to the low level.

Next, a scan driver for generating a selection signal and a light emission signal having such characteristics will be described.

5 is a structural diagram of a scan driver according to an exemplary embodiment of the present invention.

As shown in FIG. 5, the scan driver 200 according to an exemplary embodiment of the present invention may include a first signal output unit 210 that generates a selection signal and a second signal output unit 220 that generates a light emission signal. Include.

The first signal output unit 210 includes a shift register SR, NAND gates NAND1 -NADNn, and buffers B1-Bn, and the second signal output unit 220 includes a clock inverter CI1 -CIn. And inverters I1-In.

6 shows the structure of a clock inverter according to an embodiment of the present invention.

The clock interleaver CI1-CIn includes a plurality of transistors T1-T5, as shown in FIG. The transistor T3 operates according to the second input signal IN2 applied to the gate, and in response to the operation of the transistor T5, the transistors T1 and T2 invert and output the first input signal IN1. The transistors T4 and T5 invert the output signals again and output them. Thus, the first input signal is delayed and outputted without inversion. Here, the first input signal IN1 is a selection signal select [0] -select [n-1] output from the first signal output unit 210, and the second input signal IN2 is a control signal ENB. ) Therefore, the signal input to the second signal output unit 220 is delayed by the clock interleaver CI1-CIn and then inverted and output by the inverters I1-In.

Here, the inverters I1-In may be selectively used according to the characteristics of the light emission signal to be used, or one or more may be used. In other words, in the present embodiment, the transistors M2 and M4 operating according to the selection signal Scan [n-1] of the immediately preceding scan line and the transistor M5 operating according to the emission signal emit [n] have the same p-channel electric field. As an effect transistor, one inverter I1-In is formed after the clock inverters CI1-CIn so that the selection signal Scan [n-1] and the emission signal emit [n] are inverted. It was. However, in the case where the transistors M2 and M4 and the transistor M5 are made of transistors of different characteristic channels, the inverters I1-1 are output so that only the selection signal scan [n-1] is output as a light emitting signal with a predetermined time delay. In) may not be used or an even number may be used.

In the following description, it is assumed that NAND gates NAND1-NANDn, buffers B1-Bn, clock inverters CI1-CIn, and inverters I1-In are n corresponding to the number of selection scan lines S1-Sn. .

Here, the shift register SR includes (n + 1) flip-flops, and the output signal of each flip-flop becomes the output signals SR1-SRn + 1 of the shift register SR. The input signal of the first flip-flop is the start signal VSP, and the output signal of the (i) th flip-flop becomes the input signal of the (i + 1) -th flip-flop. The flip-flop of the shift register SR receives a signal when the clock VCLK is at the high level and maintains the input signal until the clock VCLK is at the high level again. Since the flip-flop may be configured in various forms, a detailed structure description of the flip-flop is omitted here.

Next, an operation of the scan driver according to an exemplary embodiment of the present invention will be described based on the structure.

The shift register SR of the first signal output unit 210 receives the clock VCLK and the start signal VSP and sequentially outputs the output signals SR1-SRn + 1 by a predetermined clock. The NAND gates NAND1-NANDn perform NAND operation on the output signals SR1-SRn of the shift register SR, and the buffers B1-Bn buffer the signals output by performing the NAND operation, and then select the select signal (select [ 0] -select [n-1]). At this time, the NAND gates NAND1-NANDn perform NAND operation on the control signal ENB and the output signals SR1-SRn + 1 of the shift register SR that are applied in a high level state to generate the light emission signal, The low level signal is output only when both the control signal ENB and the output signals SR1-SRn + 1 of the shift register SR have a high level.

Meanwhile, the clock inverters CI1-CIn of the second signal output unit 220 are signals output from the buffers B1-Bn of the first signal output unit 210 according to the applied clock, that is, the control signal ENB. That is, the select signals select [0] -select [n-1] are delayed for a predetermined time and then output, and the inverters I1-In invert the delayed signals to emit light signals emit [1] -emit [n. ])

7 shows an operation waveform of a signal output from the clock inverters CI1-CIn. As shown in FIG. 7, the input signal is output after being delayed for a predetermined time according to the characteristics of the clock inverters CI1-CIn, so that the emission signal (emit [1] -emit) finally outputted from the second signal output unit 220. The operation time of [n] is slower than the selection signals select [0] -select [n-1]. Therefore, it is possible to prevent the black gradation display from being normally performed by the off current of the transistor M5 generated when the selection signal and the emission signal are simultaneously driven.

In the above, the light emitting display device according to the exemplary embodiment of the present invention has been described. The embodiment described above is an embodiment to which the concept of the present invention is applied, and the scope of the present invention is not limited to the above embodiment, and various modifications may be made by using the concept of the present invention as it is.

According to the present invention, the luminance uniformity of the light emitting display device can be improved by compensating for the variation in the threshold voltage of the driving transistor included in the pixel circuit and the difference in voltage drop between the pixels.

In addition, the black gray scale display may be normally performed in the light emitting display device.

Claims (6)

A transistor formed in the pixel area where the data line, the selection scan line, and the light emission scan line intersect, a capacitor, a light emitting element, a transistor to supply current to the light emitting element in response to a voltage charged in the capacitor, and the transistor in response to a first control signal A first switching element for diode-connecting a second switching element, a second switching element transferring the data voltage to the capacitor in response to a selection signal from the scanning line, and a second switching signal from the transistor to the light emitting element in response to a second control signal from the light emitting scanning line A pixel circuit including a third switching element to block a supplied current; A data driver supplying a data signal to the data line according to an applied data control signal; And A scan driver including a first signal output unit configured to supply a selection signal to the scan line according to an input signal applied thereto, and a second signal output unit configured to generate the second control signal based on the selection signal output from the first signal output unit Including; The light emitting display device of which the operation time point of the second control signal is slower than the operation time point of the first control signal. The method of claim 1 And the first control signal is a selection signal applied to a scan line immediately preceding the current scan line to which the selection signal is applied. The method of claim 1, The first signal output unit of the scan driver A shift register configured to sequentially delay the input signal by a predetermined period to generate a plurality of first signals; And And a logic calculator configured to logically operate the first signals to generate a plurality of selection signals. The method according to claim 1 or 3, The second signal output unit of the scan driver And a clock inverter operating according to an applied clock control signal to delay the selection signal output from the first signal output unit for a predetermined period and outputting the second control signal applied to the light emitting scan line. The method of claim 4, wherein The second signal output unit And at least one inverter for inverting and outputting the signal output from the clock inverter. The method of claim 3, The shift register is composed of a plurality of flip-flops, And the logic calculator comprises a plurality of NAND gates for NAND-operating the first signals output from the odd-numbered flip-flop and the even-numbered flip-flop among the plurality of flip-flops and outputting the selected signals as the selection signals.

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