KR100699583B1 - Output buffer circuit - Google Patents

Abstract

The present invention relates to an output buffer circuit, which detects an offset voltage of a data driver without a capacitor and a switch, and feeds it back to an input terminal to make an output voltage equal to an input voltage, thereby miniaturizing the data driver and compensating for an accurate offset voltage. And since there is no time required to compensate for the offset voltage, there is an advantage that can transmit high-speed data.

An output buffer circuit according to the present invention includes an input terminal to which an input voltage is applied to one terminal and an output voltage to the other terminal; A class AB output stage configured to increase a current flowing through the output stage when the difference between the input voltage and the output voltage is greater than zero; A floating current source for biasing the class AB output stage; A summing circuit connected to the input terminal, the floating current source, and the class AB output terminal to sum the current supplied from the input terminal and the internal current supplied from the floating current source; An offset sensing circuit connected to the input terminal and configured of a plurality of transistors to sense an offset voltage; And an offset compensating circuit connected to the input terminal and the offset sensing circuit and configured by a plurality of transistors to compensate for the offset voltage.

Output buffer circuit, offset cancellation circuit, offset compensation circuit, offset voltage, transistor

Description

Output buffer circuit {OUTPUT BUFFER CIRCUIT}

1A illustrates an output buffer modeled according to the prior art.

1B is a diagram illustrating a bipolar offset voltage generated by the prior art.

1C is a diagram illustrating a bipolar offset voltage generated by the prior art.

2 is a circuit diagram of an output buffer circuit according to the prior art.

3 is a circuit diagram of an output buffer circuit according to the present invention.

4A is a circuit diagram of an output buffer circuit for compensating bipolar offset voltage according to the present invention.

4b is a circuit diagram of an output buffer circuit for compensating negative offset voltage according to the present invention;

5A illustrates an output buffer modeled according to the present invention.

Figure 5b is a view showing the waveform of the offset voltage measured by the present invention

Figure 5c is a view showing the waveform of the output voltage measured by the present invention

<Description of Major Symbols in Drawing>

300: output buffer circuit 301a to 301f: input terminal

301a: first NMOS transistor 301b: second NMOS transistor 301c: first PMOS transistor 301d: second PMOS transistor 301e: third NMOS transistor 301f: third PMOS transistor 302a to 302d: floating current source 303a ~ 303h: summing circuit

303a: fourth PMOS transistor 303b: fifth PMOS transistor

303c: fourth NMOS transistor 303d: fifth NMOS transistor

304a, 304b: Class AB output terminal 305a ~ 305f: Offset detection circuit

305a: 6th NMOS transistor 305b: 7th NMOS transistor 305c: 6th PMOS transistor 305d: 7th PMOS transistor 305e: 8th NMOS transistor 305f: 8th PMOS transistor 306a-306h: offset compensation circuit 306a : First current mirror

306b: second current mirror 306c: third current mirror

306d: fourth current mirror 306e: fifth current mirror

306f: sixth current mirror 306g: seventh current mirror

306h: eighth current mirror 500: output buffer

Iss: Input Bias Current Ip: Class AB Output Bias Current

t: data transmission time

The present invention relates to an output buffer circuit, by detecting an offset voltage, which is a difference between an input and an output voltage of a data driver without a capacitor and a switch, and feeding the output voltage back to an input terminal to make an output voltage equal to an input voltage. In addition to miniaturizing the size of the data driver, it is possible to compensate for offset voltage more accurately by preventing errors caused by charge injection, and to transmit data at high speed since no time for compensating the offset voltage is required. The present invention relates to an output buffer circuit.

The output resolution of SOM (Spatial Optical Modulator) driver ICs is currently at the 8-bit level, but will be put to practical use in more than 10 bits in the coming years.

However, in order to express the 10-bit grayscale voltage, considering that the output voltage range is about 4V, a data driver capable of outputting an error between input and output voltages, that is, an interlevel gray scale voltage having an offset voltage of ± 1 mV or less. Will be needed. Considering that the offset voltage of the current 8-bit data driver is in the range of ± 3mV to ± 10mV, it can be seen that a data driver with a very high precision is required. However, if the current 8-bit data driver is used, as the output resolution increases, the offset voltage is affected, and thus the accurate video signal cannot be delivered.

Therefore, in order to reduce the offset voltage of the data driver, various offset compensation circuits have been applied to the data driver. For example, an auto zeroing method, a chopper stabilization method, and a ping-pong method are used. Usually, auto zero method is used the most.

FIG. 1A illustrates an output buffer 100 modeled according to the prior art, and FIGS. 1B and 1C illustrate offset voltages generated by the prior art.

The input voltage signal is applied to the input terminal of the output buffer 100 of FIG. 1A, and the offset voltage generated according to time at the output node A of the output terminal is greater than the input voltage. ) And the input voltage is greater than the output voltage can be divided into the negative offset voltage (Fig. 1c) generated. Due to such offset voltage, a problem arises in that an accurate video signal cannot be transmitted during the data transmission time t. There may be various causes of the offset voltage, but the main cause is mismatch of transistors generated during the fabrication of semiconductor circuits. That is, during the fabrication process of the semiconductor circuit, the transistors in the signal path for processing the positive signal and the sub-signal of the semiconductor circuit input terminal are made different in size, thereby generating a positive or negative offset voltage.

FIG. 2 is a circuit diagram of an output buffer circuit 200 according to the prior art, and illustrates an output buffer circuit 200 to which an auto zero offset compensation circuit commonly used is applied.

In the output buffer circuit 200 according to the related art, as shown in FIG. 2, an input voltage is applied to one terminal and an output voltage is applied to the other terminal, and a class AB output terminal ( Floating current sources 202a to 202d for biasing 204a and 204b, the input terminals 201a to 201f, connected to the floating current sources 202a to 202d, and class AB output terminals 204a and 204b, respectively, to the input stage 201a. Summing circuits 203a to 203h that sum the current supplied from ˜201f and the internal current supplied from the floating current sources 202a to 202d, and if the difference between the input voltage and the output voltage is greater than 0, the current flowing through the output terminal is increased. It is composed of an offset compensation circuit connected to the class AB output terminals 204a and 204b for outputting a voltage, the input terminals 201a to 201f, and the class AB output terminals 204a and 204b, and composed of a switch and a capacitor to compensate for the offset voltage. do.

The offset compensation circuit includes a capacitor Coff for storing the offset voltage and switches SW1, SW2, SW3, and SW4 that are turned on to compensate for the offset voltage when the offset voltage is generated.

The offset voltage is compensated by the offset compensation circuit in two steps. Referring to the output buffer circuit 200 shown in FIG. 2, the offset voltage is compensated for as follows.

If the offset voltage of the output buffer circuit 200 itself is Voff and the input voltage is Vin, in the first step, the first switch SW1 and the second switch SW2 are turned on, and the third switch SW3, The fourth switch SW4 is turned off so that the Voff of the output buffer circuit 200 itself is stored in the capacitor Coff. That is, since the first switch SW1 and the second switch SW2 are turned on, the voltage of the negative node of the capacitor Coff is Vin, and the voltage of the positive node of the capacitor Coff is Vin. It becomes + Voff, and the voltage applied across the capacitor Coff becomes Voff.

The Voff stored in the capacitor Coff is compensated by turning on the third switch SW3 and the fourth switch SW4 in the second step, and the first switch SW1 and the second switch SW2 are turned off. do. That is, when the third switch SW3 and the fourth switch SW4 are turned on, the voltage of the positive node of the capacitor is converted into Vin, and according to the law of charge conservation, the voltage of the negative node of the capacitor is Since Vin-Voff, the voltage applied to the input terminals 201a-201f of the output buffer circuit 200 becomes Vin-Voff. Therefore, since the offset voltage of the output buffer circuit 200 itself is defined as Voff, the offset voltage Voff is compensated so that the output voltage is equal to the input voltage Vin.

However, in the conventional output buffer circuit as described above, the signal path of the input / output voltage is cut off at the time of sampling the offset, that is, the first step of compensating the offset, and the compensation of the offset voltage at the second step. As time is required, a large amount of time required for data transmission cannot be secured, which causes a problem of high speed data transmission.

In addition, as the offset voltage is compensated using the switch, an offset voltage that is different from the actual offset voltage is generated due to the charge injection phenomenon generated during the switching operation, so that the offset voltage is not completely compensated.

In addition, since the offset voltage may be stored not only in the capacitor constituting the offset compensation circuit, but also in the generated parasitic capacitor, a capacitor having a capacitance of a predetermined value or more is required to prevent the error caused by this. There was a problem that the size of the larger.

Accordingly, the present invention has been made to solve the above problems, and by detecting an offset voltage without a capacitor and a switch and feeding the output voltage back to the input terminal, the output voltage is equal to the input voltage, thereby miniaturizing the size of the data driver. In addition, the present invention provides an output buffer circuit capable of transmitting data at high speed since the error caused by the charge injection is prevented to enable accurate compensation of the offset voltage and no time is required to compensate the offset voltage.

An output buffer circuit according to the present invention for achieving the above object, the input terminal is applied to the input voltage to one terminal, the output voltage to the other terminal; A class AB output stage configured to increase a current flowing through the output stage when the difference between the input voltage and the output voltage is greater than zero; A floating current source for biasing the class AB output stage; A summing circuit connected to the input terminal, the floating current source, and the class AB output terminal to sum the current supplied from the input terminal and the internal current supplied from the floating current source; An offset sensing circuit connected to the input terminal and configured of a plurality of transistors to sense an offset voltage; And an offset compensating circuit connected to the input terminal and the offset sensing circuit and configured by a plurality of transistors to compensate for the offset voltage.

The input terminal may include a first NMOS transistor to which the input voltage is applied to a gate; A first PMOS transistor to which the input voltage is applied to a gate; A second NMOS transistor to which the output voltage is applied to a gate; A second PMOS transistor to which the output voltage is applied to a gate; A third NMOS transistor for biasing the first and second NMOS transistors; And a third PMOS transistor for biasing the first and second PMOS transistors.

The offset sensing circuit may include a sixth NMOS transistor to which the input voltage is applied to a gate; A sixth PMOS transistor to which the input voltage is applied to a gate; A seventh NMOS transistor to which the output voltage is applied to a gate; A seventh PMOS transistor to which the output voltage is applied to the gate; An eighth NMOS transistor for biasing the sixth and seventh NMOS transistors; And an eighth PMOS transistor for biasing the sixth and seventh PMOS transistors.

The offset compensation circuit may include a first current mirror connected to a drain of the first NMOS transistor of the input terminal; A second current mirror connected to the drain of the second NMOS transistor of the input terminal; A third current mirror connected to the drain of the first PMOS transistor of the input terminal; A fourth current mirror connected to the drain of the second PMOS transistor of the input terminal; A fifth current mirror connected to the drain of the sixth NMOS transistor of the offset sensing circuit; A sixth current mirror connected to the drain of the seventh NMOS transistor of the offset sensing circuit; A seventh current mirror connected to the drain of the sixth PMOS transistor of the offset sensing circuit; And an eighth current mirror connected to the drain of the seventh PMOS transistor of the offset sensing circuit.

The first, second, fifth, and sixth current mirrors may be PMOS transistors, and the third, fourth, seventh, eighth current mirrors may be NMOS transistors.

At this time, the first current mirror, characterized in that the drain current of the same magnitude as the drain current of the sixth current mirror flows.

The second current mirror is characterized in that a drain current having the same magnitude as that of the fifth current mirror flows.

A drain current of the same magnitude as that of the eighth current mirror flows through the third current mirror.

The fourth current mirror is characterized in that a drain current having the same magnitude as the drain current of the seventh current mirror flows.

In addition, the offset voltage is characterized in that the bipolar offset voltage.

At this time, the drain current value of the first NMOS transistor is larger than the drain current value of the second NMOS transistor, and the drain current value of the first PMOS transistor is smaller than the second PMOS drain current value. It is done.

The drain current value of the sixth NMOS transistor is smaller than the drain current value of the seventh NMOS transistor, and the drain current value of the sixth PMOS transistor is larger than the seventh PMOS drain current value. It is done.

The offset voltage is characterized in that the negative offset voltage.

At this time, the drain current value of the first NMOS transistor is larger than the drain current value of the second NMOS transistor, and the drain current value of the first PMOS transistor is smaller than the second PMOS drain current value. It is done.

The drain current value of the sixth NMOS transistor is greater than the drain current value of the seventh NMOS transistor, and the drain current value of the sixth PMOS transistor is smaller than the seventh PMOS drain current value. It is done.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of an output buffer circuit 300 according to the present invention.

In the output buffer circuit 300 according to the present invention, as shown in FIG. 3, an input voltage is applied to one terminal and an output voltage is applied to the other terminal, and a class AB output terminal ( Floating current sources 302a to 302d for biasing 304a and 304b, the input terminals 301a to 301f, floating current sources 302a to 302d, and class AB output terminals 304a and 304b to be connected to the input terminals 301a to Summing circuits 303a to 303h that sum the current supplied from 301f and the internal current supplied from the floating current sources 302a to 302d. If the difference between the input voltage and the output voltage is greater than 0, the current flowing through the output terminal is increased to increase the voltage. Class AB output stages 304a and 304b for outputting the signal, offset sensing circuits 305a to 305f connected to the input terminals 301a to 301f, and detecting offset voltages, and input terminals 301a to 301f and offset sensing circuits 305a. An offset to compensate for the offset voltage Set compensation circuits 306a to 306h.

The input terminals 301a to 301f include a first NMOS transistor 301a and a first PMOS transistor 301c to which the input voltage is applied to the gate, and a second NMOS transistor 301b to which the output voltage is applied to the gate. ) And a second PMOS transistor 301d, a third NMOS transistor 301e for biasing the first and second NMOS transistors 301a and 301b, and the first and second PMOS transistors 301c and 301d. ) Is composed of a third PMOS transistor 301f. As shown in FIG. 3, since the input terminals 301a to 301f are configured by using the NMOS transistor and the PMOS transistor, the voltages of the entire range from the ground voltage to the power supply voltage VDD can be ensured as the input / output voltage. do. As such, an input terminal capable of securing an input / output voltage of a voltage range from the ground voltage to the power supply voltage VDD is called a rail to rail input terminal, and thus, as an output buffer according to the present invention, the rail to rail It is preferable to use a folded cascode operational amplifier having an input.

The offset sensing circuits 305a to 305f may include a sixth NMOS transistor 305a and a sixth PMOS transistor 305c to which the input voltage is applied to the gate, and a seventh NMOS transistor to which the output voltage is applied to the gate. An eighth NMOS transistor 305e for biasing 305b and a seventh PMOS transistor 305d, the sixth and seventh NMOS transistors 305a and 305b, and the sixth and seventh PMOS transistors 305c, 8th PMOS transistor 305f which biases 305d.

The offset compensation circuits 306a to 306h may include a first current mirror 306a connected to a drain of the first NMOS transistor 301a of the input terminals 301a to 301f and a second yen of the input terminals 301a to 301f. A second current mirror 306b connected to the drain of the MOS transistor 301b, a third current mirror 306c connected to the drain of the first PMOS transistor 301c of the input terminals 301a to 301f, and the input terminals 301a to A fourth current mirror 306d connected to the drain of the second PMOS transistor 301d of 301f, and a fifth current mirror connected to the drain of the sixth NMOS transistor 305a of the offset sensing circuits 305a to 305f ( 306e), a sixth current mirror 306f connected to a drain of the seventh NMOS transistor 305b of the offset sensing circuits 305a to 305f, and a sixth PMOS transistor 305c of the offset sensing circuits 305a to 305f. A seventh current mirror 306g connected to the drain of the second transistor; and a seventh PMOS transistor of the offset detection circuits 305a to 305f. And an eighth current mirror 306h connected to the drain of the rotor 305d. Here, the first, second, fifth, and sixth current mirrors 306a, 306b, 306e, and 306f are PMOS transistors, and the third, fourth, seventh and eighth current mirrors 306c, 306d, 306g, and 306h are NMOS. A transistor, wherein the first current mirror 306a is the sixth current mirror 306f, the second current mirror 306b is the fifth current mirror 306e, and the third current mirror 306c. Is a mirror relationship with the eighth current mirror 306h and the fourth current mirror 306d with the seventh current mirror 306g, respectively. Accordingly, the first current mirror 306a, the sixth current mirror 306f, the second current mirror 306b, the fifth current mirror 306e, the third current mirror 306c, and the first current mirror 306a. The same amount of drain current flows through the eighth current mirror 306h, the fourth current mirror 306d, and the seventh current mirror 306g, respectively.

Hereinafter, a preferred embodiment of detecting the offset voltage generated by using the output buffer circuit 300 shown in FIG. 3 and performing negative feedback by the amount will be described in detail.

Example 1

4A shows a circuit diagram of an output buffer circuit for compensating bipolar offset voltage according to the present invention.

First, when the NMOS transistors 301a, 301b, and 301e of the input terminals 301a to 301e operate, the offset voltage of the bipolarity is compensated for as follows. At this time, the current biased to the input terminals 301a to 301f is defined as Is, and the current biased to the class AB output terminals 304a and 304b through the floating current sources 302a to 302d as Ip.

Since the offset voltage of the bipolar is generated when the output voltage is larger than the input voltage, the gate voltage of the first NMOS transistor 301a becomes relatively smaller than the gate voltage of the second NMOS transistor 301b. The magnitude of the drain current I ₁ of the _first NMOS transistor 301a is smaller than the magnitude of the drain current I ₂ of the second NMOS transistor 301b.

In addition, since the offset detection circuits 305a to 305f are also connected to the same node as the input terminals 301a to 301f, the gate voltage of the sixth NMOS transistor 305a of the offset detection circuits 305a to 305f is relatively high. The gate voltage of the seventh NMOS transistor 305b of the offset sensing circuits 305a to 305f becomes smaller, and accordingly, the magnitude of the drain current I ₇ of the sixth NMOS transistor 305a is The size of the offset voltage is smaller than that of the drain current I ₈ of the seventh NMOS transistor 305b.

In this case, the sixth NMOS transistor 305a of the offset sensing circuits 305a to 305f is connected to the drain of the fifth current mirror 306e of the offset compensating circuits 306a to 306h and the offset sensing circuit 305a. Since the seventh NMOS transistor 305b of ˜305f is connected to the sixth current mirror 306f of the offset compensation circuits 306a ˜ 306h, the current I ₅ flowing through the first current mirror 306a Is equal to the magnitude of the drain current I ₈ of the seventh NMOS transistor 305b of the offset sensing circuits 305a to 305f, and the current I ₆ flowing through the second current mirror 306b. Is equal to the size of the drain current I ₇ of the sixth NMOS transistor 305a of the offset sensing circuits 305a to 305f.

Accordingly, the first NMOS transistor 301a and the first transistor of the input terminals 301a to 301f are drained from the drains of the fourth PMOS transistor 303a and the fifth PMOS transistor 303b of the summing circuits 303a to 303h. Since the same current of Iss / 2 magnitude flows into the drain of the 2 NMOS transistor 301b, the output voltage is lowered and the offset voltage of the bipolar is compensated.

In addition, when the PMOS transistors 301c, 301d, and 301f of the input terminals 301a to 301f operate, the offset voltage of the bipolarity will be described. Similarly to when the NMOS transistors 301a, 301b, and 301e of the input terminals 301a to 301f operate, the current biased to the input terminals 301a to 301f is Is, classed through the floating current sources 302a to 302d. The biased current at the AB output terminals 304a and 304b will be defined as Ip.

When a bipolar offset voltage occurs, the gate voltage of the first PMOS transistor 301c becomes relatively smaller than the gate voltage of the second PMOS transistor 301d, and thus, the first PMOS transistor ( The magnitude of the drain current I ₃ of 301c is greater than the magnitude of the drain current I ₄ of the second PMOS transistor 301d by the amount of the offset voltage.

In addition, since the offset detection circuits 305a to 305f are also connected to the same node as the input terminals 301a to 301f, the gate voltage of the sixth PMOS transistor 305c of the offset detection circuits 305a to 305f is relatively high. The gate voltage of the seventh PMOS transistor 305d of the offset sensing circuits 305a to 305f becomes smaller, and accordingly, the magnitude of the drain current I ₁₁ of the sixth PMOS transistor 305c is greater than the gate voltage of the offset sensing circuits 305a to 305f. The size of the offset voltage is greater than that of the drain current I ₁₂ of the seventh PMOS transistor 305d.

In this case, the sixth PMOS transistor 305c of the offset sensing circuits 305a to 305f is connected to the drain of the seventh current mirror 306g of the offset compensating circuits 306a to 306h and the offset sensing circuit 305a. Since the seventh PMOS transistor 305d of ˜305f is connected to the eighth current mirror 306h of the offset compensation circuits 306a ˜ 306h, the current I ₉ flowing through the third current mirror 306c Is equal to the magnitude of the drain current I ₁₂ of the seventh PMOS transistor 305d of the offset sensing circuits 305a to 305f, and the current I ₁₀ flowing through the fourth current mirror 306d. Is equal to the size of the drain current I ₁₁ of the sixth PMOS transistor 305c of the offset sensing circuits 305a to 305f.

Accordingly, the first PMOS transistors 301c and the first transistors of the input terminals 301a to 301f are drained from the drains of the fourth NMOS transistor 303e and the fifth NMOS transistor 303f of the summing circuits 303a to 303h. Since the same current of Iss / 2 magnitude flows into the drain of the 2 PMOS transistor 301d, the output voltage is lowered and the offset voltage of the bipolar is compensated.

Example 2

Figure 4b shows a plan view of the output buffer circuit to compensate for the negative offset voltage of the present invention.

First, when the NMOS transistors 301a, 301b, and 301e of the input terminals 301a to 301f operate, the offset voltage of the negative polarity is compensated for as follows. At this time, the current biased to the input terminals 301a to 301f is defined as Is, and the current biased to the class AB output terminals 304a and 304b through the floating current sources 302a to 302d as Ip.

Since the negative offset voltage is generated when the input voltage is greater than the output voltage, the gate voltage of the first NMOS transistor 301a becomes relatively greater than the gate voltage of the second NMOS transistor 301b, and thus The magnitude of the drain current I ₁ of the _first NMOS transistor 301a is larger than the magnitude of the drain current I ₂ of the second NMOS transistor 301b.

In addition, since the offset detection circuits 305a to 305f are also connected to the same node as the input terminals 301a to 301f, the gate voltage of the sixth NMOS transistor 305a of the offset detection circuits 305a to 305f is relatively high. The gate voltage of the seventh NMOS transistor 305b of the offset sensing circuits 305a to 305f is greater than the gate voltage. Accordingly, the magnitude of the drain current I ₇ of the sixth NMOS transistor 305a may be greater than the gate voltage. The size of the offset voltage is greater than that of the drain current I ₈ of the seventh NMOS transistor 305b.

At this time, as in compensating the offset voltage of the polarity, the sixth NMOS transistor 305a of the offset sensing circuits 305a to 305f drains the fifth current mirror 306e of the offset compensating circuits 306a to 306h. And the seventh NMOS transistor 305b of the offset sensing circuits 305a to 305f are connected to the sixth current mirror 306f of the offset compensating circuits 306a to 306h and thus, the first current. The magnitude of the current I ₅ flowing in the mirror 306a is equal to the magnitude of the drain current I ₈ of the seventh NMOS transistor 305b of the offset sensing circuits 305a to 305f, and the second current. The magnitude of the current I ₆ flowing in the mirror 306b is equal to the magnitude of the drain current I ₇ of the sixth NMOS transistor 305a of the offset sensing circuits 305a to 305f.

Accordingly, the first NMOS transistor 301a and the first transistor of the input terminals 301a to 301f are drained from the drains of the fourth PMOS transistor 303a and the fifth PMOS transistor 303b of the summing circuits 303a to 303h. Since the same current of Iss / 2 magnitude flows into the drain of the 2 NMOS transistor 301b, the output voltage is increased and the offset voltage of the negative polarity is compensated.

In addition, when the PMOS transistors 301c, 301d, and 301f of the input terminals 301a to 301f operate, the offset voltage of the negative polarity is compensated. Similarly to when the NMOS transistors 301a, 301b, and 301e of the input terminals 301a to 301f operate, the current biased to the input terminals 301a to 301f is Is, classed through the floating current sources 302a to 302d. The biased current at the AB output terminals 304a and 304b will be defined as Ip.

When a negative offset voltage is generated, the gate voltage of the first PMOS transistor 301c becomes relatively greater than the gate voltage of the second PMOS transistor 301d, and thus, the first PMOS transistor ( The magnitude of the drain current I ₃ of 301c is smaller than the magnitude of the drain current I ₄ of the second PMOS transistor 301d by the amount of the offset voltage.

In addition, since the offset detection circuits 305a to 305f are also connected to the same node as the input terminals 301a to 301f, the gate voltage of the sixth PMOS transistor 305c of the offset detection circuits 305a to 305f is relatively high. The gate voltage of the seventh PMOS transistor 305d of the offset sensing circuits 305a to 305f is greater than the gate voltage. Accordingly, the magnitude of the drain current I ₁₁ of the sixth PMOS transistor 305c is increased. The offset voltage is smaller than the drain current I ₁₂ of the seventh PMOS transistor 305d.

In this case, the sixth PMOS transistor 305c of the offset sensing circuits 305a to 305f is connected to the drain of the seventh current mirror 306g of the offset compensating circuits 306a to 306h and the offset sensing circuit 305a. Since the seventh PMOS transistor 305d of ˜305f is connected to the eighth current mirror 306h of the offset compensation circuits 306a ˜ 306h, the current I ₉ flowing through the third current mirror 306c Is equal to the magnitude of the drain current I ₁₂ of the seventh PMOS transistor 305d of the offset sensing circuits 305a to 305f, and the current I ₁₀ flowing through the fourth current mirror 306d. Is equal to the size of the drain current I ₁₁ of the sixth PMOS transistor 305c of the offset sensing circuits 305a to 305f.

Accordingly, the first PMOS transistors 301c and the first transistors of the input terminals 301a to 301f are drained from the drains of the fourth NMOS transistor 303e and the fifth NMOS transistor 303f of the summing circuits 303a to 303h. Since the same current of size Iss / 2 flows into the drain of the 2 PMOS transistor 301d, the output voltage is increased and the offset voltage of the negative polarity is compensated.

On the other hand, Figures 5a to 5c is a view showing a simulation result according to the present invention.

5A is a diagram illustrating an output buffer 500 modeled according to the present invention. A simulation performed through the modeled output buffer 500 is performed under a condition of a power supply voltage VDD of 10V and a ground voltage of 0V. An offset voltage of 20mV was applied arbitrarily, and the capacitance of the capacitor (coff) constituting the SOM device and the data line was modeled as 50pF.

5B and 5C show waveforms of the offset voltage and the output voltage measured at the output node B of the output buffer 500 shown in FIG. 5A.

As shown in FIG. 5B, as a result of using the output buffer circuit according to the present invention, it can be seen that the offset voltage is reduced to 5 mV. As shown in FIG. 5C, as the offset sampling time is no longer needed, It can be seen that more time (T) for transmitting data is secured than in the prior art.

Table 1 is shown to compare the characteristics of the output buffer circuit according to the prior art and the present invention.

As shown in Table 1, the characteristics such as slew rate, open loop gain, and phase margin at the same power supply voltage VDD are almost the same as those of the conventional output buffer circuit, but according to the present invention, the offset is compared with the prior art. It can be seen that the voltage is significantly reduced and there is little time loss due to the time for compensating the offset voltage.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope of the technical spirit of the present invention for those skilled in the art to which the present invention pertains. Modifications may be made and such substitutions, changes and the like should be regarded as belonging to the following claims.

As described above, according to the output buffer circuit according to the present invention, by detecting the offset voltage, which is the difference between the input and output voltage of the data driver without a capacitor and a switch, it is fed back to the input terminal to make the output voltage equal to the input voltage Since the time required for compensating the offset voltage is not required, a large amount of time required for data transmission can be secured, thereby enabling high-speed data transmission.

In addition, as the switch is no longer needed, an error caused by the charge injection phenomenon is no longer generated, so that the full compensation of the offset voltage is achieved.

In addition, since only transistors are used instead of capacitors that occupy a large area of the output buffer circuit, the size of the output buffer circuit can be reduced.

Claims (15)

An input terminal to which an input voltage is applied to one terminal and an output voltage to the other terminal; A class AB output stage configured to increase a current flowing through the output stage when the difference between the input voltage and the output voltage is greater than zero; A floating current source for biasing the class AB output stage; A summing circuit connected to the input terminal, the floating current source, and the class AB output terminal to sum the current supplied from the input terminal and the internal current supplied from the floating current source; An offset sensing circuit connected to the input terminal and configured of a plurality of transistors to sense an offset voltage; And an offset compensating circuit connected to the input terminal and an offset sensing circuit and configured by a plurality of transistors to compensate for the offset voltage. The method of claim 1, wherein the input terminal, A first NMOS transistor to which the input voltage is applied to a gate; A first PMOS transistor to which the input voltage is applied to a gate; A second NMOS transistor to which the output voltage is applied to a gate; A second PMOS transistor to which the output voltage is applied to a gate; A third NMOS transistor for biasing the first and second NMOS transistors; And And a third PMOS transistor for biasing the first and second PMOS transistors. The method of claim 2, wherein the offset detection circuit, A sixth NMOS transistor to which the input voltage is applied to a gate; A sixth PMOS transistor to which the input voltage is applied to a gate; A seventh NMOS transistor to which the output voltage is applied to a gate; A seventh PMOS transistor to which the output voltage is applied to the gate; An eighth NMOS transistor for biasing the sixth and seventh NMOS transistors; And And an eighth PMOS transistor for biasing the sixth and seventh PMOS transistors. The method of claim 3, wherein the offset compensation circuit, A first current mirror connected to a drain of the first NMOS transistor of the input terminal; A second current mirror connected to the drain of the second NMOS transistor of the input terminal; A third current mirror connected to the drain of the first PMOS transistor of the input terminal; A fourth current mirror connected to the drain of the second PMOS transistor of the input terminal; A fifth current mirror connected to the drain of the sixth NMOS transistor of the offset sensing circuit; A sixth current mirror connected to the drain of the seventh NMOS transistor of the offset sensing circuit; A seventh current mirror connected to the drain of the sixth PMOS transistor of the offset sensing circuit; And And an eighth current mirror connected to the drain of the seventh PMOS transistor of the offset sensing circuit. The method of claim 4, wherein And the first, second, fifth and sixth current mirrors are PMOS transistors, and the third, fourth, seventh and eighth current mirrors are NMOS transistors. The method of claim 4, wherein And the drain current having the same magnitude as that of the sixth current mirror flows through the first current mirror. The method of claim 4, wherein And the drain current having the same magnitude as the drain current of the fifth current mirror flows through the second current mirror. The method of claim 4, wherein And the drain current having the same magnitude as the drain current of the eighth current mirror flows through the third current mirror. The method of claim 4, wherein And the drain current having the same magnitude as the drain current of the seventh current mirror flows through the fourth current mirror. The method of claim 2 or 3, And said offset voltage is a bipolar offset voltage. The method of claim 10, A drain current value of the first NMOS transistor is smaller than a drain current value of the second NMOS transistor, and a drain current value of the first PMOS transistor is larger than a second PMOS drain current value. Output buffer circuit. The method of claim 10, The drain current value of the sixth NMOS transistor is smaller than the drain current value of the seventh NMOS transistor, and the drain current value of the sixth PMOS transistor is larger than the seventh PMOS drain current value. Output buffer circuit. The method of claim 2 or 3, And said offset voltage is a negative offset voltage. The method of claim 13, A drain current value of the first NMOS transistor is greater than a drain current value of the second NMOS transistor, and a drain current value of the first PMOS transistor is smaller than a second PMOS drain current value. Output buffer circuit. The method of claim 13, The drain current value of the sixth NMOS transistor is greater than the drain current value of the seventh NMOS transistor, and the drain current value of the sixth PMOS transistor is smaller than the seventh PMOS drain current value. Output buffer circuit.

Images